[{"id":1780609,"web_url":"http://patchwork.ozlabs.org/comment/1780609/","msgid":"","list_archive_url":null,"date":"2017-10-05T13:11:09","subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 19/20] target/arm: Implement\n\tsecure function return","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/22/2017 12:00 PM, Peter Maydell wrote:\n> Secure function return happens when a non-secure function has been\n> called using BLXNS and so has a particular magic LR value (either\n> 0xfefffffe or 0xfeffffff). The function return via BX behaves\n> specially when the new PC value is this magic value, in the same\n> way that exception returns are handled.\n> \n> Adjust our BX excret guards so that they recognize the function\n> return magic number as well, and perform the function-return\n> unstacking in do_v7m_exception_exit().\n> \n> Signed-off-by: Peter Maydell \n\nAcked-by: Philippe Mathieu-Daudé \n\n> ---\n> target/arm/internals.h | 7 +++\n> target/arm/helper.c | 115 +++++++++++++++++++++++++++++++++++++++++++++----\n> target/arm/translate.c | 14 +++++-\n> 3 files changed, 126 insertions(+), 10 deletions(-)\n> \n> diff --git a/target/arm/internals.h b/target/arm/internals.h\n> index 1746737..43106a2 100644\n> --- a/target/arm/internals.h\n> +++ b/target/arm/internals.h\n> @@ -72,6 +72,13 @@ FIELD(V7M_EXCRET, DCRS, 5, 1)\n> FIELD(V7M_EXCRET, S, 6, 1)\n> FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */\n> \n> +/* Minimum value which is a magic number for exception return */\n> +#define EXC_RETURN_MIN_MAGIC 0xff000000\n> +/* Minimum number which is a magic number for function or exception return\n> + * when using v8M security extension\n> + */\n> +#define FNC_RETURN_MIN_MAGIC 0xfefffffe\n> +\n> /* We use a few fake FSR values for internal purposes in M profile.\n> * M profile cores don't have A/R format FSRs, but currently our\n> * get_phys_addr() code assumes A/R profile and reports failures via\n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index 30dc2a9..888fe0a 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -6167,7 +6167,17 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n> * - if the return value is a magic value, do exception return (like BX)\n> * - otherwise bit 0 of the return value is the target security state\n> */\n> - if (dest >= 0xff000000) {\n> + uint32_t min_magic;\n> +\n> + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n> + /* Covers FNC_RETURN and EXC_RETURN magic */\n> + min_magic = FNC_RETURN_MIN_MAGIC;\n> + } else {\n> + /* EXC_RETURN magic only */\n> + min_magic = EXC_RETURN_MIN_MAGIC;\n> + }\n> +\n> + if (dest >= min_magic) {\n> /* This is an exception return magic value; put it where\n> * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.\n> * Note that if we ever add gen_ss_advance() singlestep support to\n> @@ -6460,12 +6470,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n> bool exc_secure = false;\n> bool return_to_secure;\n> \n> - /* We can only get here from an EXCP_EXCEPTION_EXIT, and\n> - * gen_bx_excret() enforces the architectural rule\n> - * that jumps to magic addresses don't have magic behaviour unless\n> - * we're in Handler mode (compare pseudocode BXWritePC()).\n> + /* If we're not in Handler mode then jumps to magic exception-exit\n> + * addresses don't have magic behaviour. However for the v8M\n> + * security extensions the magic secure-function-return has to\n> + * work in thread mode too, so to avoid doing an extra check in\n> + * the generated code we allow exception-exit magic to also cause the\n> + * internal exception and bring us here in thread mode. Correct code\n> + * will never try to do this (the following insn fetch will always\n> + * fault) so we the overhead of having taken an unnecessary exception\n> + * doesn't matter.\n> */\n> - assert(arm_v7m_is_handler_mode(env));\n> + if (!arm_v7m_is_handler_mode(env)) {\n> + return;\n> + }\n> \n> /* In the spec pseudocode ExceptionReturn() is called directly\n> * from BXWritePC() and gets the full target PC value including\n> @@ -6753,6 +6770,78 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n> qemu_log_mask(CPU_LOG_INT, \"...successful exception return\\n\");\n> }\n> \n> +static bool do_v7m_function_return(ARMCPU *cpu)\n> +{\n> + /* v8M security extensions magic function return.\n> + * We may either:\n> + * (1) throw an exception (longjump)\n> + * (2) return true if we successfully handled the function return\n> + * (3) return false if we failed a consistency check and have\n> + * pended a UsageFault that needs to be taken now\n> + *\n> + * At this point the magic return value is split between env->regs[15]\n> + * and env->thumb. We don't bother to reconstitute it because we don't\n> + * need it (all values are handled the same way).\n> + */\n> + CPUARMState *env = &cpu->env;\n> + uint32_t newpc, newpsr, newpsr_exc;\n> +\n> + qemu_log_mask(CPU_LOG_INT, \"...really v7M secure function return\\n\");\n> +\n> + {\n> + bool threadmode, spsel;\n> + TCGMemOpIdx oi;\n> + ARMMMUIdx mmu_idx;\n> + uint32_t *frame_sp_p;\n> + uint32_t frameptr;\n> +\n> + /* Pull the return address and IPSR from the Secure stack */\n> + threadmode = !arm_v7m_is_handler_mode(env);\n> + spsel = env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK;\n> +\n> + frame_sp_p = get_v7m_sp_ptr(env, true, threadmode, spsel);\n> + frameptr = *frame_sp_p;\n> +\n> + /* These loads may throw an exception (for MPU faults). We want to\n> + * do them as secure, so work out what MMU index that is.\n> + */\n> + mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);\n> + oi = make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx));\n> + newpc = helper_le_ldul_mmu(env, frameptr, oi, 0);\n> + newpsr = helper_le_ldul_mmu(env, frameptr + 4, oi, 0);\n> +\n> + /* Consistency checks on new IPSR */\n> + newpsr_exc = newpsr & XPSR_EXCP;\n> + if (!((env->v7m.exception == 0 && newpsr_exc == 0) ||\n> + (env->v7m.exception == 1 && newpsr_exc != 0))) {\n> + /* Pend the fault and tell our caller to take it */\n> + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;\n> + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,\n> + env->v7m.secure);\n> + qemu_log_mask(CPU_LOG_INT,\n> + \"...taking INVPC UsageFault: \"\n> + \"IPSR consistency check failed\\n\");\n> + return false;\n> + }\n> +\n> + *frame_sp_p = frameptr + 8;\n> + }\n> +\n> + /* This invalidates frame_sp_p */\n> + switch_v7m_security_state(env, true);\n> + env->v7m.exception = newpsr_exc;\n> + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;\n> + if (newpsr & XPSR_SFPA) {\n> + env->v7m.control[M_REG_S] |= R_V7M_CONTROL_SFPA_MASK;\n> + }\n> + xpsr_write(env, 0, XPSR_IT);\n> + env->thumb = newpc & 1;\n> + env->regs[15] = newpc & ~1;\n> +\n> + qemu_log_mask(CPU_LOG_INT, \"...function return successful\\n\");\n> + return true;\n> +}\n> +\n> static void arm_log_exception(int idx)\n> {\n> if (qemu_loglevel_mask(CPU_LOG_INT)) {\n> @@ -7034,8 +7123,18 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)\n> case EXCP_IRQ:\n> break;\n> case EXCP_EXCEPTION_EXIT:\n> - do_v7m_exception_exit(cpu);\n> - return;\n> + if (env->regs[15] < EXC_RETURN_MIN_MAGIC) {\n> + /* Must be v8M security extension function return */\n> + assert(env->regs[15] >= FNC_RETURN_MIN_MAGIC);\n> + assert(arm_feature(env, ARM_FEATURE_M_SECURITY));\n> + if (do_v7m_function_return(cpu)) {\n> + return;\n> + }\n> + } else {\n> + do_v7m_exception_exit(cpu);\n> + return;\n> + }\n> + break;\n> default:\n> cpu_abort(cs, \"Unhandled exception 0x%x\\n\", cs->exception_index);\n> return; /* Never happens. Keep compiler happy. */\n> diff --git a/target/arm/translate.c b/target/arm/translate.c\n> index 53694bb..f5cca07 100644\n> --- a/target/arm/translate.c\n> +++ b/target/arm/translate.c\n> @@ -960,7 +960,8 @@ static inline void gen_bx_excret(DisasContext *s, TCGv_i32 var)\n> * s->base.is_jmp that we need to do the rest of the work later.\n> */\n> gen_bx(s, var);\n> - if (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M)) {\n> + if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY) ||\n> + (s->v7m_handler_mode && arm_dc_feature(s, ARM_FEATURE_M))) {\n> s->base.is_jmp = DISAS_BX_EXCRET;\n> }\n> }\n> @@ -969,9 +970,18 @@ static inline void gen_bx_excret_final_code(DisasContext *s)\n> {\n> /* Generate the code to finish possible exception return and end the TB */\n> TCGLabel *excret_label = gen_new_label();\n> + uint32_t min_magic;\n> +\n> + if (arm_dc_feature(s, ARM_FEATURE_M_SECURITY)) {\n> + /* Covers FNC_RETURN and EXC_RETURN magic */\n> + min_magic = FNC_RETURN_MIN_MAGIC;\n> + } else {\n> + /* EXC_RETURN magic only */\n> + min_magic = EXC_RETURN_MIN_MAGIC;\n> + }\n> \n> /* Is the new PC value in the magic range indicating exception return? */\n> - tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], 0xff000000, excret_label);\n> + tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);\n> /* No: end the TB as we would for a DISAS_JMP */\n> if (is_singlestepping(s)) {\n> gen_singlestep_exception(s);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-20-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::242","Subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 19/20] target/arm: Implement\n\tsecure function return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780922,"web_url":"http://patchwork.ozlabs.org/comment/1780922/","msgid":"<0cc6a4e4-184b-6452-f9f2-d52c92b21350@linaro.org>","list_archive_url":null,"date":"2017-10-05T19:00:47","subject":"Re: [Qemu-devel] [PATCH 19/20] target/arm: Implement secure\n\tfunction return","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> Secure function return happens when a non-secure function has been\n> called using BLXNS and so has a particular magic LR value (either\n> 0xfefffffe or 0xfeffffff). The function return via BX behaves\n> specially when the new PC value is this magic value, in the same\n> way that exception returns are handled.\n> \n> Adjust our BX excret guards so that they recognize the function\n> return magic number as well, and perform the function-return\n> unstacking in do_v7m_exception_exit().\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/internals.h | 7 +++\n> target/arm/helper.c | 115 +++++++++++++++++++++++++++++++++++++++++++++----\n> target/arm/translate.c | 14 +++++-\n> 3 files changed, 126 insertions(+), 10 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"gJfbAJlG\"; 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\n\tThu, 05 Oct 2017 12:00:50 -0700 (PDT)","To":"Peter Maydell , qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-20-git-send-email-peter.maydell@linaro.org>","From":"Richard Henderson ","Message-ID":"<0cc6a4e4-184b-6452-f9f2-d52c92b21350@linaro.org>","Date":"Thu, 5 Oct 2017 15:00:47 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-20-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::22d","Subject":"Re: [Qemu-devel] [PATCH 19/20] target/arm: Implement secure\n\tfunction return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]