[{"id":1780899,"web_url":"http://patchwork.ozlabs.org/comment/1780899/","msgid":"<562a5db1-ab3b-1d77-eb8e-69af276bcac3@linaro.org>","list_archive_url":null,"date":"2017-10-05T18:39:33","subject":"Re: [Qemu-devel] [PATCH 14/20] target/arm: Implement security\n\tattribute lookups for memory accesses","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> Implement the security attribute lookups for memory accesses\n> in the get_phys_addr() functions, causing these to generate\n> various kinds of SecureFault for bad accesses.\n> \n> The major subtlety in this code relates to handling of the\n> case when the security attributes the SAU assigns to the\n> address don't match the current security state of the CPU.\n> \n> In the ARM ARM pseudocode for validating instruction\n> accesses, the security attributes of the address determine\n> whether the Secure or NonSecure MPU state is used. At face\n> value, handling this would require us to encode the relevant\n> bits of state into mmu_idx for both S and NS at once, which\n> would result in our needing 16 mmu indexes. Fortunately we\n> don't actually need to do this because a mismatch between\n> address attributes and CPU state means either:\n> * some kind of fault (usually a SecureFault, but in theory\n> perhaps a UserFault for unaligned access to Device memory)\n> * execution of the SG instruction in NS state from a\n> Secure & NonSecure code region\n> \n> The purpose of SG is simply to flip the CPU into Secure\n> state, so we can handle it by emulating execution of that\n> instruction directly in arm_v7m_cpu_do_interrupt(), which\n> means we can treat all the mismatch cases as \"throw an\n> exception\" and we don't need to encode the state of the\n> other MPU bank into our mmu_idx values.\n> \n> This commit doesn't include the actual emulation of SG;\n> it also doesn't include implementation of the IDAU, which\n> is a per-board way to specify hard-coded memory attributes\n> for addresses, which override the CPU-internal SAU if they\n> specify a more secure setting than the SAU is programmed to.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/internals.h | 15 ++++\n> target/arm/helper.c | 182 ++++++++++++++++++++++++++++++++++++++++++++++++-\n> 2 files changed, 195 insertions(+), 2 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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