[{"id":1773787,"web_url":"http://patchwork.ozlabs.org/comment/1773787/","msgid":"","list_archive_url":null,"date":"2017-09-22T17:18:26","subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 17/20] target/arm: Implement SG\n\tinstruction","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 22 September 2017 at 16:00, Peter Maydell wrote:\n> Implement the SG instruction, which we emulate 'by hand' in the\n> exception handling code path.\n\nI've just realised that this patch is correct as far as it goes\nbut it only implements the common path case for SG (where it is\nin S&NSC memory and executed by a CPU in NS state). There is\nalso defined behaviour for:\n * SG in NS memory (behaves as a NOP)\n * SG in S memory and CPU already secure (clears IT bits and\n does nothing else)\n\nThose can be implemented in translate.c in the usual way;\nI'll put a patch for that in the next set (or in a respin\nof this set).\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"jmc7KF41\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzKwN1MC4z9sP1\n\tfor ;\n\tSat, 23 Sep 2017 03:19:31 +1000 (AEST)","from localhost ([::1]:60304 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dvRbt-0008Hp-Em\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22f","Subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 17/20] target/arm: Implement SG\n\tinstruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780910,"web_url":"http://patchwork.ozlabs.org/comment/1780910/","msgid":"","list_archive_url":null,"date":"2017-10-05T18:50:17","subject":"Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> Implement the SG instruction, which we emulate 'by hand' in the\n> exception handling code path.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/helper.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++++--\n> 1 file changed, 124 insertions(+), 5 deletions(-)\n> \n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index b1ecb66..8df819d 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -41,6 +41,10 @@ typedef struct V8M_SAttributes {\n> bool irvalid;\n> } V8M_SAttributes;\n> \n> +static void v8m_security_lookup(CPUARMState *env, uint32_t address,\n> + MMUAccessType access_type, ARMMMUIdx mmu_idx,\n> + V8M_SAttributes *sattrs);\n> +\n> /* Definitions for the PMCCNTR and PMCR registers */\n> #define PMCRD 0x8\n> #define PMCRC 0x4\n> @@ -6724,6 +6728,123 @@ static void arm_log_exception(int idx)\n> }\n> }\n> \n> +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, uint16_t *insn)\n> +{\n\nThis function doesn't take an address ...\n\n> + if (get_phys_addr(env, env->regs[15], MMU_INST_FETCH, mmu_idx,\n> + &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {\n\n... reading it directly from r15 ...\n\n> + if (insn != 0xe97f) {\n> + /* Not an SG instruction first half (we choose the IMPDEF\n> + * early-SG-check option).\n> + */\n> + goto gen_invep;\n> + }\n> +\n> + if (!v7m_read_half_insn(cpu, mmu_idx, &insn)) {\n> + return false;\n> + }\n> +\n> + if (insn != 0xe97f) {\n> + /* Not an SG instruction second half */\n> + goto gen_invep;\n> + }\n\n... but somehow expects to get two different values read from the same address?\n\nCertainly you'd get the wrong exception frame if you incremented r15 in between.\n\n> + env->regs[15] += 4;\n\n... that make this right and the implicit address to the readers wrong.\n\nI don't see anything else amiss in the patch.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-18-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::233","Subject":"Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780912,"web_url":"http://patchwork.ozlabs.org/comment/1780912/","msgid":"","list_archive_url":null,"date":"2017-10-05T18:55:53","subject":"Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 5 October 2017 at 19:50, Richard Henderson\n wrote:\n> On 09/22/2017 11:00 AM, Peter Maydell wrote:\n>> Implement the SG instruction, which we emulate 'by hand' in the\n>> exception handling code path.\n>>\n>> Signed-off-by: Peter Maydell \n>> ---\n>> target/arm/helper.c | 129 ++++++++++++++++++++++++++++++++++++++++++++++++++--\n>> 1 file changed, 124 insertions(+), 5 deletions(-)\n>>\n>> diff --git a/target/arm/helper.c b/target/arm/helper.c\n>> index b1ecb66..8df819d 100644\n>> --- a/target/arm/helper.c\n>> +++ b/target/arm/helper.c\n>> @@ -41,6 +41,10 @@ typedef struct V8M_SAttributes {\n>> bool irvalid;\n>> } V8M_SAttributes;\n>>\n>> +static void v8m_security_lookup(CPUARMState *env, uint32_t address,\n>> + MMUAccessType access_type, ARMMMUIdx mmu_idx,\n>> + V8M_SAttributes *sattrs);\n>> +\n>> /* Definitions for the PMCCNTR and PMCR registers */\n>> #define PMCRD 0x8\n>> #define PMCRC 0x4\n>> @@ -6724,6 +6728,123 @@ static void arm_log_exception(int idx)\n>> }\n>> }\n>>\n>> +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, uint16_t *insn)\n>> +{\n>\n> This function doesn't take an address ...\n>\n>> + if (get_phys_addr(env, env->regs[15], MMU_INST_FETCH, mmu_idx,\n>> + &physaddr, &attrs, &prot, &page_size, &fsr, &fi)) {\n>\n> ... reading it directly from r15 ...\n>\n>> + if (insn != 0xe97f) {\n>> + /* Not an SG instruction first half (we choose the IMPDEF\n>> + * early-SG-check option).\n>> + */\n>> + goto gen_invep;\n>> + }\n>> +\n>> + if (!v7m_read_half_insn(cpu, mmu_idx, &insn)) {\n>> + return false;\n>> + }\n>> +\n>> + if (insn != 0xe97f) {\n>> + /* Not an SG instruction second half */\n>> + goto gen_invep;\n>> + }\n>\n> ... but somehow expects to get two different values read from the same address?\n>\n> Certainly you'd get the wrong exception frame if you incremented r15 in between.\n\nOops. I missed this in my testing because it happens that the\ntwo halves of an SG instruction are the same value :-)\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Cqq9zSXF\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7MSg6rg0z9sRm\n\tfor ;\n\tFri, 6 Oct 2017 05:56:50 +1100 (AEDT)","from localhost ([::1]:41622 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0BKC-0003o8-64\n\tfor incoming@patchwork.ozlabs.org; Thu, 05 Oct 2017 14:56:48 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:50590)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1e0BJg-0003n2-G5\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 14:56:17 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1e0BJf-0004lw-LG\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 14:56:16 -0400","from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:47510)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1e0BJf-0004kp-Dt\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 14:56:15 -0400","by mail-wm0-x235.google.com with SMTP id t69so3787887wmt.2\n\tfor ; Thu, 05 Oct 2017 11:56:15 -0700 (PDT)","by 10.223.128.207 with HTTP; Thu, 5 Oct 2017 11:55:53 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=tdCHoxfI67I5+7Zgmrpx4IodMKUBY05vefaUyWuEYtE=;\n\tb=Cqq9zSXFA59J0GGrvrGHqDQRykprnYzCs89VhVjWR1vQ8ADc9Yd7LUOCbUlra461lY\n\tl+uvaIjhEUoWgKAhxvoyoq+hF+288SjtX1N39IBm0lPWedQN73m0NohhHs5Sj1QzfEu+\n\tB9N/wrH8AOjhEuB9Asia2Zjx3Dto6ZN/+8xa8=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=tdCHoxfI67I5+7Zgmrpx4IodMKUBY05vefaUyWuEYtE=;\n\tb=dlBe5s9x7EenC6aBB+lBo9uIYtuPnZuVxd2IL+UOnkQExvHe2ENf7KIdTCv8zxSPNg\n\teZT6pNpigSYYiamw1p0dHkE2K98Mh2ibvfJF3/pp2cwYkBd35RCTB7IT7kKxXCfPdVdX\n\tTdBG7hwwn1bgsliLHM/YTagbPw8C/n8EDq92oKjtXHKrBowxBOdu7v5X41wsoGa49xiY\n\tMq0kPr+A0R8UfObRLtHOYNipkAsAdqHRDKVbQRuXME0ssoprB+H27W3KnCCCub4M9A21\n\txM7yAhcsAZXwYLfktIg9fX47PEbdMg+AeEMa9GqQ1HLQ0dR4d7rDVXJAA6maqkkTR4xu\n\t6VeA==","X-Gm-Message-State":"AMCzsaXNk4GnJcHL+r31fzVZGlZQlBQLD1VTeWyEmucgYUKXYqhDZLKl\n\tPV8uLmP48nT3c+E4fSRHiO3J2Klci3kG9IkEed+ivg==","X-Google-Smtp-Source":"AOwi7QBgaNjO1zGwnJjqNnXQlKQsPDQ/KhdZFezt1WpYrsFW0KV6L9YunCuKGHj0Eztx+jmlwcViUkAmauO0rLX4+2I=","X-Received":"by 10.28.236.203 with SMTP id h72mr63495wmi.147.1507229774012;\n\tThu, 05 Oct 2017 11:56:14 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-18-git-send-email-peter.maydell@linaro.org>\n\t","From":"Peter Maydell ","Date":"Thu, 5 Oct 2017 19:55:53 +0100","Message-ID":"","To":"Richard Henderson ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::235","Subject":"Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\t\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780913,"web_url":"http://patchwork.ozlabs.org/comment/1780913/","msgid":"","list_archive_url":null,"date":"2017-10-05T18:57:08","subject":"Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 10/05/2017 02:55 PM, Peter Maydell wrote:\n> Oops. I missed this in my testing because it happens that the\n> two halves of an SG instruction are the same value :-)\n\nHah. I didn't notice that either.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Em0ttd5T\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7MTr134Rz9s4s\n\tfor ;\n\tFri, 6 Oct 2017 05:57:52 +1100 (AEDT)","from localhost ([::1]:41625 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0BLC-0004Sw-6z\n\tfor incoming@patchwork.ozlabs.org; Thu, 05 Oct 2017 14:57:50 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:50863)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1e0BKa-0004RR-QV\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 14:57:13 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1e0BKa-0005ct-4D\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 14:57:12 -0400","from mail-qt0-x22f.google.com ([2607:f8b0:400d:c0d::22f]:46517)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1e0BKZ-0005cK-V7\n\tfor qemu-devel@nongnu.org; Thu, 05 Oct 2017 14:57:12 -0400","by mail-qt0-x22f.google.com with SMTP id 6so18183522qtw.3\n\tfor ; Thu, 05 Oct 2017 11:57:11 -0700 (PDT)","from bigtime.twiddle.net ([2606:a000:7a4a:b100::1b])\n\tby smtp.gmail.com with ESMTPSA id\n\ts187sm9032034yws.55.2017.10.05.11.57.10\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 05 Oct 2017 11:57:10 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=VxQ5h7Z62FM3zcw7/x6JJMkZgaOypQSZj6tBXPlZH2E=;\n\tb=Em0ttd5TBgjRRoYSaE5YXGev8D2CmGqQRYJb6xHR2DR2qitufZsRTO5g2126+eWUu5\n\tq974cfXb/isrx0pTC7Zzj54PzbVqV6EJMwcLXz1ReKYGh8MEqs74f8Fknq83OwKRhZlz\n\tuXk+38ezvM7pn1gtS050iROsSYz0FaPkTsmRk=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=VxQ5h7Z62FM3zcw7/x6JJMkZgaOypQSZj6tBXPlZH2E=;\n\tb=cc2ZZV6+0Wm2fK+0s8M+3+oANpct83J9azCQXQ166Ytw6W0p8EvH4hWrJwk3ld73IJ\n\tK9HxoRaTqoJzm32jLjeSFFl/yNv4H0+Kd4X9kfDRQ0Ty/a3yZiRpB4MVN2n14a1trZiE\n\tB++6GRZ6fOylnGYbfCkhzO9v7uOnPJATzJmS8O4pgM4NQUFUEaCNxmgQdLeWPcju1I6v\n\tNP7EKMy66blLXF5Yk1+ZPtzVUndCNh9zvEHBDF1cuUhWoRQ+RbjiQlizyNkzRv/+xHmp\n\t0G9CHdKWhc4EsY1AZxHqr0EoE37+o6OdGeWKamd7OK4SoSNJwZLBg+6Fj3CNyD7OwGXl\n\tIldg==","X-Gm-Message-State":"AMCzsaVbF/XGfYrVfUwl/IcuyaKoRYPllbkt3WIxAANUiQYoRXV/82A0\n\twzBenFIa4iUL+sJej4HA2KFsEg==","X-Google-Smtp-Source":"AOwi7QDN+jQv3+E71ao2zoUdbIMbczenJc/3Nm3tPpLK4NKZcR5h+hwNOkw0wXz9EXJXbljJ1pntww==","X-Received":"by 10.37.65.148 with SMTP id o142mr7475233yba.275.1507229831331; \n\tThu, 05 Oct 2017 11:57:11 -0700 (PDT)","To":"Peter Maydell ","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-18-git-send-email-peter.maydell@linaro.org>\n\t\n\t","From":"Richard Henderson ","Message-ID":"","Date":"Thu, 5 Oct 2017 14:57:08 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::22f","Subject":"Re: [Qemu-devel] [PATCH 17/20] target/arm: Implement SG instruction","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\t\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]