[{"id":1780276,"web_url":"http://patchwork.ozlabs.org/comment/1780276/","msgid":"","list_archive_url":null,"date":"2017-10-05T04:33:01","subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 20/20] nvic: Add missing code\n\tfor writing SHCSR.HARDFAULTPENDED bit","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/22/2017 12:00 PM, Peter Maydell wrote:\n> When we added support for the new SHCSR bits in v8M in commit\n> 437d59c17e9 the code to support writing to the new HARDFAULTPENDED\n> bit was accidentally only added for non-secure writes; the\n> secure banked version of the bit should also be writable.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> hw/intc/armv7m_nvic.c | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\n> index bd1d5d3..22d5e6e 100644\n> --- a/hw/intc/armv7m_nvic.c\n> +++ b/hw/intc/armv7m_nvic.c\n> @@ -1230,6 +1230,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n\n if (attrs.secure) {\n\nif banked then arch is v8M,\n\n> s->sec_vectors[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;\n> s->sec_vectors[ARMV7M_EXCP_USAGE].enabled =\n> (value & (1 << 18)) != 0;\n> + s->sec_vectors[ARMV7M_EXCP_HARD].pending = (value & (1 << 21)) != 0;\n\ntherefore this bit is present.\n\nReviewed-by: Philippe Mathieu-Daudé \n\n> /* SecureFault not banked, but RAZ/WI to NS */\n> s->vectors[ARMV7M_EXCP_SECURE].active = (value & (1 << 4)) != 0;\n> s->vectors[ARMV7M_EXCP_SECURE].enabled = (value & (1 << 19)) != 0;\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-21-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::242","Subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 20/20] nvic: Add missing code\n\tfor writing SHCSR.HARDFAULTPENDED bit","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780923,"web_url":"http://patchwork.ozlabs.org/comment/1780923/","msgid":"<2e3d42e9-a660-6a8a-067a-f31a93ad669a@linaro.org>","list_archive_url":null,"date":"2017-10-05T19:01:20","subject":"Re: [Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing\n\tSHCSR.HARDFAULTPENDED bit","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> When we added support for the new SHCSR bits in v8M in commit\n> 437d59c17e9 the code to support writing to the new HARDFAULTPENDED\n> bit was accidentally only added for non-secure writes; the\n> secure banked version of the bit should also be writable.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> hw/intc/armv7m_nvic.c | 1 +\n> 1 file changed, 1 insertion(+)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"VvYhBS1Q\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7MZc0n2Pz9t32\n\tfor ;\n\tFri, 6 Oct 2017 06:02:00 +1100 (AEDT)","from localhost ([::1]:41645 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0BPC-0006jX-6u\n\tfor incoming@patchwork.ozlabs.org; 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\n\tThu, 05 Oct 2017 12:01:23 -0700 (PDT)","To":"Peter Maydell , qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-21-git-send-email-peter.maydell@linaro.org>","From":"Richard Henderson ","Message-ID":"<2e3d42e9-a660-6a8a-067a-f31a93ad669a@linaro.org>","Date":"Thu, 5 Oct 2017 15:01:20 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-21-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::231","Subject":"Re: [Qemu-devel] [PATCH 20/20] nvic: Add missing code for writing\n\tSHCSR.HARDFAULTPENDED bit","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]