[{"id":1780783,"web_url":"http://patchwork.ozlabs.org/comment/1780783/","msgid":"","list_archive_url":null,"date":"2017-10-05T16:18:34","subject":"Re: [Qemu-devel] [PATCH 05/20] target/arm: Restore SPSEL to correct\n\tCONTROL register on exception return","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 10:59 AM, Peter Maydell wrote:\n> On exception return for v8M, the SPSEL bit in the EXC_RETURN magic\n> value should be restored to the SPSEL bit in the CONTROL register\n> banked specified by the EXC_RETURN.ES bit.\n> \n> Add write_v7m_control_spsel_for_secstate() which behaves like\n> write_v7m_control_spsel() but allows the caller to specify which\n> CONTROL bank to use, reimplement write_v7m_control_spsel() in\n> terms of it, and use it in exception return.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/helper.c | 40 +++++++++++++++++++++++++++-------------\n> 1 file changed, 27 insertions(+), 13 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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