[{"id":1780284,"web_url":"http://patchwork.ozlabs.org/comment/1780284/","msgid":"<63505593-53ea-90ba-f2ba-72cadfd1179f@amsat.org>","list_archive_url":null,"date":"2017-10-05T04:44:25","subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/22/2017 11:59 AM, Peter Maydell wrote:\n> Currently our M profile exception return code switches to the\n> target stack pointer relatively early in the process, before\n> it tries to pop the exception frame off the stack. This is\n> awkward for v8M for two reasons:\n> * in v8M the process vs main stack pointer is not selected\n> purely by the value of CONTROL.SPSEL, so updating SPSEL\n> and relying on that to switch to the right stack pointer\n> won't work\n> * the stack we should be reading the stack frame from and\n> the stack we will eventually switch to might not be the\n> same if the guest is doing strange things\n> \n> Change our exception return code to use a 'frame pointer'\n> to read the exception frame rather than assuming that we\n> can switch the live stack pointer this early.\n> \n> Signed-off-by: Peter Maydell \n\nReviewed-by: Philippe Mathieu-Daudé \n\n> ---\n> target/arm/helper.c | 127 +++++++++++++++++++++++++++++++++++++++-------------\n> 1 file changed, 95 insertions(+), 32 deletions(-)\n> \n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index 8be78ea..f13b99d 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -6040,16 +6040,6 @@ static void v7m_push(CPUARMState *env, uint32_t val)\n> stl_phys(cs->as, env->regs[13], val);\n> }\n> \n> -static uint32_t v7m_pop(CPUARMState *env)\n> -{\n> - CPUState *cs = CPU(arm_env_get_cpu(env));\n> - uint32_t val;\n> -\n> - val = ldl_phys(cs->as, env->regs[13]);\n> - env->regs[13] += 4;\n> - return val;\n> -}\n> -\n> /* Return true if we're using the process stack pointer (not the MSP) */\n> static bool v7m_using_psp(CPUARMState *env)\n> {\n> @@ -6141,6 +6131,40 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n> env->regs[15] = dest & ~1;\n> }\n> \n> +static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n> + bool spsel)\n> +{\n> + /* Return a pointer to the location where we currently store the\n> + * stack pointer for the requested security state and thread mode.\n> + * This pointer will become invalid if the CPU state is updated\n> + * such that the stack pointers are switched around (eg changing\n> + * the SPSEL control bit).\n> + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().\n> + * Unlike that pseudocode, we require the caller to pass us in the\n> + * SPSEL control bit value; this is because we also use this\n> + * function in handling of pushing of the callee-saves registers\n> + * part of the v8M stack frame, and in that case the SPSEL bit\n> + * comes from the exception return magic LR value.\n> + */\n> + bool want_psp = threadmode && spsel;\n> +\n> + if (secure == env->v7m.secure) {\n> + /* Currently switch_v7m_sp switches SP as it updates SPSEL,\n> + * so the SP we want is always in regs[13].\n> + * When we decouple SPSEL from the actually selected SP\n> + * we need to check want_psp against v7m_using_psp()\n> + * to see whether we need regs[13] or v7m.other_sp.\n> + */\n> + return &env->regs[13];\n> + } else {\n> + if (want_psp) {\n> + return &env->v7m.other_ss_psp;\n> + } else {\n> + return &env->v7m.other_ss_msp;\n> + }\n> + }\n> +}\n> +\n> static uint32_t arm_v7m_load_vector(ARMCPU *cpu)\n> {\n> CPUState *cs = CPU(cpu);\n> @@ -6212,6 +6236,7 @@ static void v7m_push_stack(ARMCPU *cpu)\n> static void do_v7m_exception_exit(ARMCPU *cpu)\n> {\n> CPUARMState *env = &cpu->env;\n> + CPUState *cs = CPU(cpu);\n> uint32_t excret;\n> uint32_t xpsr;\n> bool ufault = false;\n> @@ -6219,6 +6244,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n> bool return_to_handler = false;\n> bool rettobase = false;\n> bool exc_secure = false;\n> + bool return_to_secure;\n> \n> /* We can only get here from an EXCP_EXCEPTION_EXIT, and\n> * gen_bx_excret() enforces the architectural rule\n> @@ -6286,6 +6312,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n> g_assert_not_reached();\n> }\n> \n> + return_to_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&\n> + (excret & R_V7M_EXCRET_S_MASK);\n> +\n> switch (excret & 0xf) {\n> case 1: /* Return to Handler */\n> return_to_handler = true;\n> @@ -6315,32 +6344,66 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n> return;\n> }\n> \n> - /* Switch to the target stack. */\n> + /* Set CONTROL.SPSEL from excret.SPSEL. For QEMU this currently\n> + * causes us to switch the active SP, but we will change this\n> + * later to not do that so we can support v8M.\n> + */\n> switch_v7m_sp(env, return_to_sp_process);\n> - /* Pop registers. */\n> - env->regs[0] = v7m_pop(env);\n> - env->regs[1] = v7m_pop(env);\n> - env->regs[2] = v7m_pop(env);\n> - env->regs[3] = v7m_pop(env);\n> - env->regs[12] = v7m_pop(env);\n> - env->regs[14] = v7m_pop(env);\n> - env->regs[15] = v7m_pop(env);\n> - if (env->regs[15] & 1) {\n> - qemu_log_mask(LOG_GUEST_ERROR,\n> - \"M profile return from interrupt with misaligned \"\n> - \"PC is UNPREDICTABLE\\n\");\n> - /* Actual hardware seems to ignore the lsbit, and there are several\n> - * RTOSes out there which incorrectly assume the r15 in the stack\n> - * frame should be a Thumb-style \"lsbit indicates ARM/Thumb\" value.\n> +\n> + {\n> + /* The stack pointer we should be reading the exception frame from\n> + * depends on bits in the magic exception return type value (and\n> + * for v8M isn't necessarily the stack pointer we will eventually\n> + * end up resuming execution with). Get a pointer to the location\n> + * in the CPU state struct where the SP we need is currently being\n> + * stored; we will use and modify it in place.\n> + * We use this limited C variable scope so we don't accidentally\n> + * use 'frame_sp_p' after we do something that makes it invalid.\n> + */\n> + uint32_t *frame_sp_p = get_v7m_sp_ptr(env,\n> + return_to_secure,\n> + !return_to_handler,\n> + return_to_sp_process);\n> + uint32_t frameptr = *frame_sp_p;\n> +\n> + /* Pop registers. TODO: make these accesses use the correct\n> + * attributes and address space (S/NS, priv/unpriv) and handle\n> + * memory transaction failures.\n> */\n> - env->regs[15] &= ~1U;\n> + env->regs[0] = ldl_phys(cs->as, frameptr);\n> + env->regs[1] = ldl_phys(cs->as, frameptr + 0x4);\n> + env->regs[2] = ldl_phys(cs->as, frameptr + 0x8);\n> + env->regs[3] = ldl_phys(cs->as, frameptr + 0xc);\n> + env->regs[12] = ldl_phys(cs->as, frameptr + 0x10);\n> + env->regs[14] = ldl_phys(cs->as, frameptr + 0x14);\n> + env->regs[15] = ldl_phys(cs->as, frameptr + 0x18);\n> + if (env->regs[15] & 1) {\n> + qemu_log_mask(LOG_GUEST_ERROR,\n> + \"M profile return from interrupt with misaligned \"\n> + \"PC is UNPREDICTABLE\\n\");\n> + /* Actual hardware seems to ignore the lsbit, and there are several\n> + * RTOSes out there which incorrectly assume the r15 in the stack\n> + * frame should be a Thumb-style \"lsbit indicates ARM/Thumb\" value.\n> + */\n> + env->regs[15] &= ~1U;\n> + }\n> + xpsr = ldl_phys(cs->as, frameptr + 0x1c);\n> +\n> + /* Commit to consuming the stack frame */\n> + frameptr += 0x20;\n> + /* Undo stack alignment (the SPREALIGN bit indicates that the original\n> + * pre-exception SP was not 8-aligned and we added a padding word to\n> + * align it, so we undo this by ORing in the bit that increases it\n> + * from the current 8-aligned value to the 8-unaligned value. (Adding 4\n> + * would work too but a logical OR is how the pseudocode specifies it.)\n> + */\n> + if (xpsr & XPSR_SPREALIGN) {\n> + frameptr |= 4;\n> + }\n> + *frame_sp_p = frameptr;\n> }\n> - xpsr = v7m_pop(env);\n> + /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */\n> xpsr_write(env, xpsr, ~XPSR_SPREALIGN);\n> - /* Undo stack alignment. */\n> - if (xpsr & XPSR_SPREALIGN) {\n> - env->regs[13] |= 4;\n> - }\n> \n> /* The restored xPSR exception field will be zero if we're\n> * resuming in Thread mode. If that doesn't match what the\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BCT+yqL7\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y70Yr6PGkz9t3k\n\tfor ;\n\tThu, 5 Oct 2017 15:45:04 +1100 (AEDT)","from localhost ([::1]:37760 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dzy1v-0000kg-2K\n\tfor incoming@patchwork.ozlabs.org; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-3-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::243","Subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780773,"web_url":"http://patchwork.ozlabs.org/comment/1780773/","msgid":"","list_archive_url":null,"date":"2017-10-05T16:04:43","subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 10:59 AM, Peter Maydell wrote:\n> Currently our M profile exception return code switches to the\n> target stack pointer relatively early in the process, before\n> it tries to pop the exception frame off the stack. This is\n> awkward for v8M for two reasons:\n> * in v8M the process vs main stack pointer is not selected\n> purely by the value of CONTROL.SPSEL, so updating SPSEL\n> and relying on that to switch to the right stack pointer\n> won't work\n> * the stack we should be reading the stack frame from and\n> the stack we will eventually switch to might not be the\n> same if the guest is doing strange things\n> \n> Change our exception return code to use a 'frame pointer'\n> to read the exception frame rather than assuming that we\n> can switch the live stack pointer this early.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/helper.c | 127 +++++++++++++++++++++++++++++++++++++++-------------\n> 1 file changed, 95 insertions(+), 32 deletions(-)\n> \n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index 8be78ea..f13b99d 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -6040,16 +6040,6 @@ static void v7m_push(CPUARMState *env, uint32_t val)\n> stl_phys(cs->as, env->regs[13], val);\n> }\n> \n> -static uint32_t v7m_pop(CPUARMState *env)\n> -{\n> - CPUState *cs = CPU(arm_env_get_cpu(env));\n> - uint32_t val;\n> -\n> - val = ldl_phys(cs->as, env->regs[13]);\n> - env->regs[13] += 4;\n> - return val;\n> -}\n> -\n> /* Return true if we're using the process stack pointer (not the MSP) */\n> static bool v7m_using_psp(CPUARMState *env)\n> {\n> @@ -6141,6 +6131,40 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n> env->regs[15] = dest & ~1;\n> }\n> \n> +static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n> + bool spsel)\n> +{\n> + /* Return a pointer to the location where we currently store the\n> + * stack pointer for the requested security state and thread mode.\n> + * This pointer will become invalid if the CPU state is updated\n> + * such that the stack pointers are switched around (eg changing\n> + * the SPSEL control bit).\n> + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().\n> + * Unlike that pseudocode, we require the caller to pass us in the\n> + * SPSEL control bit value; this is because we also use this\n> + * function in handling of pushing of the callee-saves registers\n> + * part of the v8M stack frame, and in that case the SPSEL bit\n> + * comes from the exception return magic LR value.\n\nException return magic lr value does not appear to match \"pushing\". Did you\nmean \"poping\" here?\n\nOtherwise,\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Mg2zLoLi\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7HgL4xrGz9sPt\n\tfor ;\n\tFri, 6 Oct 2017 03:05:49 +1100 (AEDT)","from localhost ([::1]:40673 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e08ef-00035K-HH\n\tfor incoming@patchwork.ozlabs.org; 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\n\tThu, 05 Oct 2017 09:04:46 -0700 (PDT)","To":"Peter Maydell , qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-3-git-send-email-peter.maydell@linaro.org>","From":"Richard Henderson ","Message-ID":"","Date":"Thu, 5 Oct 2017 12:04:43 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-3-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::233","Subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780786,"web_url":"http://patchwork.ozlabs.org/comment/1780786/","msgid":"","list_archive_url":null,"date":"2017-10-05T16:20:28","subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 5 October 2017 at 17:04, Richard Henderson\n wrote:\n> On 09/22/2017 10:59 AM, Peter Maydell wrote:\n>> Currently our M profile exception return code switches to the\n>> target stack pointer relatively early in the process, before\n>> it tries to pop the exception frame off the stack. This is\n>> awkward for v8M for two reasons:\n>> * in v8M the process vs main stack pointer is not selected\n>> purely by the value of CONTROL.SPSEL, so updating SPSEL\n>> and relying on that to switch to the right stack pointer\n>> won't work\n>> * the stack we should be reading the stack frame from and\n>> the stack we will eventually switch to might not be the\n>> same if the guest is doing strange things\n>>\n>> Change our exception return code to use a 'frame pointer'\n>> to read the exception frame rather than assuming that we\n>> can switch the live stack pointer this early.\n>>\n>> Signed-off-by: Peter Maydell \n>> ---\n>> target/arm/helper.c | 127 +++++++++++++++++++++++++++++++++++++++-------------\n>> 1 file changed, 95 insertions(+), 32 deletions(-)\n>>\n>> diff --git a/target/arm/helper.c b/target/arm/helper.c\n>> index 8be78ea..f13b99d 100644\n>> --- a/target/arm/helper.c\n>> +++ b/target/arm/helper.c\n>> @@ -6040,16 +6040,6 @@ static void v7m_push(CPUARMState *env, uint32_t val)\n>> stl_phys(cs->as, env->regs[13], val);\n>> }\n>>\n>> -static uint32_t v7m_pop(CPUARMState *env)\n>> -{\n>> - CPUState *cs = CPU(arm_env_get_cpu(env));\n>> - uint32_t val;\n>> -\n>> - val = ldl_phys(cs->as, env->regs[13]);\n>> - env->regs[13] += 4;\n>> - return val;\n>> -}\n>> -\n>> /* Return true if we're using the process stack pointer (not the MSP) */\n>> static bool v7m_using_psp(CPUARMState *env)\n>> {\n>> @@ -6141,6 +6131,40 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)\n>> env->regs[15] = dest & ~1;\n>> }\n>>\n>> +static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n>> + bool spsel)\n>> +{\n>> + /* Return a pointer to the location where we currently store the\n>> + * stack pointer for the requested security state and thread mode.\n>> + * This pointer will become invalid if the CPU state is updated\n>> + * such that the stack pointers are switched around (eg changing\n>> + * the SPSEL control bit).\n>> + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().\n>> + * Unlike that pseudocode, we require the caller to pass us in the\n>> + * SPSEL control bit value; this is because we also use this\n>> + * function in handling of pushing of the callee-saves registers\n>> + * part of the v8M stack frame, and in that case the SPSEL bit\n>> + * comes from the exception return magic LR value.\n>\n> Exception return magic lr value does not appear to match \"pushing\". Did you\n> mean \"poping\" here?\n\nNo, because the code creates the exception magic LR value for an\nexception entry, and then uses it to determine which SPSEL to use.\nIn the tailchained-exception case we use the magic LR that\nthe attempted exception-exit got when figuring out where we need\nto push more registers as part of the tailchaining. The pseudocode\nchooses to open-code the \"find the right stack pointer\" for that\ncodepath (in pseudocode function PushCalleeStack), whereas for this\nQEMU code I opted to make the utility function more specific. That's\nwhat this comment is trying to gesture at.\n\n[The push-on-exception-entry code is in \"target/arm: Add v8M support\nto exception entry code\"]\n\n> Otherwise,\n> Reviewed-by: Richard Henderson \n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"CB/2gmOY\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7J1C4pmcz9sRm\n\tfor ;\n\tFri, 6 Oct 2017 03:21:15 +1100 (AEDT)","from localhost ([::1]:40744 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e08tc-0001cv-IS\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::236","Subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\t\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1781635,"web_url":"http://patchwork.ozlabs.org/comment/1781635/","msgid":"","list_archive_url":null,"date":"2017-10-06T13:22:21","subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 5 October 2017 at 17:20, Peter Maydell wrote:\n> On 5 October 2017 at 17:04, Richard Henderson\n> wrote:\n>> On 09/22/2017 10:59 AM, Peter Maydell wrote:\n>>> +static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n>>> + bool spsel)\n>>> +{\n>>> + /* Return a pointer to the location where we currently store the\n>>> + * stack pointer for the requested security state and thread mode.\n>>> + * This pointer will become invalid if the CPU state is updated\n>>> + * such that the stack pointers are switched around (eg changing\n>>> + * the SPSEL control bit).\n>>> + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().\n>>> + * Unlike that pseudocode, we require the caller to pass us in the\n>>> + * SPSEL control bit value; this is because we also use this\n>>> + * function in handling of pushing of the callee-saves registers\n>>> + * part of the v8M stack frame, and in that case the SPSEL bit\n>>> + * comes from the exception return magic LR value.\n>>\n>> Exception return magic lr value does not appear to match \"pushing\". Did you\n>> mean \"poping\" here?\n>\n> No, because the code creates the exception magic LR value for an\n> exception entry, and then uses it to determine which SPSEL to use.\n> In the tailchained-exception case we use the magic LR that\n> the attempted exception-exit got when figuring out where we need\n> to push more registers as part of the tailchaining. The pseudocode\n> chooses to open-code the \"find the right stack pointer\" for that\n> codepath (in pseudocode function PushCalleeStack), whereas for this\n> QEMU code I opted to make the utility function more specific. That's\n> what this comment is trying to gesture at.\n>\n> [The push-on-exception-entry code is in \"target/arm: Add v8M support\n> to exception entry code\"]\n\nI'm going to change this part of the comment to read\n * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().\n * Unlike that pseudocode, we require the caller to pass us in the\n * SPSEL control bit value; this is because we also use this\n * function in handling of pushing of the callee-saves registers\n * part of the v8M stack frame (pseudocode PushCalleeStack()),\n * and in the tailchain codepath the SPSEL bit comes from the exception\n * return magic LR value from the previous exception. The pseudocode\n * opencodes the stack-selection in PushCalleeStack(), but we prefer\n * to make this utility function generic enough to do the job.\n\nwhich hopefully is a little clearer.\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"fkNogQOA\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7r1P6FvJz9t34\n\tfor ;\n\tSat, 7 Oct 2017 00:23:20 +1100 (AEDT)","from localhost ([::1]:44906 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0Sb0-0004Ba-En\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::234","Subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\t\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1781637,"web_url":"http://patchwork.ozlabs.org/comment/1781637/","msgid":"","list_archive_url":null,"date":"2017-10-06T13:24:29","subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 10/06/2017 09:22 AM, Peter Maydell wrote:\n> I'm going to change this part of the comment to read\n> * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().\n> * Unlike that pseudocode, we require the caller to pass us in the\n> * SPSEL control bit value; this is because we also use this\n> * function in handling of pushing of the callee-saves registers\n> * part of the v8M stack frame (pseudocode PushCalleeStack()),\n> * and in the tailchain codepath the SPSEL bit comes from the exception\n> * return magic LR value from the previous exception. The pseudocode\n> * opencodes the stack-selection in PushCalleeStack(), but we prefer\n> * to make this utility function generic enough to do the job.\n> \n> which hopefully is a little clearer.\n\nMuch, thanks.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"CoAOCEHi\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7r3T6lrCz9t34\n\tfor ;\n\tSat, 7 Oct 2017 00:25:09 +1100 (AEDT)","from localhost ([::1]:44915 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0Scl-0005Kn-WF\n\tfor incoming@patchwork.ozlabs.org; Fri, 06 Oct 2017 09:25:08 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34655)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1e0ScE-0005Ja-95\n\tfor qemu-devel@nongnu.org; Fri, 06 Oct 2017 09:24:35 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1e0ScD-0005xT-CI\n\tfor qemu-devel@nongnu.org; Fri, 06 Oct 2017 09:24:34 -0400","from mail-qt0-x230.google.com ([2607:f8b0:400d:c0d::230]:49047)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1e0ScD-0005x9-7e\n\tfor qemu-devel@nongnu.org; Fri, 06 Oct 2017 09:24:33 -0400","by mail-qt0-x230.google.com with SMTP id d13so30651225qta.5\n\tfor ; Fri, 06 Oct 2017 06:24:33 -0700 (PDT)","from bigtime.twiddle.net ([2606:a000:7a4a:b100::1b])\n\tby smtp.gmail.com with ESMTPSA id\n\tb138sm2275315ywa.37.2017.10.06.06.24.31\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 06 Oct 2017 06:24:31 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=zeyloMazLX4NnLlH1MJoyG9juXBNJrjhCgAN5P2uOtc=;\n\tb=CoAOCEHiVJCpqyhXovlQWUoiLUye5VrmrA+0kMr4L4cQtPzLj4CuZkc7m3VNQfMvc8\n\tcKtgubqxy7vsZRxhCxwR893byJffNmoqeUazrSDjQjkw+rjhd+KGGJqKWB9/0+t/TKdl\n\t7mDYgzJcZO01UZSSYeZZvKJmbWIoEv/ax/YaI=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=zeyloMazLX4NnLlH1MJoyG9juXBNJrjhCgAN5P2uOtc=;\n\tb=IvsjvvKBdFmqNf7vMFFodjGccCYBkk91wx7xcKcU+w+eVMAyXr+0/UUdUf3kEKSFqb\n\tPQJES+H+L9C9EyRuB9PUDCao8ob+6pKGuZ+XSzQr9SAVl/dveHOGTISBWTEF0jWLoaZk\n\tcUd1fLedrrDyH7S563pi+obWjCyI3HkfM4fdymY3s9djy8lEC7ePD+969m9K5/nim4ee\n\tFKYeSJDR3USOKs5tk0YD6xLEvdeKqbv6bsG/ENRNiTj6eGPcytDDuYVlZmJn2K3b2w0V\n\t3Ogs566kyac9rPpagcdsgcb63HSjAMyMLBbexMK2sKIzQoyrzKxi1D3mgpXrtOY6GCHk\n\tLpig==","X-Gm-Message-State":"AMCzsaUHd2BRtmxsJ61kcNKRV42YACijZ5g9lgNL9+8d9LWNwFNewcki\n\tzPU1NHYzr55DawhBTkmTJQwDwg==","X-Google-Smtp-Source":"AOwi7QAk6y/JcRFzrgFIwn6VgKC7iFjRdEL8JGNmwnSPTRiz3RYbu4N4RObXWe99yfnNfp0Il77WvQ==","X-Received":"by 10.13.214.211 with SMTP id y202mr1624620ywd.344.1507296272701;\n\tFri, 06 Oct 2017 06:24:32 -0700 (PDT)","To":"Peter Maydell ","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-3-git-send-email-peter.maydell@linaro.org>\n\t\n\t\n\t","From":"Richard Henderson ","Message-ID":"","Date":"Fri, 6 Oct 2017 09:24:29 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::230","Subject":"Re: [Qemu-devel] [PATCH 02/20] target/arm: Don't switch to target\n\tstack early in v7M exception return","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , QEMU Developers , \n\t\"patches@linaro.org\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]