[{"id":1780286,"web_url":"http://patchwork.ozlabs.org/comment/1780286/","msgid":"","list_archive_url":null,"date":"2017-10-05T04:46:33","subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 15/20] target/arm: Fix\n\tcalculation of secure mm_idx values","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/22/2017 12:00 PM, Peter Maydell wrote:\n> In cpu_mmu_index() we try to do this:\n> if (env->v7m.secure) {\n> mmu_idx += ARMMMUIdx_MSUser;\n> }\n> but it will give the wrong answer, because ARMMMUIdx_MSUser\n> includes the 0x40 ARM_MMU_IDX_M field, and so does the\n> mmu_idx we're adding to, and we'll end up with 0x8n rather\n> than 0x4n. This error is then nullified by the call to\n> arm_to_core_mmu_idx() which masks out the high part, but\n> we're about to factor out the code that calculates the\n> ARMMMUIdx values so it can be used without passing it through\n> arm_to_core_mmu_idx(), so fix this bug first.\n> \n> Signed-off-by: Peter Maydell \n\nReviewed-by: Philippe Mathieu-Daudé \n\n> ---\n> target/arm/cpu.h | 12 +++++++-----\n> 1 file changed, 7 insertions(+), 5 deletions(-)\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 441e584..70c1f85 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -2335,14 +2335,16 @@ static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)\n> int el = arm_current_el(env);\n> \n> if (arm_feature(env, ARM_FEATURE_M)) {\n> - ARMMMUIdx mmu_idx = el == 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MPriv;\n> + ARMMMUIdx mmu_idx;\n> \n> - if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {\n> - mmu_idx = ARMMMUIdx_MNegPri;\n> + if (el == 0) {\n> + mmu_idx = env->v7m.secure ? ARMMMUIdx_MSUser : ARMMMUIdx_MUser;\n> + } else {\n> + mmu_idx = env->v7m.secure ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPriv;\n> }\n> \n> - if (env->v7m.secure) {\n> - mmu_idx += ARMMMUIdx_MSUser;\n> + if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {\n> + mmu_idx = env->v7m.secure ? ARMMMUIdx_MSNegPri : ARMMMUIdx_MNegPri;\n> }\n> \n> return arm_to_core_mmu_idx(mmu_idx);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"LTZSQKCe\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y70cB4pJcz9t44\n\tfor ;\n\tThu, 5 Oct 2017 15:47:05 +1100 (AEDT)","from localhost ([::1]:37776 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dzy3q-0001Ud-WA\n\tfor incoming@patchwork.ozlabs.org; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-16-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::242","Subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 15/20] target/arm: Fix\n\tcalculation of secure mm_idx values","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780902,"web_url":"http://patchwork.ozlabs.org/comment/1780902/","msgid":"<440f5fa0-9c35-63f7-400d-2504a6e63483@linaro.org>","list_archive_url":null,"date":"2017-10-05T18:41:02","subject":"Re: [Qemu-devel] [PATCH 15/20] target/arm: Fix calculation of\n\tsecure mm_idx values","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> In cpu_mmu_index() we try to do this:\n> if (env->v7m.secure) {\n> mmu_idx += ARMMMUIdx_MSUser;\n> }\n> but it will give the wrong answer, because ARMMMUIdx_MSUser\n> includes the 0x40 ARM_MMU_IDX_M field, and so does the\n> mmu_idx we're adding to, and we'll end up with 0x8n rather\n> than 0x4n. This error is then nullified by the call to\n> arm_to_core_mmu_idx() which masks out the high part, but\n> we're about to factor out the code that calculates the\n> ARMMMUIdx values so it can be used without passing it through\n> arm_to_core_mmu_idx(), so fix this bug first.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/cpu.h | 12 +++++++-----\n> 1 file changed, 7 insertions(+), 5 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"DsO9hFae\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y7M8z4YKxz9t2V\n\tfor ;\n\tFri, 6 Oct 2017 05:43:15 +1100 (AEDT)","from localhost ([::1]:41544 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1e0B73-0006bA-Pe\n\tfor incoming@patchwork.ozlabs.org; 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