[{"id":1780254,"web_url":"http://patchwork.ozlabs.org/comment/1780254/","msgid":"<5d58270d-9d17-fe9e-6d24-9cb130646de6@amsat.org>","list_archive_url":null,"date":"2017-10-05T03:25:38","subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 03/20] target/arm: Prepare for\n\tCONTROL.SPSEL being nonzero in Handler mode","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/22/2017 11:59 AM, Peter Maydell wrote:\n> In the v7M architecture, there is an invariant that if the CPU is\n> in Handler mode then the CONTROL.SPSEL bit cannot be nonzero.\n> This in turn means that the current stack pointer is always\n> indicated by CONTROL.SPSEL, even though Handler mode always uses\n> the Main stack pointer.\n> \n> In v8M, this invariant is removed, and CONTROL.SPSEL may now\n> be nonzero in Handler mode (though Handler mode still always\n> uses the Main stack pointer). In preparation for this change,\n> change how we handle this bit: rename switch_v7m_sp() to\n> the now more accurate write_v7m_control_spsel(), and make it\n> check both the handler mode state and the SPSEL bit.\n> \n> Note that this implicitly changes the point at which we switch\n> active SP on exception exit from before we pop the exception\n> frame to after it.\n> \n> Signed-off-by: Peter Maydell \n\nReviewed-by: Philippe Mathieu-Daudé \n\n> ---\n> target/arm/cpu.h | 8 ++++++-\n> hw/intc/armv7m_nvic.c | 2 +-\n> target/arm/helper.c | 65 ++++++++++++++++++++++++++++++++++-----------------\n> 3 files changed, 51 insertions(+), 24 deletions(-)\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 8afceca..ad6eff4 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -991,6 +991,11 @@ void pmccntr_sync(CPUARMState *env);\n> #define PSTATE_MODE_EL1t 4\n> #define PSTATE_MODE_EL0t 0\n> \n> +/* Write a new value to v7m.exception, thus transitioning into or out\n> + * of Handler mode; this may result in a change of active stack pointer.\n> + */\n> +void write_v7m_exception(CPUARMState *env, uint32_t new_exc);\n> +\n> /* Map EL and handler into a PSTATE_MODE. */\n> static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)\n> {\n> @@ -1071,7 +1076,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)\n> env->condexec_bits |= (val >> 8) & 0xfc;\n> }\n> if (mask & XPSR_EXCP) {\n> - env->v7m.exception = val & XPSR_EXCP;\n> + /* Note that this only happens on exception exit */\n> + write_v7m_exception(env, val & XPSR_EXCP);\n> }\n> }\n> \n> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\n> index bc7b66d..a1041c2 100644\n> --- a/hw/intc/armv7m_nvic.c\n> +++ b/hw/intc/armv7m_nvic.c\n> @@ -616,7 +616,7 @@ bool armv7m_nvic_acknowledge_irq(void *opaque)\n> vec->active = 1;\n> vec->pending = 0;\n> \n> - env->v7m.exception = s->vectpending;\n> + write_v7m_exception(env, s->vectpending);\n> \n> nvic_irq_update(s);\n> \n> diff --git a/target/arm/helper.c b/target/arm/helper.c\n> index f13b99d..509a1aa 100644\n> --- a/target/arm/helper.c\n> +++ b/target/arm/helper.c\n> @@ -6052,21 +6052,44 @@ static bool v7m_using_psp(CPUARMState *env)\n> env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;\n> }\n> \n> -/* Switch to V7M main or process stack pointer. */\n> -static void switch_v7m_sp(CPUARMState *env, bool new_spsel)\n> +/* Write to v7M CONTROL.SPSEL bit. This may change the current\n> + * stack pointer between Main and Process stack pointers.\n> + */\n> +static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel)\n> {\n> uint32_t tmp;\n> - uint32_t old_control = env->v7m.control[env->v7m.secure];\n> - bool old_spsel = old_control & R_V7M_CONTROL_SPSEL_MASK;\n> + bool new_is_psp, old_is_psp = v7m_using_psp(env);\n> +\n> + env->v7m.control[env->v7m.secure] =\n> + deposit32(env->v7m.control[env->v7m.secure],\n> + R_V7M_CONTROL_SPSEL_SHIFT,\n> + R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);\n> +\n> + new_is_psp = v7m_using_psp(env);\n> \n> - if (old_spsel != new_spsel) {\n> + if (old_is_psp != new_is_psp) {\n> tmp = env->v7m.other_sp;\n> env->v7m.other_sp = env->regs[13];\n> env->regs[13] = tmp;\n> + }\n> +}\n> +\n> +void write_v7m_exception(CPUARMState *env, uint32_t new_exc)\n> +{\n> + /* Write a new value to v7m.exception, thus transitioning into or out\n> + * of Handler mode; this may result in a change of active stack pointer.\n> + */\n> + bool new_is_psp, old_is_psp = v7m_using_psp(env);\n> + uint32_t tmp;\n> \n> - env->v7m.control[env->v7m.secure] = deposit32(old_control,\n> - R_V7M_CONTROL_SPSEL_SHIFT,\n> - R_V7M_CONTROL_SPSEL_LENGTH, new_spsel);\n> + env->v7m.exception = new_exc;\n> +\n> + new_is_psp = v7m_using_psp(env);\n> +\n> + if (old_is_psp != new_is_psp) {\n> + tmp = env->v7m.other_sp;\n> + env->v7m.other_sp = env->regs[13];\n> + env->regs[13] = tmp;\n> }\n> }\n> \n> @@ -6149,13 +6172,11 @@ static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,\n> bool want_psp = threadmode && spsel;\n> \n> if (secure == env->v7m.secure) {\n> - /* Currently switch_v7m_sp switches SP as it updates SPSEL,\n> - * so the SP we want is always in regs[13].\n> - * When we decouple SPSEL from the actually selected SP\n> - * we need to check want_psp against v7m_using_psp()\n> - * to see whether we need regs[13] or v7m.other_sp.\n> - */\n> - return &env->regs[13];\n> + if (want_psp == v7m_using_psp(env)) {\n> + return &env->regs[13];\n> + } else {\n> + return &env->v7m.other_sp;\n> + }\n> } else {\n> if (want_psp) {\n> return &env->v7m.other_ss_psp;\n> @@ -6198,7 +6219,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr)\n> uint32_t addr;\n> \n> armv7m_nvic_acknowledge_irq(env->nvic);\n> - switch_v7m_sp(env, 0);\n> + write_v7m_control_spsel(env, 0);\n> arm_clear_exclusive(env);\n> /* Clear IT bits */\n> env->condexec_bits = 0;\n> @@ -6344,11 +6365,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n> return;\n> }\n> \n> - /* Set CONTROL.SPSEL from excret.SPSEL. For QEMU this currently\n> - * causes us to switch the active SP, but we will change this\n> - * later to not do that so we can support v8M.\n> + /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in\n> + * Handler mode (and will be until we write the new XPSR.Interrupt\n> + * field) this does not switch around the current stack pointer.\n> */\n> - switch_v7m_sp(env, return_to_sp_process);\n> + write_v7m_control_spsel(env, return_to_sp_process);\n> \n> {\n> /* The stack pointer we should be reading the exception frame from\n> @@ -9163,11 +9184,11 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)\n> case 20: /* CONTROL */\n> /* Writing to the SPSEL bit only has an effect if we are in\n> * thread mode; other bits can be updated by any privileged code.\n> - * switch_v7m_sp() deals with updating the SPSEL bit in\n> + * write_v7m_control_spsel() deals with updating the SPSEL bit in\n> * env->v7m.control, so we only need update the others.\n> */\n> if (!arm_v7m_is_handler_mode(env)) {\n> - switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);\n> + write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0);\n> }\n> env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK;\n> env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK;\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-4-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::244","Subject":"Re: [Qemu-devel] [Qemu-arm] [PATCH 03/20] target/arm: Prepare for\n\tCONTROL.SPSEL being nonzero in Handler mode","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1780776,"web_url":"http://patchwork.ozlabs.org/comment/1780776/","msgid":"","list_archive_url":null,"date":"2017-10-05T16:09:23","subject":"Re: [Qemu-devel] [PATCH 03/20] target/arm: Prepare for\n\tCONTROL.SPSEL being nonzero in Handler mode","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 10:59 AM, Peter Maydell wrote:\n> In the v7M architecture, there is an invariant that if the CPU is\n> in Handler mode then the CONTROL.SPSEL bit cannot be nonzero.\n> This in turn means that the current stack pointer is always\n> indicated by CONTROL.SPSEL, even though Handler mode always uses\n> the Main stack pointer.\n> \n> In v8M, this invariant is removed, and CONTROL.SPSEL may now\n> be nonzero in Handler mode (though Handler mode still always\n> uses the Main stack pointer). In preparation for this change,\n> change how we handle this bit: rename switch_v7m_sp() to\n> the now more accurate write_v7m_control_spsel(), and make it\n> check both the handler mode state and the SPSEL bit.\n> \n> Note that this implicitly changes the point at which we switch\n> active SP on exception exit from before we pop the exception\n> frame to after it.\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/cpu.h | 8 ++++++-\n> hw/intc/armv7m_nvic.c | 2 +-\n> target/arm/helper.c | 65 ++++++++++++++++++++++++++++++++++-----------------\n> 3 files changed, 51 insertions(+), 24 deletions(-)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org; 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\n\tThu, 05 Oct 2017 09:09:26 -0700 (PDT)","To":"Peter Maydell , qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-4-git-send-email-peter.maydell@linaro.org>","From":"Richard Henderson ","Message-ID":"","Date":"Thu, 5 Oct 2017 12:09:23 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-4-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::22f","Subject":"Re: [Qemu-devel] [PATCH 03/20] target/arm: Prepare for\n\tCONTROL.SPSEL being nonzero in Handler mode","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]