[{"id":1773344,"web_url":"http://patchwork.ozlabs.org/comment/1773344/","msgid":"<1506067636.26847.2.camel@mtksdaap41>","list_archive_url":null,"date":"2017-09-22T08:07:16","subject":"Re: [PATCH 3/4] rtc: mediatek: enhance the description for MediaTek\n\tPMIC based RTC","submitter":{"id":65011,"url":"http://patchwork.ozlabs.org/api/people/65011/","name":"Eddie Huang","email":"eddie.huang@mediatek.com"},"content":"Hi Sean,\n\nOn Fri, 2017-09-22 at 11:33 +0800, sean.wang@mediatek.com wrote:\n> From: Sean Wang \n> \n> Give a better description for original MediaTek RTC driver as PMIC based\n> RTC in order to distinguish SoC based RTC. Also turning all words with\n> Mediatek to MediaTek here.\n> \n> Cc: Eddie Huang \n> Signed-off-by: Sean Wang \n> ---\n> drivers/rtc/Kconfig | 8 ++++----\n> 1 file changed, 4 insertions(+), 4 deletions(-)\n> \n> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig\n> index 4226295..4500f77 100644\n> --- a/drivers/rtc/Kconfig\n> +++ b/drivers/rtc/Kconfig\n> @@ -1716,14 +1716,14 @@ config RTC_DRV_MEDIATEK\n> \t will be called rtc-mediatek.\n> \n> config RTC_DRV_MT6397\n> -\ttristate \"Mediatek Real Time Clock driver\"\n> +\ttristate \"MediaTek PMIC based RTC\"\n> \tdepends on MFD_MT6397 || (COMPILE_TEST && IRQ_DOMAIN)\n> \thelp\n> -\t This selects the Mediatek(R) RTC driver. RTC is part of Mediatek\n> +\t This selects the MediaTek(R) RTC driver. RTC is part of MediaTek\n> \t MT6397 PMIC. You should enable MT6397 PMIC MFD before select\n> -\t Mediatek(R) RTC driver.\n> +\t MediaTek(R) RTC driver.\n> \n> -\t If you want to use Mediatek(R) RTC interface, select Y or M here.\n> +\t If you want to use MediaTek(R) RTC interface, select Y or M here.\n> \n> config RTC_DRV_XGENE\n> \ttristate \"APM X-Gene RTC\"\n\nThanks your correction.\n\nAcked-by: Eddie Huang \n\nRegards,","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xz5gH5DLTz9s7C\n\tfor ;\n\tFri, 22 Sep 2017 18:07:23 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751830AbdIVIHX (ORCPT );\n\tFri, 22 Sep 2017 04:07:23 -0400","from mailgw02.mediatek.com ([210.61.82.184]:48264 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751704AbdIVIHW (ORCPT\n\t); Fri, 22 Sep 2017 04:07:22 -0400","from mtkexhb02.mediatek.inc [(172.21.101.103)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 1358763777; Fri, 22 Sep 2017 16:07:16 +0800","from mtkcas08.mediatek.inc (172.21.101.126) by\n\tmtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Fri, 22 Sep 2017 16:06:42 +0800","from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Fri, 22 Sep 2017 16:06:36 +0800"],"X-UUID":"18cc0420f1724bce8072e767df83536f-20170922","Message-ID":"<1506067636.26847.2.camel@mtksdaap41>","Subject":"Re: [PATCH 3/4] rtc: mediatek: enhance the description for MediaTek\n\tPMIC based RTC","From":"Eddie Huang ","To":"","CC":", ,\n\t, ,\n\t, ,\n\t, ","Date":"Fri, 22 Sep 2017 16:07:16 +0800","In-Reply-To":"<0d9d5559d9d884c98ef589a8f56ab0dcb140e5e0.1506049341.git.sean.wang@mediatek.com>","References":"\n\t<0d9d5559d9d884c98ef589a8f56ab0dcb140e5e0.1506049341.git.sean.wang@mediatek.com>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.2.3-0ubuntu6 ","Content-Transfer-Encoding":"7bit","MIME-Version":"1.0","X-MTK":"N","Sender":"linux-rtc-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-rtc@vger.kernel.org"}}]