[{"id":1776224,"web_url":"http://patchwork.ozlabs.org/comment/1776224/","msgid":"","list_archive_url":null,"date":"2017-09-27T09:55:33","subject":"Re: [U-Boot] [U-Boot,\n\t4/6] net: gmac_rockchip: Define the gmac grf register struct at\n\tgmac_rockchip.c","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> If we include both the rk3288_grf.h and rv1108_grf.h, there is a\n> number of compiling error for redefinition. So we define the reg\n> structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,\n> give them own grf offset for their use.\n> \n> Signed-off-by: David Wu \n> ---\n> \n> drivers/net/gmac_rockchip.c | 144 +++++++++++++++++++++++++++++++++++---------\n> 1 file changed, 116 insertions(+), 28 deletions(-)\n> \n\nAcked-by: Philipp Tomsich ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2DZG0hWxz9tXQ\n\tfor ;\n\tWed, 27 Sep 2017 20:28:54 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid D0A51C21E68; Wed, 27 Sep 2017 10:28:12 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id B1282C21EB9;\n\tWed, 27 Sep 2017 09:57:58 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 7689CC21D8C; Wed, 27 Sep 2017 09:57:55 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 59A5FC21E13\n\tfor ; Wed, 27 Sep 2017 09:55:42 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:60984\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dx941-0001PT-Ue; Wed, 27 Sep 2017 11:55:34 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"David Wu ","In-Reply-To":"<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>","References":"<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>","Message-Id":"","Date":"Wed, 27 Sep 2017 11:55:33 +0200","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de,\n\tJoe Hershberger ,\n\tDavid Wu , \n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t4/6] net: gmac_rockchip: Define the gmac grf register struct at\n\tgmac_rockchip.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1776437,"web_url":"http://patchwork.ozlabs.org/comment/1776437/","msgid":"","list_archive_url":null,"date":"2017-09-27T15:44:42","subject":"Re: [U-Boot] [PATCH 4/6] net: gmac_rockchip: Define the gmac grf\n\tregister struct at gmac_rockchip.c","submitter":{"id":8809,"url":"http://patchwork.ozlabs.org/api/people/8809/","name":"Joe Hershberger","email":"joe.hershberger@ni.com"},"content":"On Thu, Sep 21, 2017 at 9:17 AM, David Wu wrote:\n> If we include both the rk3288_grf.h and rv1108_grf.h, there is a\n> number of compiling error for redefinition. So we define the reg\n> structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,\n> give them own grf offset for their use.\n>\n> Signed-off-by: David Wu \n> ---\n>\n> drivers/net/gmac_rockchip.c | 144 +++++++++++++++++++++++++++++++++++---------\n> 1 file changed, 116 insertions(+), 28 deletions(-)\n>\n> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c\n> index 586ccbf..5f8f0cd 100644\n> --- a/drivers/net/gmac_rockchip.c\n> +++ b/drivers/net/gmac_rockchip.c\n> @@ -15,9 +15,6 @@\n> #include \n> #include \n> #include \n> -#include \n> -#include \n> -#include \n\nYou should also delete these header files as part of the patch.\n\n> #include \n> #include \n> #include \"designware.h\"\n> @@ -31,15 +28,37 @@ DECLARE_GLOBAL_DATA_PTR;\n> */\n> struct gmac_rockchip_platdata {\n> struct dw_eth_pdata dw_eth_pdata;\n> + void *grf;\n> int tx_delay;\n> int rx_delay;\n> };\n>\n> struct rk_gmac_ops {\n> - int (*fix_mac_speed)(struct dw_eth_dev *priv);\n> + int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,\n> + struct dw_eth_dev *priv);\n> void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);\n> };\n>\n> +struct gmac_rockchip_driver_data {\n> + const struct rk_gmac_ops *ops;\n> + unsigned int grf_offset;\n> +};\n> +\n> +struct rk3288_mac_grf {\n> + u32 soc_con1;\n> + u32 reserved;\n> + u32 soc_con3;\n> +};\n> +\n> +struct rk3368_mac_grf {\n> + u32 soc_con15;\n> + u32 soc_con16;\n> +};\n> +\n> +struct rk3399_mac_grf {\n> + u32 soc_con5;\n> + u32 soc_con6;\n> +};\n>\n> static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)\n> {\n> @@ -58,10 +77,18 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)\n> return designware_eth_ofdata_to_platdata(dev);\n> }\n>\n> -static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> +static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,\n> + struct dw_eth_dev *priv)\n> {\n> - struct rk3288_grf *grf;\n> + struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;\n> int clk;\n> + enum {\n> + RK3288_GMAC_CLK_SEL_SHIFT = 12,\n> + RK3288_GMAC_CLK_SEL_MASK = GENMASK(13, 12),\n> + RK3288_GMAC_CLK_SEL_125M = 0 << 12,\n> + RK3288_GMAC_CLK_SEL_25M = 3 << 12,\n> + RK3288_GMAC_CLK_SEL_2_5M = 2 << 12,\n> + };\n>\n> switch (priv->phydev->speed) {\n> case 10:\n> @@ -78,15 +105,15 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> return -EINVAL;\n> }\n>\n> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);\n>\n> return 0;\n> }\n>\n> -static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> +static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,\n> + struct dw_eth_dev *priv)\n> {\n> - struct rk3368_grf *grf;\n> + struct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;\n> int clk;\n> enum {\n> RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,\n> @@ -110,16 +137,22 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> return -EINVAL;\n> }\n>\n> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);\n>\n> return 0;\n> }\n>\n> -static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> +static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,\n> + struct dw_eth_dev *priv)\n> {\n> - struct rk3399_grf_regs *grf;\n> + struct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;\n> int clk;\n> + enum {\n> + RK3399_GMAC_CLK_SEL_MASK = GENMASK(6, 4),\n> + RK3399_GMAC_CLK_SEL_125M = 0 << 4,\n> + RK3399_GMAC_CLK_SEL_25M = 3 << 4,\n> + RK3399_GMAC_CLK_SEL_2_5M = 2 << 4,\n> + };\n>\n> switch (priv->phydev->speed) {\n> case 10:\n> @@ -136,7 +169,6 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> return -EINVAL;\n> }\n>\n> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);\n>\n> return 0;\n> @@ -144,9 +176,31 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n>\n> static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> {\n> - struct rk3288_grf *grf;\n> + struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;\n> + enum {\n> + RK3288_RMII_MODE_SHIFT = 14,\n> + RK3288_RMII_MODE_MASK = BIT(14),\n> +\n> + RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,\n> + RK3288_GMAC_PHY_INTF_SEL_MASK = GENMASK(8, 6),\n> + RK3288_GMAC_PHY_INTF_SEL_RGMII = BIT(6),\n> + };\n> + enum {\n> + RK3288_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),\n> + RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> + RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),\n> +\n> + RK3288_TXCLK_DLY_ENA_GMAC_MASK = BIT(14),\n> + RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> + RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(14),\n> +\n> + RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,\n> + RK3288_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),\n> +\n> + RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,\n> + RK3288_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n> + };\n>\n> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> rk_clrsetreg(&grf->soc_con1,\n> RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,\n> RK3288_GMAC_PHY_INTF_SEL_RGMII);\n> @@ -164,7 +218,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n>\n> static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> {\n> - struct rk3368_grf *grf;\n> + struct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;\n> enum {\n> RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,\n> RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),\n> @@ -184,7 +238,6 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n> };\n>\n> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> rk_clrsetreg(&grf->soc_con15,\n> RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,\n> RK3368_GMAC_PHY_INTF_SEL_RGMII);\n> @@ -202,9 +255,24 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n>\n> static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> {\n> - struct rk3399_grf_regs *grf;\n> -\n> - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> + struct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;\n> + enum {\n> + RK3399_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),\n> + RK3399_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,\n> + RK3399_GMAC_PHY_INTF_SEL_RMII = 4 << 9,\n> + };\n> + enum {\n> + RK3399_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),\n> + RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> + RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),\n> + RK3399_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),\n> + RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> + RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),\n> + RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,\n> + RK3399_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),\n> + RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,\n> + RK3399_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n> + };\n>\n> rk_clrsetreg(&grf->soc_con5,\n> RK3399_GMAC_PHY_INTF_SEL_MASK,\n> @@ -224,8 +292,9 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> static int gmac_rockchip_probe(struct udevice *dev)\n> {\n> struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);\n> - struct rk_gmac_ops *ops =\n> - (struct rk_gmac_ops *)dev_get_driver_data(dev);\n> + struct gmac_rockchip_driver_data *data =\n> + (struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);\n> + const struct rk_gmac_ops *ops = data->ops;\n> struct clk clk;\n> int ret;\n>\n> @@ -238,6 +307,9 @@ static int gmac_rockchip_probe(struct udevice *dev)\n> if (ret)\n> return ret;\n>\n> + pdata->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF) +\n> + data->grf_offset;\n> +\n> /* Set to RGMII mode */\n> ops->set_to_rgmii(pdata);\n>\n> @@ -248,14 +320,15 @@ static int gmac_rockchip_eth_start(struct udevice *dev)\n> {\n> struct eth_pdata *pdata = dev_get_platdata(dev);\n> struct dw_eth_dev *priv = dev_get_priv(dev);\n> - struct rk_gmac_ops *ops =\n> - (struct rk_gmac_ops *)dev_get_driver_data(dev);\n> + struct gmac_rockchip_driver_data *data =\n> + (struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);\n> + const struct rk_gmac_ops *ops = data->ops;\n> int ret;\n>\n> ret = designware_eth_init(priv, pdata->enetaddr);\n> if (ret)\n> return ret;\n> - ret = ops->fix_mac_speed(priv);\n> + ret = ops->fix_mac_speed((struct gmac_rockchip_platdata *)pdata, priv);\n> if (ret)\n> return ret;\n> ret = designware_eth_enable(priv);\n> @@ -279,23 +352,38 @@ const struct rk_gmac_ops rk3288_gmac_ops = {\n> .set_to_rgmii = rk3288_gmac_set_to_rgmii,\n> };\n>\n> +const struct gmac_rockchip_driver_data rk3288_gmac_data = {\n> + .ops = &rk3288_gmac_ops,\n> + .grf_offset = 0x248,\n> +};\n> +\n> const struct rk_gmac_ops rk3368_gmac_ops = {\n> .fix_mac_speed = rk3368_gmac_fix_mac_speed,\n> .set_to_rgmii = rk3368_gmac_set_to_rgmii,\n> };\n>\n> +const struct gmac_rockchip_driver_data rk3368_gmac_data = {\n> + .ops = &rk3368_gmac_ops,\n> + .grf_offset = 0x43c,\n> +};\n> +\n> const struct rk_gmac_ops rk3399_gmac_ops = {\n> .fix_mac_speed = rk3399_gmac_fix_mac_speed,\n> .set_to_rgmii = rk3399_gmac_set_to_rgmii,\n> };\n>\n> +const struct gmac_rockchip_driver_data rk3399_gmac_data = {\n> + .ops = &rk3399_gmac_ops,\n> + .grf_offset = 0xc214,\n> +};\n> +\n> static const struct udevice_id rockchip_gmac_ids[] = {\n> { .compatible = \"rockchip,rk3288-gmac\",\n> - .data = (ulong)&rk3288_gmac_ops },\n> + .data = (ulong)&rk3288_gmac_data },\n> { .compatible = \"rockchip,rk3368-gmac\",\n> - .data = (ulong)&rk3368_gmac_ops },\n> + .data = (ulong)&rk3368_gmac_data },\n> { .compatible = \"rockchip,rk3399-gmac\",\n> - .data = (ulong)&rk3399_gmac_ops },\n> + .data = (ulong)&rk3399_gmac_data },\n> { }\n> };\n>\n> --\n> 2.7.4\n>\n>\n> _______________________________________________\n> U-Boot mailing list\n> U-Boot@lists.denx.de\n> https://lists.denx.de/listinfo/u-boot","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nio365.onmicrosoft.com\n\theader.i=@nio365.onmicrosoft.com header.b=\"VXNcFCpc\"; \n\tdkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2MbR4r1Mz9tXw\n\tfor ;\n\tThu, 28 Sep 2017 01:45:23 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 72865C21D5D; Wed, 27 Sep 2017 15:45:19 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C373EC21D5B;\n\tWed, 27 Sep 2017 15:45:15 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid DFDE7C21D5B; Wed, 27 Sep 2017 15:45:14 +0000 (UTC)","from mx0b-00010702.pphosted.com (mx0b-00010702.pphosted.com\n\t[148.163.158.57])\n\tby lists.denx.de (Postfix) with ESMTPS id AA760C21C62\n\tfor ; Wed, 27 Sep 2017 15:45:13 +0000 (UTC)","from pps.filterd (m0098778.ppops.net [127.0.0.1])\n\tby mx0b-00010702.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8RFaHRQ010024\n\tfor ; Wed, 27 Sep 2017 10:45:09 -0500","from nam02-sn1-obe.outbound.protection.outlook.com\n\t(mail-sn1nam02lp0019.outbound.protection.outlook.com [216.32.180.19])\n\tby mx0b-00010702.pphosted.com with ESMTP id 2d8a0tt7ad-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor ; Wed, 27 Sep 2017 10:45:08 -0500","from mail-it0-f47.google.com (209.85.214.47) by\n\tDM5PR04MB0922.namprd04.prod.outlook.com (10.174.191.20) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Wed, 27 Sep 2017 15:45:07 +0000","by mail-it0-f47.google.com with SMTP id 85so7090007ith.2\n\tfor ; Wed, 27 Sep 2017 08:45:06 -0700 (PDT)","by 10.79.158.130 with HTTP; Wed, 27 Sep 2017 08:44:42 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=nio365.onmicrosoft.com; s=selector1-ni-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=hIDKta9TDk67Q8DZ1DvW4GL/FXciSLG6YmpAbG96sMc=;\n\tb=VXNcFCpcH1NpgoPGWYIrR8coFwnwG9Nkq8wtwl9rPYWM+tT2SYgti65A7IXFINR0itspihCsEuQZLLNg2vvNEFex6kDrPdXe9O0L/96zt1DyS58u8XGDw2S3UugT7VQwhok1U3eTMgaJJh2oX7o4AALP4D1mt+f43LjgoR4UMZE=","X-Gm-Message-State":"AHPjjUglh6qovvRF6QDZ+vny9n8Lds5rKxBD4Q9shT7kePEPSmv3jv0s\n\tCYDj/Uk6w5A53BxT9DlrsGoaJI/2CJ5xYuRKPNc=","X-Google-Smtp-Source":"AOwi7QDSqbdnamS10b3XzkT+DpIIFRXoD3cQd6ZUhwihbOUQxaXXmUT/m5g5VkJVxK/iD+NHextAyJITOasN4fJ7ijU=","X-Received":"by 10.36.176.70 with SMTP id b6mr1342838itj.26.1506527103068;\n\tWed, 27 Sep 2017 08:45:03 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>","References":"<1506003471-34551-1-git-send-email-david.wu@rock-chips.com>\n\t<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>","From":"Joe Hershberger ","Date":"Wed, 27 Sep 2017 10:44:42 -0500","X-Gmail-Original-Message-ID":"","Message-ID":"","To":"David Wu ","X-Originating-IP":"[209.85.214.47]","X-ClientProxiedBy":"MWHPR1601CA0024.namprd16.prod.outlook.com (10.172.93.34)\n\tTo DM5PR04MB0922.namprd04.prod.outlook.com (10.174.191.20)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"7e793175-cd63-4644-c20c-08d505beba7a","X-Microsoft-Antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(22001)(2017030254152)(2017052603199)(201703131423075)(201703031133081)(201702281549075);\n\tSRVR:DM5PR04MB0922; ","X-Microsoft-Exchange-Diagnostics":["1; DM5PR04MB0922;\n\t3:QXfpdvvS9PBhXjQMzmVr4BCdyUY286Mr/Xh8+501DHI486SzB30zoROdKY+ZXUWqM1/2mpXNmTL1fg15+q5sqBl1V4LCb40h4FVCrQV49u6ZBH3DKqdMVKKMUcaQReQmcscUYHEDEJcWPIVndOqmaYUjOwMHiaSdkHuXiPgOkckeJRjAGJWWl+NWOUMmsEjZxQgIZDbh2Ix2weX1ljScP+MNL2MYyYfEprsvfEpBbRo1CDfgN+LMRDriYifycZkm;\n\t25:8/7maEDgFxaG9xDs18BfIfJiHbnKEJFZ620EEUbXCpoMtswPm38AGWZ8qosmpCxbq24hySRwFk+oXaKJmx9NXoSmbbF9Ym3oSVBaRyKs5sIPyFCghfysmf7Q89WLsARFhKjz2F6T8D+fiobEPw0NTjRG+pmaslHh0kOd6R2o1R6zzNBzjyKv1EM0tU2w7Gbe5XNBfz2DXXZqGNG8Vscg9sRvidJB4QIwNmqcZMwDI5Q2Cq9oN6L1KD3oD37tglqFjtkgc4+FbZq6HW68jM2ZdF8OYQ2+NZaOGnqfIQAyQ27/xAgS1xn+BMgO3B5yyDXIzJxVMlKlR2J1yOLPv2s/+w==;\n\t31:chN/gh44TCSs6LuDRNyDt5YBT3tIqb4SdInV/9qokhe3CNWrn3uTO/DQRjrdyBS4sKuUWJTFZp3ilDV6LfpOVPB1kTV3EXB7hmcLnw8cIoj60vxgBHz9+r9W8wLMWYgy7dUMoaur+JErbyexCcpPl3q3sP0Y+x9X8IRSOlfV98jBNqSqzzblpWTDAYSTHazeLHtpr7JQ2bBtiFSrNKM0egVdizXzBw4t0SagGo3jH9A=","1; DM5PR04MB0922;\n\t20:W3vWrzDOmMi1p3vNH2Ukbvr8XG6Dgv7FkinBdYgKNNkveOFKzgiie0XNjzJQGA+YzE3XUwQr59hP+hwZoqIBBQMve11LITha79B4Ml0VMqB3pfRf5Wp4Lfta30Fsyqk4j1zyZ5F8XE0Fntxr2+js6I+lBhr8ggBR0iYjvIk6jf5YvbsQIJMPqCHLngfMzzrG3xf/nVnbwSsBrOvuUrCNUYuGpbsgZJRUh3nNG3mH18iFNVgy2tuVon2U+5sOxDoF602Rq+ckIxEwlrkjGa219/OB4ZeVmqVRhXDAF1g0TpSjQ1OwPeC0WQje81rA7vWfabSlq79YdgmyyFL1CK7vwAturyJswiBcFZCGbivuadwjJXtBLhQZRg4L5XNJEnmp7tHpJw2VspSKfDm4KR0bNXYXlxPNmMFoPkjL6/KxOjGIW9fqhsGDQKza7PcCl4am9Bieh7CSw95GTfGLJbwexE2jDliAyfUNmc1hbpNDf3tbBdNV9yZ4MrGZfVzOXfTSA/nknftUtQjdTqf6lSbmXAd9Px8aHu+6qyJ9hfPjTsJINGHTcRz7m5OFhZlAW/efHt9xuFURMaVDiiFU4cNz6ap6ydi421VEALGLUTIQVw4=;\n\t4:h436LJBfZjQWIyPV504oOz/burIuJ5iQieZpOL7AOzSIW7e8hf5cxlYAj2puNxufdR9SjYSIJTb5JagmF8rnN0ME5UFsGDnL9ZcaughiAede463yEtS8I6Svz7PVtLO99nh5xv5MRdZ0Gf2JmSSE0AI/NhbEAGyFVV09Buopons/lPqiiOsgKH6kBlXv9ifGqPrVsWXG0tEEM3mnD6b5IICv6mf+p+sfIyQv9HFen9hwWxKBwyFL1yuBZd3jv/n11/IMNsVxOX2QCiKkYud5O67g9mS95KO54rAZjUErQJw=","=?utf-8?q?1=3BDM5PR04MB0922=3B23=3AMB4l?=\n\t=?utf-8?q?oq7A2ZaKkRt3ZeDIxzdJV4HFHMnAfG2Dz5v3x2RIbeWkIF2yayn3t6B9?=\n\t=?utf-8?q?ngYzGFeNT4pLZqBNBAZcvZMb1ygkFQONOmAbhVQXPX7s7fesdSxosDxd?=\n\t=?utf-8?q?/a2S2Oz/IPGOue4/Zl6JLpb0U4lGHLf4ig485riyUzrxQgCJC43uhe14?=\n\t=?utf-8?q?HH8WgB7ea3YX2Df694Jbgl38qwnJ+px6LJt5P6B11d8ogxYA6vxG9eM+?=\n\t=?utf-8?q?pg90C3loSGxU7Z0mVr1my5s7fy1BNy62gAwKnSO+KAiOmRPYm54YSuoV?=\n\t=?utf-8?q?RRwSoYljQvHwrm1yJtAoSFl4B66Gvz5D00LNNl4HjzAZurbmMT4whBj5?=\n\t=?utf-8?q?nohaHIs6jpwwTYai6ZPhFSXrqQvde/CRu5SHck5JErKdR03EfJkbd9ft?=\n\t=?utf-8?q?5DpBul2jBnaRku4usoXq6r+jpJVa9tNQ/v42ebqbs48OaEj5NLRoIxyS?=\n\t=?utf-8?q?iWTS38qlXxf2FXpFIvxCqjCeKRtlojiElM4tjyPgu0HuHZUyMyIaKkTL?=\n\t=?utf-8?q?Xd0N0y7naT883+GH/GvBvodWcfkigFidiqNtVYwAzoZA950sCUEb1zFR?=\n\t=?utf-8?q?POOGmLsi9QcIjRlu7BOGKXQCcX4SNdVd7kMsJuDdAbLXgnmqmQ57zFdM?=\n\t=?utf-8?q?gQIakUlgXJJ8a08D5g2ix+eUhxMjKEDbgjdXr6HVzUbhjdwvXH3vPm4Z?=\n\t=?utf-8?q?jzFpixrG5S9Gc9NlUmq5lZfRQZBD1VrMVKv5enSm1V4fvIzbqiaer0FU?=\n\t=?utf-8?q?89T9xsGIYry/Fkq1GJlkLKO6Qc3zjf862DscV/S66gASdA4uVipn7LBb?=\n\t=?utf-8?q?Rw1Y7EqBMMGCpfcpKxPQWyXXixJr9Qkmab1b366HGRZqvZizV0feCXCp?=\n\t=?utf-8?q?Zu+9UMECjIDInxUstp9ysfI+jxWDc/YiVb5Cea4JbHiqFm/KGYBmgzFV?=\n\t=?utf-8?q?1pwOJspbKISdog/FqvpSNfhYc5Kkk3aQs17aoxnLKa/2EQ22LFb3xQSu?=\n\t=?utf-8?q?4o8dZfw/h1yCJ/VcCeVyBhFvjqr8k8qsDlJvcoqT/aSGmDwIY2MZEZuQ?=\n\t=?utf-8?q?5ib9Or9J0/9m2HR35Qbsd2ND9tejqcUskaqdFZtme89Wp6k9Ajj1QHw5?=\n\t=?utf-8?q?GXIvt8H2hj//M8tfvd9WtQnRH54dxwgbqsvZB4Po5C+AJ7m7L7LOQiTy?=\n\t=?utf-8?q?EoOc6jHiMHbqX6kVL5gGVaQQmAEXwpqbGPuel9wqsXuRd3UDDcqy5bjZ?=\n\t=?utf-8?q?/9ayw5PQlw13CXQ8al8C8mkUibtN1mPqEo0soKyGo0iyn+a+aaKUnjsS?=\n\t=?utf-8?q?7G4pPsuNMK5E/+uf0DsWYXwqlKS1eyT2HJdoP3JkxmuTlBWd4ABGZVCw?=\n\t=?utf-8?q?hvzyhoPkn8vavNHaMSVFON2M4Kh027QgfcGtXbSWgfGr8WQ9Orx/lExI?=\n\t=?utf-8?q?Wvj5tJWzIa/WsyQ8xh893ojcMhIIkQxcntz0S/yN0wurnveoiBNMgNq4?=\n\t=?utf-8?q?KXhGD8xb0x3YOvFcsEVjsLZdM2J4OuxGzgHe1UbF3y5oB7B2EZErBgih?=\n\t=?utf-8?q?2X6gDHscMxs2?=","1; DM5PR04MB0922;\n\t6:5SmMa9r8qmd6CAvgchSAz1UZ72mI3zydesBBXwOavQY3wUt8zfTFG/6WrSOnT2aCpoJWHlomwBRz14g1miWIAR5TwYMS670Q7j76w9XzSreG6Dj1XvVcHqllPdZEvR+oNM+WJ0NfkV8MqEeACPUaw5ONwCMlMXFUHx/5XCTW8dsFda+zvGBlyeVJCg+HtGcAbxB2/gPiQfQoqGWKf05YbthwWny7KZsWlVIf4tO3KQZ4d/oXYUXRUggcZaCNVTLChXuAAu20Cq5IWMLhi+F32PAFuvO7NFRcYq9ulUjdm+4szjUXTh1K1cqBHKN5JwpA/e6wI3FgYXvbRVGP4bkKWA==;\n\t5:tQ0cz6CTKTPKkZJeHQkBL0ODARtPTArLVA511nR5jY9Ppfxy2NFHKRaDqh9pf8u4qI3kNluaIL3FKQ8rjx5HqkGTf6GAtN/zxmZmK2sMpHgy3LfKtpSYpxfqpGhMNUnLIBOTreqhjhU8nACJPyjCLQ==;\n\t24:xzZuIAaCtyPXV+izrsbaZnJi1xf6VCSmKQsQwIClvuuDgQme6afnJzqsAD0SwTecGCqOeY8KiuWQ3CD66WSOpg7iQq9IoT1wsjc0MWcGp7Y=;\n\t7:tYywLoAYDkCAzl3hkmEht4CMfL7bNg79M2wYb4tCYpBKX1MggXziIJHuSfUp6kQ3V8elbtfqa2bnvZOvYeUKMNkJs+ww+OLPpqaQv0BIw+uQBKu6m24QJPOS4gr8gcGXYuu9LQm/QXJR4huv0yja0r4DZzfSV8ZHrNILlwEWGttNSRt525mDIpqPOpYIUgY+S71tw2cxirNoRQjDkH7OpvebnG9++NM6ocqlz7iuVxE="],"X-MS-TrafficTypeDiagnostic":"DM5PR04MB0922:","X-Exchange-Antispam-Report-Test":"UriScan:(16074681357397);","X-Microsoft-Antispam-PRVS":"","X-Exchange-Antispam-Report-CFA-Test":"BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(100000703101)(100105400095)(3002001)(10201501046)(93006095)(93001095)(6041248)(20161123560025)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123562025)(20161123558100)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:DM5PR04MB0922; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:DM5PR04MB0922; ","X-Forefront-PRVS":"04433051BF","X-Forefront-Antispam-Report":"SFV:NSPM;\n\tSFS:(10019020)(6009001)(346002)(376002)(199003)(24454002)(189002)(377454003)(8676002)(16586007)(3846002)(6246003)(6306002)(59536001)(61266001)(189998001)(7736002)(105586002)(9686003)(229853002)(498394004)(47776003)(53546010)(2860700003)(61726006)(66066001)(478600001)(68736007)(8936002)(6116002)(9896002)(81156014)(97736004)(2906002)(98316002)(69596002)(316002)(107886003)(6862004)(305945005)(54906003)(5820100001)(22416003)(81166006)(106356001)(53936002)(50986999)(101416001)(5660300001)(23676002)(122856001)(55446002)(54356999)(4326008)(76176999)(42186006)(2950100002)(63696999)(93516999)(966005)(50466002)(575784001)(43066003)(55456009);\n\tDIR:OUT; SFP:1102; SCL:1; SRVR:DM5PR04MB0922;\n\tH:mail-it0-f47.google.com; FPR:; \n\tSPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: ni.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"ni.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"27 Sep 2017 15:45:07.3325\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"87ba1f9a-44cd-43a6-b008-6fdb45a5204e","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM5PR04MB0922","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_04:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_policy_notspam\n\tpolicy=outbound_policy score=30\n\tpriorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0\n\tbulkscore=0\n\tspamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0\n\tadultscore=0\n\tclassifier=spam adjust=30 reason=mlx scancount=1\n\tengine=8.0.1-1707230000\n\tdefinitions=main-1709270217","Cc":"huangtao , u-boot ,\n\tJoe Hershberger ,\n\tAndy Yan , chenjh@rock-chips.com","Subject":"Re: [U-Boot] [PATCH 4/6] net: gmac_rockchip: Define the gmac grf\n\tregister struct at gmac_rockchip.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Reply-To":"joe.hershberger@gmail.com","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1781396,"web_url":"http://patchwork.ozlabs.org/comment/1781396/","msgid":"","list_archive_url":null,"date":"2017-10-06T10:06:56","subject":"Re: [U-Boot] [U-Boot,\n\t4/6] net: gmac_rockchip: Define the gmac grf register struct at\n\tgmac_rockchip.c","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"On Thu, 21 Sep 2017, David Wu wrote:\n\n> If we include both the rk3288_grf.h and rv1108_grf.h, there is a\n> number of compiling error for redefinition. So we define the reg\n> structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,\n> give them own grf offset for their use.\n\nThe reg offset should not be open-coded in gmac_rockchip.c.\n\nThe issue of GRF-header having conflicting definitions was already\ndiscussed on the list, when I initially submitted the RK3368 support.\nThe decision back then was as follows:\n1/ The GRF files should not contain definitions that are private to\n the IOMUX (e.g. these should go into the pinctrl-driver), etc.\n2/ As an intermediate step, we move some of this (i.e. the GMAC_CLK_SEL\n definitions into gmac_rockchip.c.\n3/ The long-term solution will be to either create misc-devices that\n handle the 'set-to-rgmii' functionality and the 'GMAC_CLK_SEL'\n bits (although on those, modelling it via the clk-framework might\n be more appropriate).\n\nPlease clean up the affected GRF files that cause the conflicts (e.g.\nthe RV1108) and extend the current implementation w/o open-coding a\ngrf-offet.\n\nAdditional requested changes below.\n\n>\n> Signed-off-by: David Wu \n> Acked-by: Philipp Tomsich \n> ---\n>\n> drivers/net/gmac_rockchip.c | 144 +++++++++++++++++++++++++++++++++++---------\n> 1 file changed, 116 insertions(+), 28 deletions(-)\n>\n> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c\n> index 586ccbf..5f8f0cd 100644\n> --- a/drivers/net/gmac_rockchip.c\n> +++ b/drivers/net/gmac_rockchip.c\n> @@ -15,9 +15,6 @@\n> #include \n> #include \n> #include \n> -#include \n> -#include \n> -#include \n> #include \n> #include \n> #include \"designware.h\"\n> @@ -31,15 +28,37 @@ DECLARE_GLOBAL_DATA_PTR;\n> */\n> struct gmac_rockchip_platdata {\n> \tstruct dw_eth_pdata dw_eth_pdata;\n> +\tvoid *grf;\n> \tint tx_delay;\n> \tint rx_delay;\n> };\n>\n> struct rk_gmac_ops {\n> -\tint (*fix_mac_speed)(struct dw_eth_dev *priv);\n> +\tint (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,\n> +\t\t\t struct dw_eth_dev *priv);\n> \tvoid (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);\n> };\n>\n> +struct gmac_rockchip_driver_data {\n> +\tconst struct rk_gmac_ops *ops;\n> +\tunsigned int grf_offset;\n> +};\n> +\n> +struct rk3288_mac_grf {\n> +\tu32 soc_con1;\n> +\tu32 reserved;\n> +\tu32 soc_con3;\n> +};\n> +\n> +struct rk3368_mac_grf {\n> +\tu32 soc_con15;\n> +\tu32 soc_con16;\n> +};\n> +\n> +struct rk3399_mac_grf {\n> +\tu32 soc_con5;\n> +\tu32 soc_con6;\n> +};\n\nWe really can't pollute the GMAC driver with these definitions.\nThe actual values need to come out of the central GRF structure \ndefinition.\n\n>\n> static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)\n> {\n> @@ -58,10 +77,18 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)\n> \treturn designware_eth_ofdata_to_platdata(dev);\n> }\n>\n> -static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> +static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,\n> +\t\t\t\t struct dw_eth_dev *priv)\n> {\n> -\tstruct rk3288_grf *grf;\n> +\tstruct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;\n> \tint clk;\n> +\tenum {\n> +\t\tRK3288_GMAC_CLK_SEL_SHIFT = 12,\n> +\t\tRK3288_GMAC_CLK_SEL_MASK = GENMASK(13, 12),\n> +\t\tRK3288_GMAC_CLK_SEL_125M = 0 << 12,\n> +\t\tRK3288_GMAC_CLK_SEL_25M = 3 << 12,\n> +\t\tRK3288_GMAC_CLK_SEL_2_5M = 2 << 12,\n> +\t};\n>\n> \tswitch (priv->phydev->speed) {\n> \tcase 10:\n> @@ -78,15 +105,15 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> \t\treturn -EINVAL;\n> \t}\n>\n> -\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> \trk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);\n>\n> \treturn 0;\n> }\n>\n> -static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> +static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,\n> +\t\t\t\t struct dw_eth_dev *priv)\n> {\n> -\tstruct rk3368_grf *grf;\n> +\tstruct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;\n> \tint clk;\n> \tenum {\n> \t\tRK3368_GMAC_CLK_SEL_2_5M = 2 << 4,\n> @@ -110,16 +137,22 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> \t\treturn -EINVAL;\n> \t}\n>\n> -\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> \trk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);\n>\n> \treturn 0;\n> }\n>\n> -static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> +static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata *pdata,\n> +\t\t\t\t struct dw_eth_dev *priv)\n> {\n> -\tstruct rk3399_grf_regs *grf;\n> +\tstruct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;\n> \tint clk;\n> +\tenum {\n> +\t\tRK3399_GMAC_CLK_SEL_MASK = GENMASK(6, 4),\n> +\t\tRK3399_GMAC_CLK_SEL_125M = 0 << 4,\n> +\t\tRK3399_GMAC_CLK_SEL_25M\t = 3 << 4,\n> +\t\tRK3399_GMAC_CLK_SEL_2_5M = 2 << 4,\n> +\t};\n>\n> \tswitch (priv->phydev->speed) {\n> \tcase 10:\n> @@ -136,7 +169,6 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n> \t\treturn -EINVAL;\n> \t}\n>\n> -\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> \trk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);\n>\n> \treturn 0;\n> @@ -144,9 +176,31 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n>\n> static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> {\n> -\tstruct rk3288_grf *grf;\n> +\tstruct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;\n> +\tenum {\n> +\t\tRK3288_RMII_MODE_SHIFT = 14,\n> +\t\tRK3288_RMII_MODE_MASK = BIT(14),\n> +\n> +\t\tRK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,\n> +\t\tRK3288_GMAC_PHY_INTF_SEL_MASK = GENMASK(8, 6),\n> +\t\tRK3288_GMAC_PHY_INTF_SEL_RGMII = BIT(6),\n> +\t};\n> +\tenum {\n> +\t\tRK3288_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),\n> +\t\tRK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> +\t\tRK3288_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),\n> +\n> +\t\tRK3288_TXCLK_DLY_ENA_GMAC_MASK = BIT(14),\n> +\t\tRK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> +\t\tRK3288_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(14),\n> +\n> +\t\tRK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,\n> +\t\tRK3288_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),\n> +\n> +\t\tRK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,\n> +\t\tRK3288_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n> +\t};\n>\n> -\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> \trk_clrsetreg(&grf->soc_con1,\n> \t\t RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,\n> \t\t RK3288_GMAC_PHY_INTF_SEL_RGMII);\n> @@ -164,7 +218,7 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n>\n> static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> {\n> -\tstruct rk3368_grf *grf;\n> +\tstruct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;\n> \tenum {\n> \t\tRK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,\n> \t\tRK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),\n> @@ -184,7 +238,6 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> \t\tRK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n> \t};\n>\n> -\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> \trk_clrsetreg(&grf->soc_con15,\n> \t\t RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,\n> \t\t RK3368_GMAC_PHY_INTF_SEL_RGMII);\n> @@ -202,9 +255,24 @@ static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n>\n> static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> {\n> -\tstruct rk3399_grf_regs *grf;\n> -\n> -\tgrf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n> +\tstruct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;\n> +\tenum {\n> +\t\tRK3399_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),\n> +\t\tRK3399_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,\n> +\t\tRK3399_GMAC_PHY_INTF_SEL_RMII = 4 << 9,\n> +\t};\n> +\tenum {\n> +\t\tRK3399_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),\n> +\t\tRK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> +\t\tRK3399_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),\n> +\t\tRK3399_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),\n> +\t\tRK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,\n> +\t\tRK3399_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),\n> +\t\tRK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,\n> +\t\tRK3399_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),\n> +\t\tRK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,\n> +\t\tRK3399_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n> +\t};\n>\n> \trk_clrsetreg(&grf->soc_con5,\n> \t\t RK3399_GMAC_PHY_INTF_SEL_MASK,\n> @@ -224,8 +292,9 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)\n> static int gmac_rockchip_probe(struct udevice *dev)\n> {\n> \tstruct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);\n> -\tstruct rk_gmac_ops *ops =\n> -\t\t(struct rk_gmac_ops *)dev_get_driver_data(dev);\n> +\tstruct gmac_rockchip_driver_data *data =\n> +\t\t(struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);\n> +\tconst struct rk_gmac_ops *ops = data->ops;\n> \tstruct clk clk;\n> \tint ret;\n>\n> @@ -238,6 +307,9 @@ static int gmac_rockchip_probe(struct udevice *dev)\n> \tif (ret)\n> \t\treturn ret;\n>\n> +\tpdata->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF) +\n> +\t\t data->grf_offset;\n> +\n> \t/* Set to RGMII mode */\n> \tops->set_to_rgmii(pdata);\n>\n> @@ -248,14 +320,15 @@ static int gmac_rockchip_eth_start(struct udevice *dev)\n> {\n> \tstruct eth_pdata *pdata = dev_get_platdata(dev);\n> \tstruct dw_eth_dev *priv = dev_get_priv(dev);\n> -\tstruct rk_gmac_ops *ops =\n> -\t\t(struct rk_gmac_ops *)dev_get_driver_data(dev);\n> +\tstruct gmac_rockchip_driver_data *data =\n> +\t (struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);\n> +\tconst struct rk_gmac_ops *ops = data->ops;\n> \tint ret;\n>\n> \tret = designware_eth_init(priv, pdata->enetaddr);\n> \tif (ret)\n> \t\treturn ret;\n> -\tret = ops->fix_mac_speed(priv);\n> +\tret = ops->fix_mac_speed((struct gmac_rockchip_platdata *)pdata, priv);\n> \tif (ret)\n> \t\treturn ret;\n> \tret = designware_eth_enable(priv);\n> @@ -279,23 +352,38 @@ const struct rk_gmac_ops rk3288_gmac_ops = {\n> \t.set_to_rgmii = rk3288_gmac_set_to_rgmii,\n> };\n>\n> +const struct gmac_rockchip_driver_data rk3288_gmac_data = {\n> +\t.ops\t\t= &rk3288_gmac_ops,\n> +\t.grf_offset\t= 0x248,\n> +};\n> +\n> const struct rk_gmac_ops rk3368_gmac_ops = {\n> \t.fix_mac_speed = rk3368_gmac_fix_mac_speed,\n> \t.set_to_rgmii = rk3368_gmac_set_to_rgmii,\n> };\n>\n> +const struct gmac_rockchip_driver_data rk3368_gmac_data = {\n> +\t.ops\t\t= &rk3368_gmac_ops,\n> +\t.grf_offset\t= 0x43c,\n> +};\n> +\n> const struct rk_gmac_ops rk3399_gmac_ops = {\n> \t.fix_mac_speed = rk3399_gmac_fix_mac_speed,\n> \t.set_to_rgmii = rk3399_gmac_set_to_rgmii,\n> };\n>\n> +const struct gmac_rockchip_driver_data rk3399_gmac_data = {\n> +\t.ops\t\t= &rk3399_gmac_ops,\n> +\t.grf_offset\t= 0xc214,\n\nThe grf_offset really can not be hardcoded here.\n\n> +};\n> +\n> static const struct udevice_id rockchip_gmac_ids[] = {\n> \t{ .compatible = \"rockchip,rk3288-gmac\",\n> -\t .data = (ulong)&rk3288_gmac_ops },\n> +\t .data = (ulong)&rk3288_gmac_data },\n> \t{ .compatible = \"rockchip,rk3368-gmac\",\n> -\t .data = (ulong)&rk3368_gmac_ops },\n> +\t .data = (ulong)&rk3368_gmac_data },\n> \t{ .compatible = \"rockchip,rk3399-gmac\",\n> -\t .data = (ulong)&rk3399_gmac_ops },\n> +\t .data = (ulong)&rk3399_gmac_data },\n> \t{ }\n> };\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y7lg55yskz9t48\n\tfor ;\n\tFri, 6 Oct 2017 21:07:13 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid F0A71C21E0A; Fri, 6 Oct 2017 10:07:10 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 43862C21C40;\n\tFri, 6 Oct 2017 10:07:06 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 32912C21C40; Fri, 6 Oct 2017 10:07:05 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 83A61C21C3F\n\tfor ; Fri, 6 Oct 2017 10:07:02 +0000 (UTC)","from [86.59.122.178] (port=51517 helo=android.lan)\n\tby mail.theobroma-systems.com with esmtps\n\t(TLS1.2:RSA_AES_128_CBC_SHA1:128)\n\t(Exim 4.80) (envelope-from )\n\tid 1e0PX1-00047z-It; Fri, 06 Oct 2017 12:06:59 +0200","from [10.11.0.14] (helo=vpn-10-11-0-14.lan)\n\tby android.lan with esmtp (Exim 4.84_2)\n\t(envelope-from )\n\tid 1e0PX1-000FFs-5r; Fri, 06 Oct 2017 12:06:59 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","Date":"Fri, 6 Oct 2017 12:06:56 +0200 (CEST)","From":"Philipp Tomsich ","X-X-Sender":"ptomsich@vpn-10-11-0-14.lan","To":"David Wu ","In-Reply-To":"<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>","Message-ID":"","References":"<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>","User-Agent":"Alpine 2.21 (OSX 202 2017-01-01)","MIME-Version":"1.0","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de,\n\tJoe Hershberger , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t4/6] net: gmac_rockchip: Define the gmac grf register struct at\n\tgmac_rockchip.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1788297,"web_url":"http://patchwork.ozlabs.org/comment/1788297/","msgid":"","list_archive_url":null,"date":"2017-10-17T11:52:56","subject":"Re: [U-Boot] [U-Boot,\n\t4/6] net: gmac_rockchip: Define the gmac grf register struct at\n\tgmac_rockchip.c","submitter":{"id":68083,"url":"http://patchwork.ozlabs.org/api/people/68083/","name":"David Wu","email":"david.wu@rock-chips.com"},"content":"Hi Philipp,\n\n在 2017/10/6 18:06, Philipp Tomsich 写道:\n> \n> \n> On Thu, 21 Sep 2017, David Wu wrote:\n> \n>> If we include both the rk3288_grf.h and rv1108_grf.h, there is a\n>> number of compiling error for redefinition. So we define the reg\n>> structs of mac_grf at gmac_rockchip.c. Remove the rk**_grf.h files,\n>> give them own grf offset for their use.\n> \n> The reg offset should not be open-coded in gmac_rockchip.c.\n> \n> The issue of GRF-header having conflicting definitions was already\n> discussed on the list, when I initially submitted the RK3368 support.\n> The decision back then was as follows:\n> 1/ The GRF files should not contain definitions that are private to\n>    the IOMUX (e.g. these should go into the pinctrl-driver), etc.\n\nI'll try to move all the iomux definitions at GRF-header into \npinctrl-driver, use pinctrl_request* interface to set iomux in some \nboard.c file.\n\n> 2/ As an intermediate step, we move some of this (i.e. the GMAC_CLK_SEL\n>    definitions into gmac_rockchip.c.\n\nI still think the 'GMAC_CLK_SEL' bit set should be implemented at clk \ndriver.\n\n> 3/ The long-term solution will be to either create misc-devices that\n>    handle the 'set-to-rgmii' functionality and the 'GMAC_CLK_SEL'\n>    bits (although on those, modelling it via the clk-framework might\n>    be more appropriate).\n\nCould you give me a example code for misc-devices?\n\n> \n> Please clean up the affected GRF files that cause the conflicts (e.g.\n> the RV1108) and extend the current implementation w/o open-coding a\n> grf-offet.\n> \n> Additional requested changes below.\n> \n>>\n>> Signed-off-by: David Wu \n>> Acked-by: Philipp Tomsich \n>> ---\n>>\n>> drivers/net/gmac_rockchip.c | 144 \n>> +++++++++++++++++++++++++++++++++++---------\n>> 1 file changed, 116 insertions(+), 28 deletions(-)\n>>\n>> diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c\n>> index 586ccbf..5f8f0cd 100644\n>> --- a/drivers/net/gmac_rockchip.c\n>> +++ b/drivers/net/gmac_rockchip.c\n>> @@ -15,9 +15,6 @@\n>> #include \n>> #include \n>> #include \n>> -#include \n>> -#include \n>> -#include \n>> #include \n>> #include \n>> #include \"designware.h\"\n>> @@ -31,15 +28,37 @@ DECLARE_GLOBAL_DATA_PTR;\n>>  */\n>> struct gmac_rockchip_platdata {\n>>     struct dw_eth_pdata dw_eth_pdata;\n>> +    void *grf;\n>>     int tx_delay;\n>>     int rx_delay;\n>> };\n>>\n>> struct rk_gmac_ops {\n>> -    int (*fix_mac_speed)(struct dw_eth_dev *priv);\n>> +    int (*fix_mac_speed)(struct gmac_rockchip_platdata *pdata,\n>> +                 struct dw_eth_dev *priv);\n>>     void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);\n>> };\n>>\n>> +struct gmac_rockchip_driver_data {\n>> +    const struct rk_gmac_ops *ops;\n>> +    unsigned int grf_offset;\n>> +};\n>> +\n>> +struct rk3288_mac_grf {\n>> +    u32 soc_con1;\n>> +    u32 reserved;\n>> +    u32 soc_con3;\n>> +};\n>> +\n>> +struct rk3368_mac_grf {\n>> +    u32 soc_con15;\n>> +    u32 soc_con16;\n>> +};\n>> +\n>> +struct rk3399_mac_grf {\n>> +    u32 soc_con5;\n>> +    u32 soc_con6;\n>> +};\n> \n> We really can't pollute the GMAC driver with these definitions.\n> The actual values need to come out of the central GRF structure definition.\n> \n>>\n>> static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev)\n>> {\n>> @@ -58,10 +77,18 @@ static int gmac_rockchip_ofdata_to_platdata(struct \n>> udevice *dev)\n>>     return designware_eth_ofdata_to_platdata(dev);\n>> }\n>>\n>> -static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n>> +static int rk3288_gmac_fix_mac_speed(struct gmac_rockchip_platdata \n>> *pdata,\n>> +                     struct dw_eth_dev *priv)\n>> {\n>> -    struct rk3288_grf *grf;\n>> +    struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;\n>>     int clk;\n>> +    enum {\n>> +        RK3288_GMAC_CLK_SEL_SHIFT = 12,\n>> +        RK3288_GMAC_CLK_SEL_MASK  = GENMASK(13, 12),\n>> +        RK3288_GMAC_CLK_SEL_125M  = 0 << 12,\n>> +        RK3288_GMAC_CLK_SEL_25M   = 3 << 12,\n>> +        RK3288_GMAC_CLK_SEL_2_5M  = 2 << 12,\n>> +    };\n>>\n>>     switch (priv->phydev->speed) {\n>>     case 10:\n>> @@ -78,15 +105,15 @@ static int rk3288_gmac_fix_mac_speed(struct \n>> dw_eth_dev *priv)\n>>         return -EINVAL;\n>>     }\n>>\n>> -    grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n>>     rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk);\n>>\n>>     return 0;\n>> }\n>>\n>> -static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n>> +static int rk3368_gmac_fix_mac_speed(struct gmac_rockchip_platdata \n>> *pdata,\n>> +                     struct dw_eth_dev *priv)\n>> {\n>> -    struct rk3368_grf *grf;\n>> +    struct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;\n>>     int clk;\n>>     enum {\n>>         RK3368_GMAC_CLK_SEL_2_5M = 2 << 4,\n>> @@ -110,16 +137,22 @@ static int rk3368_gmac_fix_mac_speed(struct \n>> dw_eth_dev *priv)\n>>         return -EINVAL;\n>>     }\n>>\n>> -    grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n>>     rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk);\n>>\n>>     return 0;\n>> }\n>>\n>> -static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv)\n>> +static int rk3399_gmac_fix_mac_speed(struct gmac_rockchip_platdata \n>> *pdata,\n>> +                     struct dw_eth_dev *priv)\n>> {\n>> -    struct rk3399_grf_regs *grf;\n>> +    struct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;\n>>     int clk;\n>> +    enum {\n>> +        RK3399_GMAC_CLK_SEL_MASK  = GENMASK(6, 4),\n>> +        RK3399_GMAC_CLK_SEL_125M  = 0 << 4,\n>> +        RK3399_GMAC_CLK_SEL_25M      = 3 << 4,\n>> +        RK3399_GMAC_CLK_SEL_2_5M  = 2 << 4,\n>> +    };\n>>\n>>     switch (priv->phydev->speed) {\n>>     case 10:\n>> @@ -136,7 +169,6 @@ static int rk3399_gmac_fix_mac_speed(struct \n>> dw_eth_dev *priv)\n>>         return -EINVAL;\n>>     }\n>>\n>> -    grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n>>     rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);\n>>\n>>     return 0;\n>> @@ -144,9 +176,31 @@ static int rk3399_gmac_fix_mac_speed(struct \n>> dw_eth_dev *priv)\n>>\n>> static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata \n>> *pdata)\n>> {\n>> -    struct rk3288_grf *grf;\n>> +    struct rk3288_mac_grf *grf = (struct rk3288_mac_grf *)pdata->grf;\n>> +    enum {\n>> +        RK3288_RMII_MODE_SHIFT = 14,\n>> +        RK3288_RMII_MODE_MASK  = BIT(14),\n>> +\n>> +        RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6,\n>> +        RK3288_GMAC_PHY_INTF_SEL_MASK  = GENMASK(8, 6),\n>> +        RK3288_GMAC_PHY_INTF_SEL_RGMII = BIT(6),\n>> +    };\n>> +    enum {\n>> +        RK3288_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),\n>> +        RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0,\n>> +        RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),\n>> +\n>> +        RK3288_TXCLK_DLY_ENA_GMAC_MASK = BIT(14),\n>> +        RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0,\n>> +        RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(14),\n>> +\n>> +        RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,\n>> +        RK3288_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),\n>> +\n>> +        RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,\n>> +        RK3288_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n>> +    };\n>>\n>> -    grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n>>     rk_clrsetreg(&grf->soc_con1,\n>>              RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK,\n>>              RK3288_GMAC_PHY_INTF_SEL_RGMII);\n>> @@ -164,7 +218,7 @@ static void rk3288_gmac_set_to_rgmii(struct \n>> gmac_rockchip_platdata *pdata)\n>>\n>> static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata \n>> *pdata)\n>> {\n>> -    struct rk3368_grf *grf;\n>> +    struct rk3368_mac_grf *grf = (struct rk3368_mac_grf *)pdata->grf;\n>>     enum {\n>>         RK3368_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,\n>>         RK3368_GMAC_PHY_INTF_SEL_MASK = GENMASK(11, 9),\n>> @@ -184,7 +238,6 @@ static void rk3368_gmac_set_to_rgmii(struct \n>> gmac_rockchip_platdata *pdata)\n>>         RK3368_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n>>     };\n>>\n>> -    grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n>>     rk_clrsetreg(&grf->soc_con15,\n>>              RK3368_RMII_MODE_MASK | RK3368_GMAC_PHY_INTF_SEL_MASK,\n>>              RK3368_GMAC_PHY_INTF_SEL_RGMII);\n>> @@ -202,9 +255,24 @@ static void rk3368_gmac_set_to_rgmii(struct \n>> gmac_rockchip_platdata *pdata)\n>>\n>> static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata \n>> *pdata)\n>> {\n>> -    struct rk3399_grf_regs *grf;\n>> -\n>> -    grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n>> +    struct rk3399_mac_grf *grf = (struct rk3399_mac_grf *)pdata->grf;\n>> +    enum {\n>> +        RK3399_GMAC_PHY_INTF_SEL_MASK  = GENMASK(11, 9),\n>> +        RK3399_GMAC_PHY_INTF_SEL_RGMII = 1 << 9,\n>> +        RK3399_GMAC_PHY_INTF_SEL_RMII  = 4 << 9,\n>> +    };\n>> +    enum {\n>> +        RK3399_RXCLK_DLY_ENA_GMAC_MASK = BIT(15),\n>> +        RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,\n>> +        RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(15),\n>> +        RK3399_TXCLK_DLY_ENA_GMAC_MASK = BIT(7),\n>> +        RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,\n>> +        RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(7),\n>> +        RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,\n>> +        RK3399_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(14, 8),\n>> +        RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,\n>> +        RK3399_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),\n>> +    };\n>>\n>>     rk_clrsetreg(&grf->soc_con5,\n>>              RK3399_GMAC_PHY_INTF_SEL_MASK,\n>> @@ -224,8 +292,9 @@ static void rk3399_gmac_set_to_rgmii(struct \n>> gmac_rockchip_platdata *pdata)\n>> static int gmac_rockchip_probe(struct udevice *dev)\n>> {\n>>     struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);\n>> -    struct rk_gmac_ops *ops =\n>> -        (struct rk_gmac_ops *)dev_get_driver_data(dev);\n>> +    struct gmac_rockchip_driver_data *data =\n>> +        (struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);\n>> +    const struct rk_gmac_ops *ops = data->ops;\n>>     struct clk clk;\n>>     int ret;\n>>\n>> @@ -238,6 +307,9 @@ static int gmac_rockchip_probe(struct udevice *dev)\n>>     if (ret)\n>>         return ret;\n>>\n>> +    pdata->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF) +\n>> +             data->grf_offset;\n>> +\n>>     /* Set to RGMII mode */\n>>     ops->set_to_rgmii(pdata);\n>>\n>> @@ -248,14 +320,15 @@ static int gmac_rockchip_eth_start(struct \n>> udevice *dev)\n>> {\n>>     struct eth_pdata *pdata = dev_get_platdata(dev);\n>>     struct dw_eth_dev *priv = dev_get_priv(dev);\n>> -    struct rk_gmac_ops *ops =\n>> -        (struct rk_gmac_ops *)dev_get_driver_data(dev);\n>> +    struct gmac_rockchip_driver_data *data =\n>> +           (struct gmac_rockchip_driver_data *)dev_get_driver_data(dev);\n>> +    const struct rk_gmac_ops *ops = data->ops;\n>>     int ret;\n>>\n>>     ret = designware_eth_init(priv, pdata->enetaddr);\n>>     if (ret)\n>>         return ret;\n>> -    ret = ops->fix_mac_speed(priv);\n>> +    ret = ops->fix_mac_speed((struct gmac_rockchip_platdata *)pdata, \n>> priv);\n>>     if (ret)\n>>         return ret;\n>>     ret = designware_eth_enable(priv);\n>> @@ -279,23 +352,38 @@ const struct rk_gmac_ops rk3288_gmac_ops = {\n>>     .set_to_rgmii = rk3288_gmac_set_to_rgmii,\n>> };\n>>\n>> +const struct gmac_rockchip_driver_data rk3288_gmac_data = {\n>> +    .ops        = &rk3288_gmac_ops,\n>> +    .grf_offset    = 0x248,\n>> +};\n>> +\n>> const struct rk_gmac_ops rk3368_gmac_ops = {\n>>     .fix_mac_speed = rk3368_gmac_fix_mac_speed,\n>>     .set_to_rgmii = rk3368_gmac_set_to_rgmii,\n>> };\n>>\n>> +const struct gmac_rockchip_driver_data rk3368_gmac_data = {\n>> +    .ops        = &rk3368_gmac_ops,\n>> +    .grf_offset    = 0x43c,\n>> +};\n>> +\n>> const struct rk_gmac_ops rk3399_gmac_ops = {\n>>     .fix_mac_speed = rk3399_gmac_fix_mac_speed,\n>>     .set_to_rgmii = rk3399_gmac_set_to_rgmii,\n>> };\n>>\n>> +const struct gmac_rockchip_driver_data rk3399_gmac_data = {\n>> +    .ops        = &rk3399_gmac_ops,\n>> +    .grf_offset    = 0xc214,\n> \n> The grf_offset really can not be hardcoded here.\n> \n>> +};\n>> +\n>> static const struct udevice_id rockchip_gmac_ids[] = {\n>>     { .compatible = \"rockchip,rk3288-gmac\",\n>> -      .data = (ulong)&rk3288_gmac_ops },\n>> +      .data = (ulong)&rk3288_gmac_data },\n>>     { .compatible = \"rockchip,rk3368-gmac\",\n>> -      .data = (ulong)&rk3368_gmac_ops },\n>> +      .data = (ulong)&rk3368_gmac_data },\n>>     { .compatible = \"rockchip,rk3399-gmac\",\n>> -      .data = (ulong)&rk3399_gmac_ops },\n>> +      .data = (ulong)&rk3399_gmac_data },\n>>     { }\n>> };\n>>\n>>\n> \n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yGYVG6chMz9sPr\n\tfor ;\n\tTue, 17 Oct 2017 22:53:10 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid B2E75C21DA1; Tue, 17 Oct 2017 11:53:09 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 85CBFC21C71;\n\tTue, 17 Oct 2017 11:53:04 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid CBAACC21C71; Tue, 17 Oct 2017 11:53:02 +0000 (UTC)","from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.135])\n\tby lists.denx.de (Postfix) with ESMTPS id 7E610C21C40\n\tfor ; Tue, 17 Oct 2017 11:53:01 +0000 (UTC)","from david.wu?rock-chips.com (unknown [192.168.167.140])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id 802F95E3C;\n\tTue, 17 Oct 2017 19:52:57 +0800 (CST)","from [172.16.12.107] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id B92EF36B;\n\tTue, 17 Oct 2017 19:52:56 +0800 (CST)","from [172.16.12.107] (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 268551VRI9V;\n\tTue, 17 Oct 2017 19:52:57 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"**","X-Spam-Status":"No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL,\n\tRCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no\n\tversion=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"1","X-MAIL-DELIVERY":"0","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"david.wu@rock-chips.com","X-FST-TO":"chenjh@rock-chips.com","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"david.wu@rock-chips.com","X-UNIQUE-TAG":"<8b07f66ed8420c7155c4b71dd5d40c23>","X-ATTACHMENT-NUM":"0","X-SENDER":"wdc@rock-chips.com","X-DNS-TYPE":"0","To":"Philipp Tomsich ","References":"<1506003471-34551-5-git-send-email-david.wu@rock-chips.com>\n\t","From":"\"David.Wu\" ","Message-ID":"","Date":"Tue, 17 Oct 2017 19:52:56 +0800","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de,\n\tJoe Hershberger , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t4/6] net: gmac_rockchip: Define the gmac grf register struct at\n\tgmac_rockchip.c","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]