[{"id":1776648,"web_url":"http://patchwork.ozlabs.org/comment/1776648/","msgid":"<20170927215638.tjbllqq2twdvuivj@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-27T21:56:38","subject":"Re: [RESEND RFC PATCH 4/7] dt-bindings: Document Allwinner DWC HDMI\n\tTX node","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, Sep 20, 2017 at 10:01:21PM +0200, Jernej Skrabec wrote:\n> Add documentation about Allwinner DWC HDMI TX node, found in H3 SoC.\n> \n> Signed-off-by: Jernej Skrabec \n> ---\n> .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++++++++++++++++-\n> 1 file changed, 157 insertions(+), 1 deletion(-)\n> \n> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n> index 92512953943e..cb6aee5c486f 100644\n> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n> @@ -60,6 +60,40 @@ Required properties:\n> first port should be the input endpoint. The second should be the\n> output, usually to an HDMI connector.\n> \n> +DWC HDMI TX Encoder\n> +-----------------------------\n> +\n> +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP\n> +with Allwinner's own PHY IP. It supports audio and video outputs and CEC.\n> +\n> +These DT bindings follow the Synopsys DWC HDMI TX bindings defined in\n> +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the\n> +following device-specific properties.\n> +\n> +Required properties:\n> +\n> + - compatible: value must be one of:\n> + * \"allwinner,sun8i-h3-dw-hdmi\"\n> + - reg: two pairs of base address and size of memory-mapped region, first\n> + for controller and second for PHY\n> + registers.\n> + - reg-io-width: See dw_hdmi.txt. Shall be 1.\n> + - interrupts: HDMI interrupt number\n> + - clocks: phandles to the clocks feeding the HDMI encoder\n> + * iahb: the HDMI interface clock\n> + * isfr: the HDMI module clock\n> + * ddc: the HDMI ddc clock\n> + - clock-names: the clock names mentioned above\n> + - resets: phandles to the reset controllers driving the encoder\n> + * hdmi: the reset line for the HDMI\n> + * ddc: the reset line for the DDC\n> + - reset-names: the reset names mentioned above\n> +\n> + - ports: A ports node with endpoint definitions as defined in\n> + Documentation/devicetree/bindings/media/video-interfaces.txt. The\n> + first port should be the input endpoint. The second should be the\n> + output, usually to an HDMI connector.\n> +\n> TV Encoder\n> ----------\n> \n> @@ -255,7 +289,7 @@ Required properties:\n> - allwinner,pipelines: list of phandle to the display engine\n> frontends (DE 1.0) or mixers (DE 2.0) available.\n> \n> -Example:\n> +Example 1:\n> \n> panel: panel {\n> \tcompatible = \"olimex,lcd-olinuxino-43-ts\";\n> @@ -455,3 +489,125 @@ display-engine {\n> \tcompatible = \"allwinner,sun5i-a13-display-engine\";\n> \tallwinner,pipelines = <&fe0>;\n> };\n> +\n> +Example 2:\n> +\n> +connector {\n> +\tcompatible = \"hdmi-connector\";\n> +\ttype = \"a\";\n> +\n> +\tport {\n> +\t\thdmi_con_in: endpoint {\n> +\t\t\tremote-endpoint = <&hdmi_out_con>;\n> +\t\t};\n> +\t};\n> +};\n> +\n> +de: display-engine {\n> +\tcompatible = \"allwinner,sun8i-h3-display-engine\";\n> +\tallwinner,pipelines = <&mixer0>;\n> +};\n> +\n> +hdmi: hdmi@1ee0000 {\n> +\tcompatible = \"allwinner,h3-dw-hdmi\";\n> +\treg = <0x01ee0000 0x10000>,\n> +\t <0x01ef0000 0x10000>;\n> +\treg-io-width = <1>;\n> +\tinterrupts = ;\n> +\tclocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,\n> +\t\t <&ccu CLK_HDMI_DDC>;\n> +\tclock-names = \"iahb\", \"isfr\", \"ddc\";\n> +\tresets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;\n> +\treset-names = \"hdmi\", \"ddc\";\n> +\n> +\tports {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\thdmi_in: port@0 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\treg = <0>;\n> +\n> +\t\t\thdmi_in_tcon0: endpoint@0 {\n> +\t\t\t\treg = <0>;\n\nYou don't need reg when there's only one.\n\nOtherwise,\n\nAcked-by: Rob Herring \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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