[{"id":1784064,"web_url":"http://patchwork.ozlabs.org/comment/1784064/","msgid":"<28c32a9c-1fd8-3af4-abc6-f4938e138daa@wedev4u.fr>","list_archive_url":null,"date":"2017-10-10T19:23:25","subject":"Re: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles\n\tfrom nv cfg reg","submitter":{"id":70551,"url":"http://patchwork.ozlabs.org/api/people/70551/","name":"Cyrille Pitchen","email":"cyrille.pitchen@wedev4u.fr"},"content":"Hi Matthew\n\nNAK for this patch\n\nLe 20/09/2017 à 20:28, matthew.gerlach@linux.intel.com a écrit :\n> From: Matthew Gerlach \n> \n> This patch is a work around for some non-standard behavior\n> of EPCQ flash parts:\n> \n> https://www.altera.com/documentation/wtw1396921531042.html#wtw1396921651224\n>\n\nFrom the above documentation:\n\"\"\"\nWrite Non-Volatile Configuration Register Operation\n\nYou need to write the non-volatile configuration registers for EPCQ-L\ndevices for different configuration schemes. If you are using the .jic\nfile, the Quartus® Prime programmer sets the number of dummy clock\ncycles and address bytes. If you are using an external programmer tools\n(3rd party programmer tools), you must set the non-volatile\nconfiguration registers.\n\nTo set the non-volatile configuration register, follow these steps:\n\n Execute the write enable operation.\n Execute the write non-volatile configuration register operation.\n Set the 16-bit register value.\n\nSet the 16-bit register value as b'1110 1110 xxxx 1111 where xxxx is the\ndummy clock value. When the xxxx value is from 0001 to 1110, the dummy\nclock value is from 1 to 14. When xxxx is 0000 or 1111, the dummy clock\nvalue is at the default value, which is 8 for standard fast read (AS x1)\nmode and 10 for extended quad input fast read (AS x4) mode.\n\"\"\"\n\nAFAIU, it is stated that you can set the number of dummy cycle to either\n0000b or 1111b, the default value. There is no valid reason to use any\nother value, like there is no valid reason to tune the number of dummy\nclock cycles. Just keep the default settings, please!\n\nIf we start to play changing the number of dummy cycles it would be real\nmess to maintain.\n\nFirst, should we read the value to be used from some register or should\nwe force this value instead by writing that register ?\nSome would prefer reading whereas other would prefer updating...\n\nMoreover, the method to read or write the number of dummy cycles is not\nstandard and is manufacturer specific:\n\n- Micron uses 2 registers: the Volatile Configuration Register and the\nNon-Volatile configuration Register.\n\n- Macronix uses another register but doesn't store the number of dummy\ncycles directly: instead this manufacturer uses codes. So we would have\nto store tables mapping codes <-> number dummy clock cycles\n\n- Spansion/Cypress also uses code tables and I already know that\ndepending on the memory part number the code is either 2bit or 4bit and\nstored in different registers. Damned!\n\nIf I allow you to tune the number of dummy clock cycles for Micron\nmemory it would be fair that I allow other people to tune this number\nfor other memory manufacturers. However it would be a real pain to\nmaintain because there is no standard for that hence manufacturers just\ndo what they want and change things when they want. Far too\nunpredictable, IMHO.\n\nSo to avoid a messy situation, the rule is simple: SPI-NOR memory MUST\nbe configured in their default factory settings when spi_nor_scan() is\ncalled. Your memory has the very same JEDEC ID as some Micron memory,\nthen it should behave the exact same way: in this case the value for the\nnumber of dummy clock cycles should be set to 0000b or 1111b in the NVCR\n(and VCR too).\n\n\n> These flash parts are generally used to configure Intel/Altera FPGAs\n> on power up. These parts report a JEDEC id of the Micron part at the core,\n> but have a different number of dummy cycles than specified in the Micron\n> data sheet. The number of required dummy cycles can be read from the\n> Non-Volatile Configuration register.\n> \n> Signed-off-by: Matthew Gerlach \n> ---\n> drivers/mtd/spi-nor/altera-asmip2.c | 31 ++++++++++++++++++++++++++-----\n> include/linux/mtd/altera-asmip2.h | 3 +++\n> 2 files changed, 29 insertions(+), 5 deletions(-)\n> \n> diff --git a/drivers/mtd/spi-nor/altera-asmip2.c b/drivers/mtd/spi-nor/altera-asmip2.c\n> index a977765..d9cd807 100644\n> --- a/drivers/mtd/spi-nor/altera-asmip2.c\n> +++ b/drivers/mtd/spi-nor/altera-asmip2.c\n> @@ -40,6 +40,10 @@\n> #define QSPI_POLL_TIMEOUT_US\t\t10000000\n> #define QSPI_POLL_INTERVAL_US\t\t5\n> \n> +#define SPINOR_OP_RD_NVCFG\t\t0xb5\n> +#define NVCFG_DUMMY_SFT\t\t\t12\n> +#define NVCFG_DUMMY_MASK\t\t0xf\n> +\n> struct altera_asmip2 {\n> \tvoid __iomem *csr_base;\n> \tu32 num_flashes;\n> @@ -231,7 +235,8 @@ static void altera_asmip2_unprep(struct spi_nor *nor, enum spi_nor_ops ops)\n> }\n> \n> static int altera_asmip2_setup_banks(struct device *dev,\n> -\t\t\t\t u32 bank, struct device_node *np)\n> +\t\t\t\t u32 bank, struct device_node *np,\n> +\t\t\t\t u32 flags)\n> {\n> \tconst struct spi_nor_hwcaps hwcaps = {\n> \t\t.mask = SNOR_HWCAPS_READ |\n> @@ -241,6 +246,7 @@ static int altera_asmip2_setup_banks(struct device *dev,\n> \tstruct altera_asmip2 *q = dev_get_drvdata(dev);\n> \tstruct altera_asmip2_flash *flash;\n> \tstruct spi_nor *nor;\n> +\tu16 nvcfg;\n> \tint ret = 0;\n> \n> \tif (bank > q->num_flashes - 1)\n> @@ -273,6 +279,20 @@ static int altera_asmip2_setup_banks(struct device *dev,\n> \t\treturn ret;\n> \t}\n> \n> +\tif (flags & ALTERA_ASMIP2_FLASH_FLG_RD_NVCFG) {\n> +\t\tret = altera_asmip2_read_reg(nor, SPINOR_OP_RD_NVCFG,\n> +\t\t \t\t\t (u8*)&nvcfg, sizeof(nvcfg));\n> +\n> +\t\tif (ret) {\n> +\t\t\tdev_err(nor->dev,\n> +\t\t\t\t\"failed to read NV Configuration register\\n\");\n> +\t\t\treturn ret;\n> +\t\t}\n> +\n> +\t\tnor->read_dummy = (nvcfg >> NVCFG_DUMMY_SFT) & NVCFG_DUMMY_MASK;\n> +\t\tdev_info(nor->dev, \"%s dummy %d\\n\", __func__, nor->read_dummy);\n> +\t}\n> +\n\nYou have forgotten the special case for values 0000b and 1111b (default\nsettings). For those 2 values, the actual number of dummy clock cycles is:\n- 0 for Read (03h/13h)\n- 8 for Fast Read 1-1-1 (0Bh/0Ch)\n- 8 for Fast Read 1-1-2 (3Bh/3Ch)\n- 8 for Fast Read 1-2-2 (BBh/BCh)\n- 8 for Fast Read 1-1-4 (6Bh/6Ch)\n- 10 for Fast Read 1-4-4 (EBh/ECh)\n\nBesides, the value read from the Non-Volatile Configuration Register is\nthe value loaded into the Volatile Configuration Register at power-up.\nThe actual number of dummy clock cycles to be used by Fast Read commands\nshould be read from the Volatile Configuration Register.\n\nAnyway, this not the way to go.\n\nBest regards,\n\nCyrille\n\n> \tret = mtd_device_register(&nor->mtd, NULL, 0);\n> \n> \treturn ret;\n> @@ -308,7 +328,7 @@ static int altera_asmip2_create(struct device *dev, void __iomem *csr_base)\n> }\n> \n> static int altera_asmip2_add_bank(struct device *dev,\n> -\t\t\t u32 bank, struct device_node *np)\n> +\t\t\t u32 bank, struct device_node *np, u32 flags)\n> {\n> \tstruct altera_asmip2 *q = dev_get_drvdata(dev);\n> \n> @@ -317,7 +337,7 @@ static int altera_asmip2_add_bank(struct device *dev,\n> \n> \tq->num_flashes++;\n> \n> -\treturn altera_asmip2_setup_banks(dev, bank, np);\n> +\treturn altera_asmip2_setup_banks(dev, bank, np, flags);\n> }\n> \n> static int altera_asmip2_remove_banks(struct device *dev)\n> @@ -361,7 +381,8 @@ static int altera_asmip2_probe_with_pdata(struct platform_device *pdev,\n> \t}\n> \n> \tfor (i = 0; i < qdata->num_chip_sel; i++) {\n> -\t\tret = altera_asmip2_add_bank(dev, i, NULL);\n> +\t\tret = altera_asmip2_add_bank(dev, i, NULL,\n> +\t\t\t\t\t qdata->flash_flags[i]);\n> \t\tif (ret) {\n> \t\t\tdev_err(dev, \"failed to add qspi bank %d\\n\", ret);\n> \t\t\tbreak;\n> @@ -414,7 +435,7 @@ static int altera_asmip2_probe(struct platform_device *pdev)\n> \t\t\tgoto error;\n> \t\t}\n> \n> -\t\tif (altera_asmip2_add_bank(dev, bank, pp)) {\n> +\t\tif (altera_asmip2_add_bank(dev, bank, pp, 0)) {\n> \t\t\tdev_err(dev, \"failed to add bank %u\\n\", bank);\n> \t\t\tgoto error;\n> \t\t}\n> diff --git a/include/linux/mtd/altera-asmip2.h b/include/linux/mtd/altera-asmip2.h\n> index 580c43c..185a9b2 100644\n> --- a/include/linux/mtd/altera-asmip2.h\n> +++ b/include/linux/mtd/altera-asmip2.h\n> @@ -16,9 +16,12 @@\n> #define ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP 3\n> #define ALTERA_ASMIP2_RESOURCE_SIZE 0x10\n> \n> +#define ALTERA_ASMIP2_FLASH_FLG_RD_NVCFG\tBIT(0)\n> +\n> struct altera_asmip2_plat_data {\n> \tvoid __iomem *csr_base;\n> \tu32 num_chip_sel;\n> +\tu32 flash_flags[ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP];\n> };\n> \n> #endif\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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Tue, 10 Oct 2017 19:23:58 +0000","from mountainer.wedev4u.int (unknown [82.232.94.13])\n\tby smtp3-g21.free.fr (Postfix) with ESMTP id BCD9F13F89D;\n\tTue, 10 Oct 2017 21:23:25 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Cc:Content-ID:\n\tContent-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n\t:Resent-Message-ID:List-Owner;\n\tbh=gp1rwWydubGaZy7vxKLhtuqVO5dnrS36Qw9w93YK708=;\n\tb=hFK7qd9yM5CIG/S+t8Z14kOtGK\n\thBWF/fweACvOMdcbINq7lyMf/qyKrX7/ndH/DyAPKW0IbTbxjrXtQRDBTO5hruALHOy3NToL106OA\n\tQ/qqezdzIMfledzVS+O7jKxqQqz6MFWqyyTh6R5rcgb/9NYCWx5hEbQnXsQiHzMKXTpr0jQEQP45N\n\t+TflDhZj7hyy7yBlBWaP4KS+i9FsEo3VTZFeZcui0AN/kUyZ36JcQV2AIun9gHm3DGSUuL9QZCoqq\n\tFsnZjv2D5nvWtvCAcg7dtsealLzK/v8ilmqlfOdwbdAYLs5QXM4FzRyEHuZFHPtiPXNkpG2vPHPWE\n\tEwrKMMHA==;","Subject":"Re: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles\n\tfrom nv cfg reg","To":"matthew.gerlach@linux.intel.com, vndao@altera.com, dwmw2@infradead.org, \n\tcomputersforpeace@gmail.com, boris.brezillon@free-electrons.com,\n\tmarek.vasut@gmail.com, richard@nod.at, robh+dt@kernel.org,\n\tmark.rutland@arm.com, linux-mtd@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tgregkh@linuxfoundation.org, davem@davemloft.net, mchehab@kernel.org, \n\tlinux-fpga@vger.kernel.org, tien.hock.loh@intel.com,\n\thean.loong.ong@intel.com","References":"<1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com>\n\t<1505932139-2905-4-git-send-email-matthew.gerlach@linux.intel.com>","From":"Cyrille Pitchen ","Message-ID":"<28c32a9c-1fd8-3af4-abc6-f4938e138daa@wedev4u.fr>","Date":"Tue, 10 Oct 2017 21:23:25 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1505932139-2905-4-git-send-email-matthew.gerlach@linux.intel.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171010_122353_181389_75EFDDDF ","X-CRM114-Status":"GOOD ( 27.81 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a01:e0c:1:1599:0:0:0:12 listed in] [list.dnswl.org]\n\t0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}},{"id":1787648,"web_url":"http://patchwork.ozlabs.org/comment/1787648/","msgid":"","list_archive_url":null,"date":"2017-10-16T18:41:31","subject":"Re: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles\n\tfrom nv cfg reg","submitter":{"id":70992,"url":"http://patchwork.ozlabs.org/api/people/70992/","name":"Matthew Gerlach","email":"matthew.gerlach@linux.intel.com"},"content":"Hi Cyrille,\n\nThanks for the feedback. See my comments in line below.\n\nMatthew Gerlach\n\n\nOn Tue, 10 Oct 2017, Cyrille Pitchen wrote:\n\n> Hi Matthew\n>\n> NAK for this patch\n>\n> Le 20/09/2017 à 20:28, matthew.gerlach@linux.intel.com a écrit :\n>> From: Matthew Gerlach \n>>\n>> This patch is a work around for some non-standard behavior\n>> of EPCQ flash parts:\n>>\n>> https://www.altera.com/documentation/wtw1396921531042.html#wtw1396921651224\n>>\n>\n> From the above documentation:\n> \"\"\"\n> Write Non-Volatile Configuration Register Operation\n>\n> You need to write the non-volatile configuration registers for EPCQ-L\n> devices for different configuration schemes. If you are using the .jic\n> file, the Quartus® Prime programmer sets the number of dummy clock\n> cycles and address bytes. If you are using an external programmer tools\n> (3rd party programmer tools), you must set the non-volatile\n> configuration registers.\n>\n> To set the non-volatile configuration register, follow these steps:\n>\n> Execute the write enable operation.\n> Execute the write non-volatile configuration register operation.\n> Set the 16-bit register value.\n>\n\nThis documentation does not match my experience with the flash. No where\nam I setting the non-volatile configuration register. After power up, I \njust read the register and observe 10 dummy clock cycles, which is the \nonly value that results in successfully reading correct data from the \nflash. I suspect the FPGA is doing the same at power up.\n\n> Set the 16-bit register value as b'1110 1110 xxxx 1111 where xxxx is the\n> dummy clock value. When the xxxx value is from 0001 to 1110, the dummy\n> clock value is from 1 to 14. When xxxx is 0000 or 1111, the dummy clock\n> value is at the default value, which is 8 for standard fast read (AS x1)\n> mode and 10 for extended quad input fast read (AS x4) mode.\n> \"\"\"\n>\n> AFAIU, it is stated that you can set the number of dummy cycle to either\n> 0000b or 1111b, the default value. There is no valid reason to use any\n> other value, like there is no valid reason to tune the number of dummy\n> clock cycles. Just keep the default settings, please!\n\nThe default Micron setting simply does not work.\n\n>\n> If we start to play changing the number of dummy cycles it would be real\n> mess to maintain.\n\nI completely understand the maintainance issue.\n\n>\n> First, should we read the value to be used from some register or should\n> we force this value instead by writing that register ?\n> Some would prefer reading whereas other would prefer updating...\n>\n> Moreover, the method to read or write the number of dummy cycles is not\n> standard and is manufacturer specific:\n\nYes I get it that is manufacturer specific, and this would be another \nexample of yet a different manufacturer's approach.\n\n>\n> - Micron uses 2 registers: the Volatile Configuration Register and the\n> Non-Volatile configuration Register.\n>\n> - Macronix uses another register but doesn't store the number of dummy\n> cycles directly: instead this manufacturer uses codes. So we would have\n> to store tables mapping codes <-> number dummy clock cycles\n>\n> - Spansion/Cypress also uses code tables and I already know that\n> depending on the memory part number the code is either 2bit or 4bit and\n> stored in different registers. Damned!\n>\n> If I allow you to tune the number of dummy clock cycles for Micron\n> memory it would be fair that I allow other people to tune this number\n> for other memory manufacturers. However it would be a real pain to\n> maintain because there is no standard for that hence manufacturers just\n> do what they want and change things when they want. Far too\n> unpredictable, IMHO.\n>\n> So to avoid a messy situation, the rule is simple: SPI-NOR memory MUST\n> be configured in their default factory settings when spi_nor_scan() is\n> called. Your memory has the very same JEDEC ID as some Micron memory,\n> then it should behave the exact same way: in this case the value for the\n> number of dummy clock cycles should be set to 0000b or 1111b in the NVCR\n> (and VCR too).\n\nI think this is crux of the problem. The flash chip is essentially lying \nabout what kind of chip it is. It says it is a Micron memory, but it \ncertainly is not behaving like a Micron chip. I believe the purpose of \nthese EPCQ chips is somehow make it easier for the FPGA to configure \nitself on power up, but it is doing it in a very non-standard and \nnon-maintainable way. I believe the FPGA is reading dummy cycles from the\nNVCR on power up. How else would it know how many dummy cycles to use?\n\n\nThe good news is that these chips are on path to \nend of life, and moving forward we will be using standard flash parts. \nThe bad news is that there are a lot of these chips already in the wild, \nand I suspect more are in the pipeline.\n\nAt this point I see no path forward to being able to upstream support for \nthese EPCQ chips.\n\n>\n>\n>> These flash parts are generally used to configure Intel/Altera FPGAs\n>> on power up. These parts report a JEDEC id of the Micron part at the core,\n>> but have a different number of dummy cycles than specified in the Micron\n>> data sheet. The number of required dummy cycles can be read from the\n>> Non-Volatile Configuration register.\n>>\n>> Signed-off-by: Matthew Gerlach \n>> ---\n>> drivers/mtd/spi-nor/altera-asmip2.c | 31 ++++++++++++++++++++++++++-----\n>> include/linux/mtd/altera-asmip2.h | 3 +++\n>> 2 files changed, 29 insertions(+), 5 deletions(-)\n>>\n>> diff --git a/drivers/mtd/spi-nor/altera-asmip2.c b/drivers/mtd/spi-nor/altera-asmip2.c\n>> index a977765..d9cd807 100644\n>> --- a/drivers/mtd/spi-nor/altera-asmip2.c\n>> +++ b/drivers/mtd/spi-nor/altera-asmip2.c\n>> @@ -40,6 +40,10 @@\n>> #define QSPI_POLL_TIMEOUT_US\t\t10000000\n>> #define QSPI_POLL_INTERVAL_US\t\t5\n>>\n>> +#define SPINOR_OP_RD_NVCFG\t\t0xb5\n>> +#define NVCFG_DUMMY_SFT\t\t\t12\n>> +#define NVCFG_DUMMY_MASK\t\t0xf\n>> +\n>> struct altera_asmip2 {\n>> \tvoid __iomem *csr_base;\n>> \tu32 num_flashes;\n>> @@ -231,7 +235,8 @@ static void altera_asmip2_unprep(struct spi_nor *nor, enum spi_nor_ops ops)\n>> }\n>>\n>> static int altera_asmip2_setup_banks(struct device *dev,\n>> -\t\t\t\t u32 bank, struct device_node *np)\n>> +\t\t\t\t u32 bank, struct device_node *np,\n>> +\t\t\t\t u32 flags)\n>> {\n>> \tconst struct spi_nor_hwcaps hwcaps = {\n>> \t\t.mask = SNOR_HWCAPS_READ |\n>> @@ -241,6 +246,7 @@ static int altera_asmip2_setup_banks(struct device *dev,\n>> \tstruct altera_asmip2 *q = dev_get_drvdata(dev);\n>> \tstruct altera_asmip2_flash *flash;\n>> \tstruct spi_nor *nor;\n>> +\tu16 nvcfg;\n>> \tint ret = 0;\n>>\n>> \tif (bank > q->num_flashes - 1)\n>> @@ -273,6 +279,20 @@ static int altera_asmip2_setup_banks(struct device *dev,\n>> \t\treturn ret;\n>> \t}\n>>\n>> +\tif (flags & ALTERA_ASMIP2_FLASH_FLG_RD_NVCFG) {\n>> +\t\tret = altera_asmip2_read_reg(nor, SPINOR_OP_RD_NVCFG,\n>> +\t\t \t\t\t (u8*)&nvcfg, sizeof(nvcfg));\n>> +\n>> +\t\tif (ret) {\n>> +\t\t\tdev_err(nor->dev,\n>> +\t\t\t\t\"failed to read NV Configuration register\\n\");\n>> +\t\t\treturn ret;\n>> +\t\t}\n>> +\n>> +\t\tnor->read_dummy = (nvcfg >> NVCFG_DUMMY_SFT) & NVCFG_DUMMY_MASK;\n>> +\t\tdev_info(nor->dev, \"%s dummy %d\\n\", __func__, nor->read_dummy);\n>> +\t}\n>> +\n>\n> You have forgotten the special case for values 0000b and 1111b (default\n> settings). For those 2 values, the actual number of dummy clock cycles is:\n> - 0 for Read (03h/13h)\n> - 8 for Fast Read 1-1-1 (0Bh/0Ch)\n> - 8 for Fast Read 1-1-2 (3Bh/3Ch)\n> - 8 for Fast Read 1-2-2 (BBh/BCh)\n> - 8 for Fast Read 1-1-4 (6Bh/6Ch)\n> - 10 for Fast Read 1-4-4 (EBh/ECh)\n>\n> Besides, the value read from the Non-Volatile Configuration Register is\n> the value loaded into the Volatile Configuration Register at power-up.\n> The actual number of dummy clock cycles to be used by Fast Read commands\n> should be read from the Volatile Configuration Register.\n>\n> Anyway, this not the way to go.\n>\n> Best regards,\n>\n> Cyrille\n>\n>> \tret = mtd_device_register(&nor->mtd, NULL, 0);\n>>\n>> \treturn ret;\n>> @@ -308,7 +328,7 @@ static int altera_asmip2_create(struct device *dev, void __iomem *csr_base)\n>> }\n>>\n>> static int altera_asmip2_add_bank(struct device *dev,\n>> -\t\t\t u32 bank, struct device_node *np)\n>> +\t\t\t u32 bank, struct device_node *np, u32 flags)\n>> {\n>> \tstruct altera_asmip2 *q = dev_get_drvdata(dev);\n>>\n>> @@ -317,7 +337,7 @@ static int altera_asmip2_add_bank(struct device *dev,\n>>\n>> \tq->num_flashes++;\n>>\n>> -\treturn altera_asmip2_setup_banks(dev, bank, np);\n>> +\treturn altera_asmip2_setup_banks(dev, bank, np, flags);\n>> }\n>>\n>> static int altera_asmip2_remove_banks(struct device *dev)\n>> @@ -361,7 +381,8 @@ static int altera_asmip2_probe_with_pdata(struct platform_device *pdev,\n>> \t}\n>>\n>> \tfor (i = 0; i < qdata->num_chip_sel; i++) {\n>> -\t\tret = altera_asmip2_add_bank(dev, i, NULL);\n>> +\t\tret = altera_asmip2_add_bank(dev, i, NULL,\n>> +\t\t\t\t\t qdata->flash_flags[i]);\n>> \t\tif (ret) {\n>> \t\t\tdev_err(dev, \"failed to add qspi bank %d\\n\", ret);\n>> \t\t\tbreak;\n>> @@ -414,7 +435,7 @@ static int altera_asmip2_probe(struct platform_device *pdev)\n>> \t\t\tgoto error;\n>> \t\t}\n>>\n>> -\t\tif (altera_asmip2_add_bank(dev, bank, pp)) {\n>> +\t\tif (altera_asmip2_add_bank(dev, bank, pp, 0)) {\n>> \t\t\tdev_err(dev, \"failed to add bank %u\\n\", bank);\n>> \t\t\tgoto error;\n>> \t\t}\n>> diff --git a/include/linux/mtd/altera-asmip2.h b/include/linux/mtd/altera-asmip2.h\n>> index 580c43c..185a9b2 100644\n>> --- a/include/linux/mtd/altera-asmip2.h\n>> +++ b/include/linux/mtd/altera-asmip2.h\n>> @@ -16,9 +16,12 @@\n>> #define ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP 3\n>> #define ALTERA_ASMIP2_RESOURCE_SIZE 0x10\n>>\n>> +#define ALTERA_ASMIP2_FLASH_FLG_RD_NVCFG\tBIT(0)\n>> +\n>> struct altera_asmip2_plat_data {\n>> \tvoid __iomem *csr_base;\n>> \tu32 num_chip_sel;\n>> +\tu32 flash_flags[ALTERA_ASMIP2_MAX_NUM_FLASH_CHIP];\n>> };\n>>\n>> #endif\n>>\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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d=\"scan'208\";a=\"163275489\"","Date":"Mon, 16 Oct 2017 11:41:31 -0700 (PDT)","From":"matthew.gerlach@linux.intel.com","X-X-Sender":"mgerlach@mgerlach-VirtualBox","To":"Cyrille Pitchen ","Subject":"Re: [PATCH v2 3/3] mtd: spi-nor: add flag for reading dummy cycles\n\tfrom nv cfg reg","In-Reply-To":"<28c32a9c-1fd8-3af4-abc6-f4938e138daa@wedev4u.fr>","Message-ID":"","References":"<1505932139-2905-1-git-send-email-matthew.gerlach@linux.intel.com>\n\t<1505932139-2905-4-git-send-email-matthew.gerlach@linux.intel.com>\n\t<28c32a9c-1fd8-3af4-abc6-f4938e138daa@wedev4u.fr>","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"multipart/mixed; BOUNDARY=\"8323329-231588532-1508179293=:19479\"","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171016_114156_228097_AC03F4C8 ","X-CRM114-Status":"GOOD ( 39.82 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [192.55.52.43 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-mtd@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"Linux MTD discussion mailing list ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"vndao@altera.com, boris.brezillon@free-electrons.com, mchehab@kernel.org,\n\tdevicetree@vger.kernel.org, hean.loong.ong@intel.com, richard@nod.at, \n\tlinux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmarek.vasut@gmail.com, robh+dt@kernel.org,\n\tlinux-mtd@lists.infradead.org, \n\tgregkh@linuxfoundation.org, mark.rutland@arm.com,\n\tcomputersforpeace@gmail.com, \n\tdwmw2@infradead.org, davem@davemloft.net, tien.hock.loh@intel.com","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"}}]