[{"id":1771812,"web_url":"http://patchwork.ozlabs.org/comment/1771812/","msgid":"<20170920124726.GA26836@leverpostej>","list_archive_url":null,"date":"2017-09-20T12:47:26","subject":"Re: [PATCH v2] bootwrapper: SVE: Enable SVE for EL2 and below","submitter":{"id":8806,"url":"http://patchwork.ozlabs.org/api/people/8806/","name":"Mark Rutland","email":"mark.rutland@arm.com"},"content":"On Wed, Sep 20, 2017 at 01:09:48PM +0100, Dave Martin wrote:\n> By default, SVE will trap to EL3.  We also want to make sure that\n> lower ELs have access to the full SVE vector length before dropping\n> down.\n> \n> This patch programs CPTR_EL3 and ZCR_EL3 appropriately to enable\n> SVE for lower exception levels and make sure that they can use the\n> full vector length provided by the hardware.\n> \n> Signed-off-by: Dave Martin <Dave.Martin@arm.com>\n> Cc: Mark Rutland <mark.rutland@arm.com>\n> Cc: Alex Bennée <alex.bennee@linaro.org>\n\nThis looks fine, builds with my toolchain collection, and I assume\nyou've boot-tested this.\n\nI've pushed this out now.\n\nThanks,\nMark.\n\n> ---\n> \n> This is basically the same as v1 [1], but rebased to an up-to-date\n> bootwrapper tree.  (I was previously tracking Catalin's tree, which no\n> longer exists...)\n> \n> [1] [PATCH] bootwrapper: SVE: Enable SVE for EL2 and below\n> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/527000.html\n> \n> \n>  arch/aarch64/boot.S            | 13 +++++++++++++\n>  arch/aarch64/include/asm/cpu.h |  5 +++++\n>  2 files changed, 18 insertions(+)\n> \n> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S\n> index ceeee76..f7d795a 100644\n> --- a/arch/aarch64/boot.S\n> +++ b/arch/aarch64/boot.S\n> @@ -45,6 +45,19 @@ _start:\n>  \n>  \tmsr\tcptr_el3, xzr\t\t\t// Disable copro. traps to EL3\n>  \n> +\tmrs\tx0, id_aa64pfr0_el1\n> +\tubfx\tx0, x0, #32, #4\t\t\t// SVE present?\n> +\tcbz\tx0, 1f\t\t\t\t// Skip SVE init if not\n> +\n> +\tmrs\tx0, cptr_el3\n> +\torr\tx0, x0, #CPTR_EL3_EZ\t\t// enable SVE\n> +\tmsr\tcptr_el3, x0\n> +\tisb\n> +\n> +\tmov\tx0, #ZCR_EL3_LEN_MASK\t\t// SVE: Enable full vector len\n> +\tmsr\tZCR_EL3, x0\t\t\t// for EL2.\n> +\n> +1:\n>  \tldr\tx0, =CNTFRQ\n>  \tmsr\tcntfrq_el0, x0\n>  \n> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h\n> index 66726ef..ccb5397 100644\n> --- a/arch/aarch64/include/asm/cpu.h\n> +++ b/arch/aarch64/include/asm/cpu.h\n> @@ -27,6 +27,11 @@\n>  #define SPSR_EL2H\t\t(9 << 0)\t/* EL2 Handler mode */\n>  #define SPSR_HYP\t\t(0x1a << 0)\t/* M[3:0] = hyp, M[4] = AArch32 */\n>  \n> +#define CPTR_EL3_EZ\t\t(1 << 8)\n> +\n> +#define ZCR_EL3\t\t\ts3_6_c1_c2_0\n> +#define ZCR_EL3_LEN_MASK\t0x1ff\n> +\n>  #define SCTLR_EL1_CP15BEN\t(1 << 5)\n>  #define SCTLR_EL1_RES1\t\t(3 << 28 | 3 << 22 | 1 << 11)\n>  \n> -- \n> 2.1.4\n>","headers":{"Return-Path":"<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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