[{"id":1776635,"web_url":"http://patchwork.ozlabs.org/comment/1776635/","msgid":"<20170927214429.2w7s3f7zpqr4kkvs@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-27T21:44:29","subject":"Re: [PATCH 1/4] dt-bindings: clock: mediatek: document clk bindings\n\tfor MediaTek MT7622 SoC","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, Sep 20, 2017 at 05:49:25PM +0800, sean.wang@mediatek.com wrote:\n> From: Sean Wang <sean.wang@mediatek.com>\n> \n> This patch adds the binding documentation for apmixedsys, ethsys, hifsys,\n> infracfg, pericfg, topckgen and audsys for MT7622.\n> \n> Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>\n> Signed-off-by: Sean Wang <sean.wang@mediatek.com>\n> ---\n>  .../bindings/arm/mediatek/mediatek,apmixedsys.txt  |  1 +\n>  .../bindings/arm/mediatek/mediatek,audsys.txt      | 22 ++++++++++++++++++++++\n>  .../bindings/arm/mediatek/mediatek,ethsys.txt      |  1 +\n>  .../bindings/arm/mediatek/mediatek,hifsys.txt      |  1 +\n>  .../bindings/arm/mediatek/mediatek,infracfg.txt    |  1 +\n>  .../bindings/arm/mediatek/mediatek,pciesys.txt     | 22 ++++++++++++++++++++++\n>  .../bindings/arm/mediatek/mediatek,pericfg.txt     |  1 +\n>  .../bindings/arm/mediatek/mediatek,sgmiisys.txt    | 22 ++++++++++++++++++++++\n>  .../bindings/arm/mediatek/mediatek,ssusbsys.txt    | 22 ++++++++++++++++++++++\n>  .../bindings/arm/mediatek/mediatek,topckgen.txt    |  1 +\n>  10 files changed, 94 insertions(+)\n>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt\n>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt\n>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt\n>  create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt\n\nAcked-by: Rob Herring <robh@kernel.org>\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2WYt16F5z9t5l\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 07:44:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751982AbdI0Voc (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tWed, 27 Sep 2017 17:44:32 -0400","from mail-pf0-f194.google.com ([209.85.192.194]:37449 \"EHLO\n\tmail-pf0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751958AbdI0Vob (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Wed, 27 Sep 2017 17:44:31 -0400","by mail-pf0-f194.google.com with SMTP id e69so7766045pfg.4;\n\tWed, 27 Sep 2017 14:44:31 -0700 (PDT)","from localhost ([70.35.39.2]) by smtp.gmail.com with ESMTPSA id\n\td69sm21476347pfl.50.2017.09.27.14.44.29\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 27 Sep 2017 14:44:30 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=IGfpFhGf9PlOhvBxPO8AF3mSyOREz6cgPmD0nCqRRzg=;\n\tb=HohmSF/yrIPVeJWi38X9DtOI9lUEbF50L9+IIbFlY9vIiyeW9J4McEKCxXaiCQykXD\n\tXRKopfOVfr9nGsCiHOMh2H/4MaKMCb23l1PKljXxr9imI9olSky2Z7OklTJ1FeVLKG/F\n\t99iHd83Rbj8L1bZPFAcmMlcqpEHJg2p++7ekNdolxg3M6BG1/dOLNC0SqIkh23fh7bRo\n\t1npj3PurOFXxnqbCAoq5BB5GHfUZOk0g7eIohNgoSuU33GSuxZTIlunHalU1nhsGFbIA\n\tjqoX64BbOPpcutIMSm4FWQ06+1VEzgNA9bavPRCAizwdjbNRgXWOrumnlzm1Dd5SP30y\n\twz0w==","X-Gm-Message-State":"AHPjjUgMcrjSYCCLfg1QQ3wqH21Dvz9jitER3hZrxUcNY50vlyIgQIG0\n\tL5CIHKeKR1oFpU17CIVMJXhnzv4=","X-Google-Smtp-Source":"AOwi7QB4JONxS2p/DHPJ0r6seH+rPd6eOXO6o1PXtCfxSRnSh4JJi6C2ol1jbHutESzNky/bJVnE2g==","X-Received":"by 10.99.124.87 with SMTP id l23mr2389440pgn.351.1506548671099; \n\tWed, 27 Sep 2017 14:44:31 -0700 (PDT)","Date":"Wed, 27 Sep 2017 16:44:29 -0500","From":"Rob Herring <robh@kernel.org>","To":"sean.wang@mediatek.com","Cc":"sboyd@codeaurora.org, mturquette@baylibre.com,\n\tmatthias.bgg@gmail.com, mark.rutland@arm.com,\n\tp.zabel@pengutronix.de, devicetree@vger.kernel.org,\n\tlinux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tChen Zhong <chen.zhong@mediatek.com>","Subject":"Re: [PATCH 1/4] dt-bindings: clock: mediatek: document clk bindings\n\tfor MediaTek MT7622 SoC","Message-ID":"<20170927214429.2w7s3f7zpqr4kkvs@rob-hp-laptop>","References":"<cover.1505890481.git.sean.wang@mediatek.com>\n\t<3a6338ca5f1513b897cac2facc7c0bf796b8c64f.1505890481.git.sean.wang@mediatek.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<3a6338ca5f1513b897cac2facc7c0bf796b8c64f.1505890481.git.sean.wang@mediatek.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"}}]