[{"id":1771775,"web_url":"http://patchwork.ozlabs.org/comment/1771775/","msgid":"","list_archive_url":null,"date":"2017-09-20T11:52:19","subject":"Re: [U-Boot] [U-Boot, v3,\n\t04/14] rockchip: clk: Add SARADC clock support for rk3288","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n> SARADC integer divider control register is 8-bits width.\n> \n> Signed-off-by: David Wu \n> Reviewed-by: Philipp Tomsich \n> Acked-by: Philipp Tomsich \n> ---\n> \n> Changes in v3: None\n> Changes in v2:\n> - Use bitfield_extract\n> - Use GENMASK\n> \n> drivers/clk/rockchip/clk_rk3288.c | 41 +++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 41 insertions(+)\n> \n\nApplied to u-boot-rockchip, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxyn413lMz9sPt\n\tfor ;\n\tWed, 20 Sep 2017 21:53:26 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 31FC5C21EF4; Wed, 20 Sep 2017 11:52:47 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9DB03C21DE4;\n\tWed, 20 Sep 2017 11:52:28 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid CB568C21CB3; Wed, 20 Sep 2017 11:52:25 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 84AB8C21D55\n\tfor ; Wed, 20 Sep 2017 11:52:25 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:52547\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dudYB-0006vn-QE; Wed, 20 Sep 2017 13:52:19 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"David Wu ","In-Reply-To":"<1505888909-98816-5-git-send-email-david.wu@rock-chips.com>","References":"<1505888909-98816-5-git-send-email-david.wu@rock-chips.com>","Message-Id":"","Date":"Wed, 20 Sep 2017 13:52:19 +0200","Cc":"huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tdavid.wu@rock-chips.com, andy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot, v3,\n\t04/14] rockchip: clk: Add SARADC clock support for rk3288","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]