[{"id":1776631,"web_url":"http://patchwork.ozlabs.org/comment/1776631/","msgid":"<20170927214213.qjz7qalvvmhpxxmy@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-27T21:42:13","subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Tue, Sep 19, 2017 at 03:40:00PM -0700, Brendan Higgins wrote:\n> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n> specific device tree for the NPCM750 (Poleg) evaluation board.\n> \n> Signed-off-by: Brendan Higgins \n> Reviewed-by: Tomer Maimon \n> Reviewed-by: Avi Fishman \n> Reviewed-by: Joel Stanley \n> Tested-by: Tomer Maimon \n> Tested-by: Avi Fishman \n> ---\n> .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 ++++\n> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 48 +++++\n> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 211 +++++++++++++++++++++\n> include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 ++++\n> 5 files changed, 346 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> \n> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> new file mode 100644\n> index 000000000000..e81f85b400cf\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> @@ -0,0 +1,42 @@\n> +=========================================================\n> +Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n> +=========================================================\n> +\n> +To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n> +defined in the \"cpus\" node.\n> +\n> +Enable method name:\t\"nuvoton,npcm7xx-smp\"\n> +Compatible machines:\t\"nuvoton,npcm750\"\n> +Compatible CPUs:\t\"arm,cortex-a9\"\n> +Related properties:\t(none)\n> +\n> +Note:\n> +This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n> +\"nuvoton,npcm750-gcr\".\n> +\n> +Example:\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> +\t\tcpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <0>;\n> +\t\t\tnext-level-cache = <&L2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <1>;\n> +\t\t\tnext-level-cache = <&L2>;\n> +\t\t};\n> +\t};\n> +\n> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> new file mode 100644\n> index 000000000000..2d87d9ecea85\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> @@ -0,0 +1,6 @@\n> +NPCM Platforms Device Tree Bindings\n> +-----------------------------------\n> +NPCM750 SoC\n> +Required root node properties:\n> +\t- compatible = \"nuvoton,npcm750\";\n> +\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> new file mode 100644\n> index 000000000000..a0675e584125\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> @@ -0,0 +1,48 @@\n> +/*\n> + * DTS file for all NPCM750 SoCs\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +/dts-v1/;\n> +#include \"nuvoton-npcm750.dtsi\"\n> +\n> +/ {\n> +\tmodel = \"Nuvoton npcm750 Development Board (Device Tree)\";\n> +\tcompatible = \"nuvoton,npcm750\";\n> +\n> +\tchosen {\n> +\t\tstdout-path = &serial3;\n> +\t};\n> +\n> +\tmemory {\n> +\t\treg = <0 0x40000000>;\n> +\t};\n> +};\n> +\n> +&watchdog1 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial0 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial1 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial2 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial3 {\n> +\tstatus = \"okay\";\n> +};\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> new file mode 100644\n> index 000000000000..5d8a48e44274\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> @@ -0,0 +1,211 @@\n> +/*\n> + * DTSi file for the NPCM750 SoC\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +#include \n> +#include \n> +\n> +/ {\n> +\t#address-cells = <1>;\n> +\t#size-cells = <1>;\n> +\tinterrupt-parent = <&gic>;\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> +\t\tcpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <0>;\n> +\t\t\tnext-level-cache = <&l2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <1>;\n> +\t\t\tnext-level-cache = <&l2>;\n> +\t\t};\n> +\t};\n> +\n\n> +\tgcr: gcr@f0800000 {\n> +\t\tcompatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n> +\t\t\t\"simple-mfd\";\n> +\t\treg = <0xf0800000 0x1000>;\n> +\t};\n> +\n> +\tscu: scu@f03fe000 {\n> +\t\tcompatible = \"arm,cortex-a9-scu\";\n> +\t\treg = <0xf03fe000 0x1000>;\n> +\t};\n> +\n> +\tl2: cache-controller@f03fc000 {\n> +\t\tcompatible = \"arm,pl310-cache\";\n> +\t\treg = <0xf03fc000 0x1000>;\n> +\t\tinterrupts = <0 21 4>;\n> +\t\tcache-unified;\n> +\t\tcache-level = <2>;\n> +\t\tclocks = <&clk NPCM7XX_CLK_AXI>;\n> +\t};\n> +\n> +\tgic: interrupt-controller@f03ff000 {\n> +\t\tcompatible = \"arm,cortex-a9-gic\";\n> +\t\tinterrupt-controller;\n> +\t\t#interrupt-cells = <3>;\n> +\t\treg = <0xf03ff000 0x1000>,\n> +\t\t <0xf03fe100 0x100>;\n> +\t};\n> +\n> +\ttimer@f03fe600 {\n> +\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n> +\t\treg = <0xf03fe600 0x20>;\n> +\t\tinterrupts = <1 13 0x304>;\n> +\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t};\n\nAll these nodes with a memory mapped address should go under a bus node.\n\n> +\n> +\tahb {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <1>;\n> +\t\tcompatible = \"simple-bus\";\n> +\t\tinterrupt-parent = <&gic>;\n> +\t\tranges = <0x80000000 0x80000000 0x40000000\n> +\t\t\t 0xc0000000 0xc0000000 0x00002000\n> +\t\t\t 0xc0008000 0xc0008000 0x00001000\n> +\t\t\t 0xe0800000 0xe0800000 0x00001000\n> +\t\t\t 0xe1000000 0xe1000000 0x00001000\n> +\t\t\t 0xe8000000 0xe8000000 0x08000000\n\nThese addresses don't appear to be used. These are coming later? They \ncould be collapsed down into 2 entries.\n\n<0x80000000 0x80000000 0x40010000>\n<0xe0800000 0xe0800000 0x0f800000>\n\n> +\t\t\t /* APB start */\n> +\t\t\t 0xf0000000 0xf0000000 0x00005000\n> +\t\t\t 0xf0007000 0xf0007000 0x00005000\n> +\t\t\t 0xf0010000 0xf0010000 0x00008000\n> +\t\t\t 0xf0080000 0xf0080000 0x00010000\n> +\t\t\t 0xf009f000 0xf009f000 0x00001000\n> +\t\t\t 0xf0100000 0xf0100000 0x00005000\n> +\t\t\t 0xf0180000 0xf0180000 0x0000b000\n> +\t\t\t 0xf0200000 0xf0200000 0x00002000\n\nNot necessary to be so fine grained and shouldn't just be 1:1. So \nfor these just:\n\n<0 0xf0000000 0x00900000>\n\n\n> +\t\t\t /* APB end */\n> +\t\t\t 0xf0800000 0xf0800000 0x000fc000\n> +\t\t\t 0xf8000000 0xf8000000 0x02000000\n> +\t\t\t 0xfb000000 0xfb000000 0x00002000>;\n\n> +\n> +\t\tclk: clock-controller@f0801000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-clk\";\n> +\t\t\t#clock-cells = <1>;\n> +\t\t\treg = <0xf0801000 0x1000>;\n\nThen this becomes: 0x801000 0x1000\n\n> +\t\t\tstatus = \"okay\";\n> +\t\t};\n> +\n> +\t\t/* external clock signal rg1refck, supplied by the phy */\n> +\t\tclk-rg1refck {\n> +\t\t\tcompatible = \"fixed-clock\";\n> +\t\t\t#clock-cells = <0>;\n> +\t\t\tclock-frequency = <125000000>;\n> +\t\t};\n> +\n> +\t\t/* external clock signal rg2refck, supplied by the phy */\n> +\t\tclk-rg2refck {\n> +\t\t\tcompatible = \"fixed-clock\";\n> +\t\t\t#clock-cells = <0>;\n> +\t\t\tclock-frequency = <125000000>;\n> +\t\t};\n> +\n> +\t\tclk-xin {\n> +\t\t\tcompatible = \"fixed-clock\";\n> +\t\t\t#clock-cells = <0>;\n> +\t\t\tclock-frequency = <50000000>;\n> +\t\t};\n\nThese clocks are not on the bus, so move them out of the bus node to the \ntop level.\n\n> +\n> +\t\tapb {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <1>;\n> +\t\t\tcompatible = \"simple-bus\";\n> +\t\t\tinterrupt-parent = <&gic>;\n> +\t\t\tranges = <0xf0000000 0xf0000000 0x00005000\n> +\t\t\t\t 0xf0007000 0xf0007000 0x00005000\n> +\t\t\t\t 0xf0010000 0xf0010000 0x00008000\n> +\t\t\t\t 0xf0080000 0xf0080000 0x00010000\n> +\t\t\t\t 0xf009f000 0xf009f000 0x00001000\n> +\t\t\t\t 0xf0100000 0xf0100000 0x00005000\n> +\t\t\t\t 0xf0180000 0xf0180000 0x0000b000\n> +\t\t\t\t 0xf0200000 0xf0200000 0x00002000>;\n\nWith above changes this can be just: <0 0 0x300000>\n\n> +\n> +\t\t\ttimer0: timer@f0000000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-timer\";\n> +\t\t\t\tinterrupts = <0 32 4>;\n> +\t\t\t\treg = <0xf0000000 0x1000>;\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t\t};\n> +\n> +\t\t\twatchdog0: watchdog@f0008000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\t\tinterrupts = <0 47 4>;\n> +\t\t\t\treg = <0xf0008000 0x1000>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t\t};\n> +\n> +\t\t\twatchdog1: watchdog@f0009000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\t\tinterrupts = <0 48 4>;\n> +\t\t\t\treg = <0xf0009000 0x1000>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t\t};\n> +\n> +\t\t\twatchdog2: watchdog@f000a000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\t\tinterrupts = <0 49 4>;\n> +\t\t\t\treg = <0xf000a000 0x1000>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t\t};\n> +\n> +\t\t\tserial0: serial0@f0001000 {\n\nSorry I miss this earlier, but need to drop the 0 in the node names. \nIOW, should be \"serial@f0001000\".\n\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\t\treg = <0xf0001000 0x1000>;\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\t\tinterrupts = <0 2 4>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t};\n> +\n> +\t\t\tserial1: serial1@f0002000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\t\treg = <0xf0002000 0x1000>;\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\t\tinterrupts = <0 3 4>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t};\n> +\n> +\t\t\tserial2: serial2@f0003000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\t\treg = <0xf0003000 0x1000>;\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\t\tinterrupts = <0 4 4>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t};\n> +\n> +\t\t\tserial3: serial3@f0004000 {\n> +\t\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\t\treg = <0xf0004000 0x1000>;\n> +\t\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\t\tinterrupts = <0 5 4>;\n> +\t\t\t\tstatus = \"disabled\";\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +};","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2WWR2ZZVz9t67\n\tfor ;\n\tThu, 28 Sep 2017 07:42:27 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3y2WWR1Tn5zDsPt\n\tfor ;\n\tThu, 28 Sep 2017 07:42:27 +1000 (AEST)","from mail-pf0-f195.google.com (mail-pf0-f195.google.com\n\t[209.85.192.195])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3y2WWG19kQzDsPT\n\tfor ; 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\n\tWed, 27 Sep 2017 14:42:15 -0700 (PDT)","Date":"Wed, 27 Sep 2017 16:42:13 -0500","From":"Rob Herring ","To":"Brendan Higgins ","Subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","Message-ID":"<20170927214213.qjz7qalvvmhpxxmy@rob-hp-laptop>","References":"<20170919224001.22284-1-brendanhiggins@google.com>\n\t<20170919224001.22284-3-brendanhiggins@google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170919224001.22284-3-brendanhiggins@google.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\ttmaimon77@gmail.com, avifishman70@gmail.com, openbmc@lists.ozlabs.org,\n\tlinux@armlinux.org.uk, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1790850,"web_url":"http://patchwork.ozlabs.org/comment/1790850/","msgid":"","list_archive_url":null,"date":"2017-10-19T19:04:36","subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":69647,"url":"http://patchwork.ozlabs.org/api/people/69647/","name":"Brendan Higgins","email":"brendanhiggins@google.com"},"content":"Sorry for the delay. A couple questions:\n\nOn Wed, Sep 27, 2017 at 2:42 PM, Rob Herring wrote:\n> On Tue, Sep 19, 2017 at 03:40:00PM -0700, Brendan Higgins wrote:\n>> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n>> specific device tree for the NPCM750 (Poleg) evaluation board.\n>>\n>> Signed-off-by: Brendan Higgins \n>> Reviewed-by: Tomer Maimon \n>> Reviewed-by: Avi Fishman \n>> Reviewed-by: Joel Stanley \n>> Tested-by: Tomer Maimon \n>> Tested-by: Avi Fishman \n>> ---\n>> .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 ++++\n>> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n>> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 48 +++++\n>> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 211 +++++++++++++++++++++\n>> include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 ++++\n>> 5 files changed, 346 insertions(+)\n>> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n>> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n>> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n>> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n>> create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n>>\n>> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n>> new file mode 100644\n>> index 000000000000..e81f85b400cf\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n>> @@ -0,0 +1,42 @@\n>> +=========================================================\n>> +Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n>> +=========================================================\n>> +\n>> +To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n>> +defined in the \"cpus\" node.\n>> +\n>> +Enable method name: \"nuvoton,npcm7xx-smp\"\n>> +Compatible machines: \"nuvoton,npcm750\"\n>> +Compatible CPUs: \"arm,cortex-a9\"\n>> +Related properties: (none)\n>> +\n>> +Note:\n>> +This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n>> +\"nuvoton,npcm750-gcr\".\n>> +\n>> +Example:\n>> +\n>> + cpus {\n>> + #address-cells = <1>;\n>> + #size-cells = <0>;\n>> + enable-method = \"nuvoton,npcm7xx-smp\";\n>> +\n>> + cpu@0 {\n>> + device_type = \"cpu\";\n>> + compatible = \"arm,cortex-a9\";\n>> + clocks = <&clk NPCM7XX_CLK_CPU>;\n>> + clock-names = \"clk_cpu\";\n>> + reg = <0>;\n>> + next-level-cache = <&L2>;\n>> + };\n>> +\n>> + cpu@1 {\n>> + device_type = \"cpu\";\n>> + compatible = \"arm,cortex-a9\";\n>> + clocks = <&clk NPCM7XX_CLK_CPU>;\n>> + clock-names = \"clk_cpu\";\n>> + reg = <1>;\n>> + next-level-cache = <&L2>;\n>> + };\n>> + };\n>> +\n>> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n>> new file mode 100644\n>> index 000000000000..2d87d9ecea85\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n>> @@ -0,0 +1,6 @@\n>> +NPCM Platforms Device Tree Bindings\n>> +-----------------------------------\n>> +NPCM750 SoC\n>> +Required root node properties:\n>> + - compatible = \"nuvoton,npcm750\";\n>> +\n>> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n>> new file mode 100644\n>> index 000000000000..a0675e584125\n>> --- /dev/null\n>> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n>> @@ -0,0 +1,48 @@\n>> +/*\n>> + * DTS file for all NPCM750 SoCs\n>> + *\n>> + * Copyright 2012 Tomer Maimon \n>> + *\n>> + * The code contained herein is licensed under the GNU General Public\n>> + * License. You may obtain a copy of the GNU General Public License\n>> + * Version 2 or later at the following locations:\n>> + *\n>> + * http://www.opensource.org/licenses/gpl-license.html\n>> + * http://www.gnu.org/copyleft/gpl.html\n>> + */\n>> +\n>> +/dts-v1/;\n>> +#include \"nuvoton-npcm750.dtsi\"\n>> +\n>> +/ {\n>> + model = \"Nuvoton npcm750 Development Board (Device Tree)\";\n>> + compatible = \"nuvoton,npcm750\";\n>> +\n>> + chosen {\n>> + stdout-path = &serial3;\n>> + };\n>> +\n>> + memory {\n>> + reg = <0 0x40000000>;\n>> + };\n>> +};\n>> +\n>> +&watchdog1 {\n>> + status = \"okay\";\n>> +};\n>> +\n>> +&serial0 {\n>> + status = \"okay\";\n>> +};\n>> +\n>> +&serial1 {\n>> + status = \"okay\";\n>> +};\n>> +\n>> +&serial2 {\n>> + status = \"okay\";\n>> +};\n>> +\n>> +&serial3 {\n>> + status = \"okay\";\n>> +};\n>> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n>> new file mode 100644\n>> index 000000000000..5d8a48e44274\n>> --- /dev/null\n>> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n>> @@ -0,0 +1,211 @@\n>> +/*\n>> + * DTSi file for the NPCM750 SoC\n>> + *\n>> + * Copyright 2012 Tomer Maimon \n>> + *\n>> + * The code contained herein is licensed under the GNU General Public\n>> + * License. You may obtain a copy of the GNU General Public License\n>> + * Version 2 or later at the following locations:\n>> + *\n>> + * http://www.opensource.org/licenses/gpl-license.html\n>> + * http://www.gnu.org/copyleft/gpl.html\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +\n>> +/ {\n>> + #address-cells = <1>;\n>> + #size-cells = <1>;\n>> + interrupt-parent = <&gic>;\n>> +\n>> + cpus {\n>> + #address-cells = <1>;\n>> + #size-cells = <0>;\n>> + enable-method = \"nuvoton,npcm7xx-smp\";\n>> +\n>> + cpu@0 {\n>> + device_type = \"cpu\";\n>> + compatible = \"arm,cortex-a9\";\n>> + clocks = <&clk NPCM7XX_CLK_CPU>;\n>> + clock-names = \"clk_cpu\";\n>> + reg = <0>;\n>> + next-level-cache = <&l2>;\n>> + };\n>> +\n>> + cpu@1 {\n>> + device_type = \"cpu\";\n>> + compatible = \"arm,cortex-a9\";\n>> + clocks = <&clk NPCM7XX_CLK_CPU>;\n>> + clock-names = \"clk_cpu\";\n>> + reg = <1>;\n>> + next-level-cache = <&l2>;\n>> + };\n>> + };\n>> +\n>\n>> + gcr: gcr@f0800000 {\n>> + compatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n>> + \"simple-mfd\";\n>> + reg = <0xf0800000 0x1000>;\n>> + };\n>> +\n>> + scu: scu@f03fe000 {\n>> + compatible = \"arm,cortex-a9-scu\";\n>> + reg = <0xf03fe000 0x1000>;\n>> + };\n>> +\n>> + l2: cache-controller@f03fc000 {\n>> + compatible = \"arm,pl310-cache\";\n>> + reg = <0xf03fc000 0x1000>;\n>> + interrupts = <0 21 4>;\n>> + cache-unified;\n>> + cache-level = <2>;\n>> + clocks = <&clk NPCM7XX_CLK_AXI>;\n>> + };\n>> +\n>> + gic: interrupt-controller@f03ff000 {\n>> + compatible = \"arm,cortex-a9-gic\";\n>> + interrupt-controller;\n>> + #interrupt-cells = <3>;\n>> + reg = <0xf03ff000 0x1000>,\n>> + <0xf03fe100 0x100>;\n>> + };\n>> +\n>> + timer@f03fe600 {\n>> + compatible = \"arm,cortex-a9-twd-timer\";\n>> + reg = <0xf03fe600 0x20>;\n>> + interrupts = <1 13 0x304>;\n>> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n>> + };\n>\n> All these nodes with a memory mapped address should go under a bus node.\n>\n>> +\n>> + ahb {\n>> + #address-cells = <1>;\n>> + #size-cells = <1>;\n>> + compatible = \"simple-bus\";\n>> + interrupt-parent = <&gic>;\n>> + ranges = <0x80000000 0x80000000 0x40000000\n>> + 0xc0000000 0xc0000000 0x00002000\n>> + 0xc0008000 0xc0008000 0x00001000\n>> + 0xe0800000 0xe0800000 0x00001000\n>> + 0xe1000000 0xe1000000 0x00001000\n>> + 0xe8000000 0xe8000000 0x08000000\n>\n> These addresses don't appear to be used. These are coming later? They\n> could be collapsed down into 2 entries.\n\nYep, the other addresses will be used in later patch sets. This is part of why I\ndid not think that it made sense to do address translation here. I thought that\nmapping such a large range of addresses would not make it any easier to read,\nquite the opposite. At least addresses 'mapped' to the original address\ncorrespond to the datasheet. So I am guessing that is not what you are asking\nme to do.\n\nMost of the large mappings (on the orders of MB) correspond to memory\nlocations mapped on either one of the SPI busses or PCIe busses, which when\nimplemented would likely get their own busses under ahb.\n\nAre you asking that I remap just the addresses for controlling SoC devices\n(0xf0xxxxxx), leave the external busses as is, and then remap those within their\nbusses when we get to that point?\n\nI will try to implement what I think you are asking me to do and get a patch out\nlater today. Hopefully that will make this discussion easier.\n\n>\n> <0x80000000 0x80000000 0x40010000>\n> <0xe0800000 0xe0800000 0x0f800000>\n>\n>> + /* APB start */\n>> + 0xf0000000 0xf0000000 0x00005000\n>> + 0xf0007000 0xf0007000 0x00005000\n>> + 0xf0010000 0xf0010000 0x00008000\n>> + 0xf0080000 0xf0080000 0x00010000\n>> + 0xf009f000 0xf009f000 0x00001000\n>> + 0xf0100000 0xf0100000 0x00005000\n>> + 0xf0180000 0xf0180000 0x0000b000\n>> + 0xf0200000 0xf0200000 0x00002000\n>\n> Not necessary to be so fine grained and shouldn't just be 1:1. So\n> for these just:\n>\n> <0 0xf0000000 0x00900000>\n>\n>\n>> + /* APB end */\n>> + 0xf0800000 0xf0800000 0x000fc000\n>> + 0xf8000000 0xf8000000 0x02000000\n>> + 0xfb000000 0xfb000000 0x00002000>;\n>\n>> +\n>> + clk: clock-controller@f0801000 {\n>> + compatible = \"nuvoton,npcm750-clk\";\n>> + #clock-cells = <1>;\n>> + reg = <0xf0801000 0x1000>;\n>\n> Then this becomes: 0x801000 0x1000\n>\n>> + status = \"okay\";\n>> + };\n>> +\n>> + /* external clock signal rg1refck, supplied by the phy */\n>> + clk-rg1refck {\n>> + compatible = \"fixed-clock\";\n>> + #clock-cells = <0>;\n>> + clock-frequency = <125000000>;\n>> + };\n>> +\n>> + /* external clock signal rg2refck, supplied by the phy */\n>> + clk-rg2refck {\n>> + compatible = \"fixed-clock\";\n>> + #clock-cells = <0>;\n>> + clock-frequency = <125000000>;\n>> + };\n>> +\n>> + clk-xin {\n>> + compatible = \"fixed-clock\";\n>> + #clock-cells = <0>;\n>> + clock-frequency = <50000000>;\n>> + };\n>\n> These clocks are not on the bus, so move them out of the bus node to the\n> top level.\n>\n>> +\n>> + apb {\n>> + #address-cells = <1>;\n>> + #size-cells = <1>;\n>> + compatible = \"simple-bus\";\n>> + interrupt-parent = <&gic>;\n>> + ranges = <0xf0000000 0xf0000000 0x00005000\n>> + 0xf0007000 0xf0007000 0x00005000\n>> + 0xf0010000 0xf0010000 0x00008000\n>> + 0xf0080000 0xf0080000 0x00010000\n>> + 0xf009f000 0xf009f000 0x00001000\n>> + 0xf0100000 0xf0100000 0x00005000\n>> + 0xf0180000 0xf0180000 0x0000b000\n>> + 0xf0200000 0xf0200000 0x00002000>;\n>\n> With above changes this can be just: <0 0 0x300000>\n>\n>> +\n>> + timer0: timer@f0000000 {\n>> + compatible = \"nuvoton,npcm750-timer\";\n>> + interrupts = <0 32 4>;\n>> + reg = <0xf0000000 0x1000>;\n>> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n>> + };\n>> +\n>> + watchdog0: watchdog@f0008000 {\n>> + compatible = \"nuvoton,npcm750-wdt\";\n>> + interrupts = <0 47 4>;\n>> + reg = <0xf0008000 0x1000>;\n>> + status = \"disabled\";\n>> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n>> + };\n>> +\n>> + watchdog1: watchdog@f0009000 {\n>> + compatible = \"nuvoton,npcm750-wdt\";\n>> + interrupts = <0 48 4>;\n>> + reg = <0xf0009000 0x1000>;\n>> + status = \"disabled\";\n>> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n>> + };\n>> +\n>> + watchdog2: watchdog@f000a000 {\n>> + compatible = \"nuvoton,npcm750-wdt\";\n>> + interrupts = <0 49 4>;\n>> + reg = <0xf000a000 0x1000>;\n>> + status = \"disabled\";\n>> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n>> + };\n>> +\n>> + serial0: serial0@f0001000 {\n>\n> Sorry I miss this earlier, but need to drop the 0 in the node names.\n> IOW, should be \"serial@f0001000\".\n>\n>> + compatible = \"nuvoton,npcm750-uart\";\n>> + reg = <0xf0001000 0x1000>;\n>> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n>> + interrupts = <0 2 4>;\n>> + status = \"disabled\";\n>> + };\n>> +\n>> + serial1: serial1@f0002000 {\n>> + compatible = \"nuvoton,npcm750-uart\";\n>> + reg = <0xf0002000 0x1000>;\n>> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n>> + interrupts = <0 3 4>;\n>> + status = \"disabled\";\n>> + };\n>> +\n>> + serial2: serial2@f0003000 {\n>> + compatible = \"nuvoton,npcm750-uart\";\n>> + reg = <0xf0003000 0x1000>;\n>> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n>> + interrupts = <0 4 4>;\n>> + status = \"disabled\";\n>> + };\n>> +\n>> + serial3: serial3@f0004000 {\n>> + compatible = \"nuvoton,npcm750-uart\";\n>> + reg = <0xf0004000 0x1000>;\n>> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n>> + interrupts = <0 5 4>;\n>> + status = \"disabled\";\n>> + };\n>> + };\n>> + };\n>> +};\n\nThanks!","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yHyzX6vcpz9t5R\n\tfor ;\n\tFri, 20 Oct 2017 06:04:56 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yHyzX3b7SzDqRM\n\tfor ;\n\tFri, 20 Oct 2017 06:04:56 +1100 (AEDT)","from mail-qt0-x241.google.com (mail-qt0-x241.google.com\n\t[IPv6:2607:f8b0:400d:c0d::241])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yHyzF2ZzQzDqBr\n\tfor ; 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charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland ,\n\tdevicetree ,\n\tFlorian Fainelli , tmaimon77@gmail.com,\n\tAvi Fishman ,\n\tOpenBMC Maillist ,\n\tRussell King ,\n\tLinux Kernel Mailing List ,\n\tlinux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1795531,"web_url":"http://patchwork.ozlabs.org/comment/1795531/","msgid":"","list_archive_url":null,"date":"2017-10-29T20:33:40","subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":72291,"url":"http://patchwork.ozlabs.org/api/people/72291/","name":"Tomer Maimon","email":"tmaimon77@gmail.com"},"content":"On 20 September 2017 at 00:40, Brendan Higgins\n wrote:\n> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n> specific device tree for the NPCM750 (Poleg) evaluation board.\n>\n> Signed-off-by: Brendan Higgins \n> Reviewed-by: Tomer Maimon \n> Reviewed-by: Avi Fishman \n> Reviewed-by: Joel Stanley \n> Tested-by: Tomer Maimon \n> Tested-by: Avi Fishman \n> ---\n> .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 ++++\n> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 48 +++++\n> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 211 +++++++++++++++++++++\n> include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 ++++\n> 5 files changed, 346 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n>\n> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> new file mode 100644\n> index 000000000000..e81f85b400cf\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> @@ -0,0 +1,42 @@\n> +=========================================================\n> +Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n> +=========================================================\n> +\n> +To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n> +defined in the \"cpus\" node.\n> +\n> +Enable method name: \"nuvoton,npcm7xx-smp\"\n> +Compatible machines: \"nuvoton,npcm750\"\n> +Compatible CPUs: \"arm,cortex-a9\"\n> +Related properties: (none)\n> +\n> +Note:\n> +This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n> +\"nuvoton,npcm750-gcr\".\n> +\n> +Example:\n> +\n> + cpus {\n> + #address-cells = <1>;\n> + #size-cells = <0>;\n> + enable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> + cpu@0 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <0>;\n> + next-level-cache = <&L2>;\n> + };\n> +\n> + cpu@1 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <1>;\n> + next-level-cache = <&L2>;\n> + };\n> + };\n> +\n> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> new file mode 100644\n> index 000000000000..2d87d9ecea85\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> @@ -0,0 +1,6 @@\n> +NPCM Platforms Device Tree Bindings\n> +-----------------------------------\n> +NPCM750 SoC\n> +Required root node properties:\n> + - compatible = \"nuvoton,npcm750\";\n> +\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> new file mode 100644\n> index 000000000000..a0675e584125\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> @@ -0,0 +1,48 @@\n> +/*\n> + * DTS file for all NPCM750 SoCs\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +/dts-v1/;\n> +#include \"nuvoton-npcm750.dtsi\"\n> +\n> +/ {\n> + model = \"Nuvoton npcm750 Development Board (Device Tree)\";\n> + compatible = \"nuvoton,npcm750\";\n> +\n> + chosen {\n> + stdout-path = &serial3;\n> + };\n> +\n> + memory {\n> + reg = <0 0x40000000>;\n> + };\n> +};\n> +\n> +&watchdog1 {\n> + status = \"okay\";\n> +};\n> +\n> +&serial0 {\n> + status = \"okay\";\n> +};\n> +\n> +&serial1 {\n> + status = \"okay\";\n> +};\n> +\n> +&serial2 {\n> + status = \"okay\";\n> +};\n> +\n> +&serial3 {\n> + status = \"okay\";\n> +};\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> new file mode 100644\n> index 000000000000..5d8a48e44274\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> @@ -0,0 +1,211 @@\n> +/*\n> + * DTSi file for the NPCM750 SoC\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +#include \n> +#include \n> +\n> +/ {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + interrupt-parent = <&gic>;\n> +\n> + cpus {\n> + #address-cells = <1>;\n> + #size-cells = <0>;\n> + enable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> + cpu@0 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <0>;\n> + next-level-cache = <&l2>;\n> + };\n> +\n> + cpu@1 {\n> + device_type = \"cpu\";\n> + compatible = \"arm,cortex-a9\";\n> + clocks = <&clk NPCM7XX_CLK_CPU>;\n> + clock-names = \"clk_cpu\";\n> + reg = <1>;\n> + next-level-cache = <&l2>;\n> + };\n> + };\n> +\n> + gcr: gcr@f0800000 {\n> + compatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n> + \"simple-mfd\";\n> + reg = <0xf0800000 0x1000>;\n> + };\n> +\n> + scu: scu@f03fe000 {\n> + compatible = \"arm,cortex-a9-scu\";\n> + reg = <0xf03fe000 0x1000>;\n> + };\n> +\n> + l2: cache-controller@f03fc000 {\n> + compatible = \"arm,pl310-cache\";\n> + reg = <0xf03fc000 0x1000>;\n> + interrupts = <0 21 4>;\n> + cache-unified;\n> + cache-level = <2>;\n> + clocks = <&clk NPCM7XX_CLK_AXI>;\n> + };\n> +\n> + gic: interrupt-controller@f03ff000 {\n> + compatible = \"arm,cortex-a9-gic\";\n> + interrupt-controller;\n> + #interrupt-cells = <3>;\n> + reg = <0xf03ff000 0x1000>,\n> + <0xf03fe100 0x100>;\n> + };\n> +\n> + timer@f03fe600 {\n> + compatible = \"arm,cortex-a9-twd-timer\";\n> + reg = <0xf03fe600 0x20>;\n> + interrupts = <1 13 0x304>;\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + ahb {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + compatible = \"simple-bus\";\n> + interrupt-parent = <&gic>;\n> + ranges = <0x80000000 0x80000000 0x40000000\n> + 0xc0000000 0xc0000000 0x00002000\n> + 0xc0008000 0xc0008000 0x00001000\n> + 0xe0800000 0xe0800000 0x00001000\n> + 0xe1000000 0xe1000000 0x00001000\n> + 0xe8000000 0xe8000000 0x08000000\n> + /* APB start */\n> + 0xf0000000 0xf0000000 0x00005000\n> + 0xf0007000 0xf0007000 0x00005000\n> + 0xf0010000 0xf0010000 0x00008000\n> + 0xf0080000 0xf0080000 0x00010000\n> + 0xf009f000 0xf009f000 0x00001000\n> + 0xf0100000 0xf0100000 0x00005000\n> + 0xf0180000 0xf0180000 0x0000b000\n> + 0xf0200000 0xf0200000 0x00002000\n> + /* APB end */\n> + 0xf0800000 0xf0800000 0x000fc000\n> + 0xf8000000 0xf8000000 0x02000000\n> + 0xfb000000 0xfb000000 0x00002000>;\n> +\n> + clk: clock-controller@f0801000 {\n> + compatible = \"nuvoton,npcm750-clk\";\n> + #clock-cells = <1>;\n> + reg = <0xf0801000 0x1000>;\n> + status = \"okay\";\n> + };\n> +\n> + /* external clock signal rg1refck, supplied by the phy */\n> + clk-rg1refck {\n> + compatible = \"fixed-clock\";\n> + #clock-cells = <0>;\n> + clock-frequency = <125000000>;\n> + };\n> +\n> + /* external clock signal rg2refck, supplied by the phy */\n> + clk-rg2refck {\n> + compatible = \"fixed-clock\";\n> + #clock-cells = <0>;\n> + clock-frequency = <125000000>;\n> + };\n> +\n> + clk-xin {\n> + compatible = \"fixed-clock\";\n> + #clock-cells = <0>;\n> + clock-frequency = <50000000>;\n> + };\n> +\n> + apb {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + compatible = \"simple-bus\";\n> + interrupt-parent = <&gic>;\n> + ranges = <0xf0000000 0xf0000000 0x00005000\n> + 0xf0007000 0xf0007000 0x00005000\n> + 0xf0010000 0xf0010000 0x00008000\n> + 0xf0080000 0xf0080000 0x00010000\n> + 0xf009f000 0xf009f000 0x00001000\n> + 0xf0100000 0xf0100000 0x00005000\n> + 0xf0180000 0xf0180000 0x0000b000\n> + 0xf0200000 0xf0200000 0x00002000>;\n> +\n> + timer0: timer@f0000000 {\n> + compatible = \"nuvoton,npcm750-timer\";\n> + interrupts = <0 32 4>;\n> + reg = <0xf0000000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n\nI started the upstream process of NPCM7xx clocksource driver, I got\nthe following comment:\nhttps://www.spinics.net/lists/devicetree/msg197916.html\n\nIs it possible to modify the the timer DT entry to:\n\ntimer0: timer@f0008000 {\n compatible = \"nuvoton,npcm7xx-timer\";\n interrupts = <0 32 4>;\n reg = <0xf0008000 0x1000>;\n clocks = <&clk NPCM7XX_CLK_TIMER>;\n};\n\n> +\n> + watchdog0: watchdog@f0008000 {\n> + compatible = \"nuvoton,npcm750-wdt\";\n> + interrupts = <0 47 4>;\n> + reg = <0xf0008000 0x1000>;\n> + status = \"disabled\";\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + watchdog1: watchdog@f0009000 {\n> + compatible = \"nuvoton,npcm750-wdt\";\n> + interrupts = <0 48 4>;\n> + reg = <0xf0009000 0x1000>;\n> + status = \"disabled\";\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + watchdog2: watchdog@f000a000 {\n> + compatible = \"nuvoton,npcm750-wdt\";\n> + interrupts = <0 49 4>;\n> + reg = <0xf000a000 0x1000>;\n> + status = \"disabled\";\n> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n> + };\n> +\n> + serial0: serial0@f0001000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0001000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 2 4>;\n> + status = \"disabled\";\n> + };\n> +\n> + serial1: serial1@f0002000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0002000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 3 4>;\n> + status = \"disabled\";\n> + };\n> +\n> + serial2: serial2@f0003000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0003000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 4 4>;\n> + status = \"disabled\";\n> + };\n> +\n> + serial3: serial3@f0004000 {\n> + compatible = \"nuvoton,npcm750-uart\";\n> + reg = <0xf0004000 0x1000>;\n> + clocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> + interrupts = <0 5 4>;\n> + status = \"disabled\";\n> + };\n> + };\n> + };\n> +};\n> diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> new file mode 100644\n> index 000000000000..c69d3bbf7e42\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> @@ -0,0 +1,39 @@\n> +/*\n> + * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com\n> + *\n> + * This software is licensed under the terms of the GNU General Public\n> + * License version 2, as published by the Free Software Foundation, and\n> + * may be copied, distributed, and modified under those terms.\n> + */\n> +\n> +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H\n> +#define _DT_BINDINGS_CLK_NPCM7XX_H\n> +\n> +#define NPCM7XX_CLK_PLL0 0\n> +#define NPCM7XX_CLK_PLL1 1\n> +#define NPCM7XX_CLK_PLL2 2\n> +#define NPCM7XX_CLK_GFX 3\n> +#define NPCM7XX_CLK_APB1 4\n> +#define NPCM7XX_CLK_APB2 5\n> +#define NPCM7XX_CLK_APB3 6\n> +#define NPCM7XX_CLK_APB4 7\n> +#define NPCM7XX_CLK_APB5 8\n> +#define NPCM7XX_CLK_MC 9\n> +#define NPCM7XX_CLK_CPU 10\n> +#define NPCM7XX_CLK_SPI0 11\n> +#define NPCM7XX_CLK_SPI3 12\n> +#define NPCM7XX_CLK_SPIX 13\n> +#define NPCM7XX_CLK_UART_CORE 14\n> +#define NPCM7XX_CLK_TIMER 15\n> +#define NPCM7XX_CLK_HOST_UART 16\n> +#define NPCM7XX_CLK_MMC 17\n> +#define NPCM7XX_CLK_SDHC 18\n> +#define NPCM7XX_CLK_ADC 19\n> +#define NPCM7XX_CLK_GFX_MEM 20\n> +#define NPCM7XX_CLK_USB_BRIDGE 21\n> +#define NPCM7XX_CLK_AXI 22\n> +#define NPCM7XX_CLK_AHB 23\n> +#define NPCM7XX_CLK_EMC 24\n> +#define NPCM7XX_CLK_GMAC 25\n> +\n> +#endif\n> --\n> 2.14.1.690.gbb1197296e-goog\n>\n\nThanks!","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yQ8Tk1zCHz9t4c\n\tfor ;\n\tMon, 30 Oct 2017 07:34:02 +1100 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<20170919224001.22284-3-brendanhiggins@google.com>","References":"<20170919224001.22284-1-brendanhiggins@google.com>\n\t<20170919224001.22284-3-brendanhiggins@google.com>","From":"Tomer Maimon ","Date":"Sun, 29 Oct 2017 22:33:40 +0200","Message-ID":"","Subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","To":"Brendan Higgins ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland ,\n\tdevicetree ,\n\tFlorian Fainelli ,\n\tAvi Fishman , \n\tOpenBMC Maillist ,\n\tRussell King - ARM Linux ,\n\tLinux Kernel Mailing List ,\n\tRob Herring , linux-arm-kernel@lists.infradead.org","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}},{"id":1797580,"web_url":"http://patchwork.ozlabs.org/comment/1797580/","msgid":"","list_archive_url":null,"date":"2017-11-02T00:41:15","subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":67416,"url":"http://patchwork.ozlabs.org/api/people/67416/","name":"Rob Herring","email":"robh+dt@kernel.org"},"content":"On Sun, Oct 29, 2017 at 3:33 PM, Tomer Maimon wrote:\n> On 20 September 2017 at 00:40, Brendan Higgins\n> wrote:\n>> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n>> specific device tree for the NPCM750 (Poleg) evaluation board.\n>>\n\n>> + timer0: timer@f0000000 {\n>> + compatible = \"nuvoton,npcm750-timer\";\n>> + interrupts = <0 32 4>;\n>> + reg = <0xf0000000 0x1000>;\n>> + clocks = <&clk NPCM7XX_CLK_TIMER>;\n>> + };\n>\n> I started the upstream process of NPCM7xx clocksource driver, I got\n> the following comment:\n> https://www.spinics.net/lists/devicetree/msg197916.html\n>\n> Is it possible to modify the the timer DT entry to:\n>\n> timer0: timer@f0008000 {\n> compatible = \"nuvoton,npcm7xx-timer\";\n\nPlease don't. Using 750 is correct. Using 7xx (i.e. wildcards) is not.\n\nIf there's subsequent SoCs with the same block, then you can do:\n'\"nuvoton,npcm760-timer\", \"nuvoton,npcm750-timer\"'.\n\nRob","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","openbmc@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","openbmc@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yS5rR35Fxz9t2l\n\tfor ;\n\tThu, 2 Nov 2017 11:41:59 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yS5rR0pNlzDr5L\n\tfor ;\n\tThu, 2 Nov 2017 11:41:59 +1100 (AEDT)","from mail.kernel.org (mail.kernel.org [198.145.29.99])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yS5r36SYgzDr5J\n\tfor ; Thu, 2 Nov 2017 11:41:39 +1100 (AEDT)","from mail-qt0-f170.google.com (mail-qt0-f170.google.com\n\t[209.85.216.170])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 4E4DA2194A\n\tfor ; Thu, 2 Nov 2017 00:41:37 +0000 (UTC)","by mail-qt0-f170.google.com with SMTP id p1so4888048qtg.2\n\tfor ; Wed, 01 Nov 2017 17:41:37 -0700 (PDT)","by 10.12.130.134 with HTTP; Wed, 1 Nov 2017 17:41:15 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=kernel.org\n\t(client-ip=198.145.29.99; helo=mail.kernel.org;\n\tenvelope-from=robh+dt@kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh+dt@kernel.org"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 4E4DA2194A","X-Gm-Message-State":"AMCzsaXdKMg5d6YZCYC7VMsWKoBx3fJtaVOqUaYS2fipKi7QQlqFoGNl\n\tWiNSKMd7QIup911KQSgoMB0u5TvBVCh/D/oZLQ==","X-Google-Smtp-Source":"ABhQp+SsNjv1ypLO+Rv9+1A9Pnt/MyopcfVXit0J2Cw7EtwVO7SRkal/DlH0u0IReVSROTUB7tIZeHvN1xXhUvCKmc0=","X-Received":"by 10.200.8.239 with SMTP id y44mr2715082qth.341.1509583296458; \n\tWed, 01 Nov 2017 17:41:36 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<20170919224001.22284-1-brendanhiggins@google.com>\n\t<20170919224001.22284-3-brendanhiggins@google.com>\n\t","From":"Rob Herring ","Date":"Wed, 1 Nov 2017 19:41:15 -0500","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v6 2/3] arm: dts: add Nuvoton NPCM750 device tree","To":"Tomer Maimon ","Content-Type":"text/plain; charset=\"UTF-8\"","X-BeenThere":"openbmc@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Development list for OpenBMC ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland ,\n\tdevicetree ,\n\tFlorian Fainelli ,\n\tAvi Fishman , \n\tOpenBMC Maillist ,\n\tBrendan Higgins ,\n\tRussell King - ARM Linux ,\n\tLinux Kernel Mailing List ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t","Errors-To":"openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"openbmc\"\n\t"}}]