[{"id":1771565,"web_url":"http://patchwork.ozlabs.org/comment/1771565/","msgid":"","list_archive_url":null,"date":"2017-09-20T05:01:55","subject":"Re: [U-Boot] [PATCH v2 4/6] PCI: Add driver for a\n\t'pci-host-ecam-generic' host controller","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/people/64981/","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"content":"Hi Tuomas,\n\nOn Wed, Sep 20, 2017 at 4:18 AM, Tuomas Tynkkynen\n wrote:\n> QEMU emulates such a device with '-machine virt,highmem=off' on ARM.\n> The 'highmem=off' part is required for things to work as the PCI code\n> in U-Boot doesn't seem to support 64-bit BARs.\n>\n> Signed-off-by: Tuomas Tynkkynen \n> ---\n> v2:\n> - no 'default n'\n> - remove unnecessary non-DM struct field (inherited from the Xilinx driver)\n> - fix doc comment problems (inherited from the Xilinx driver)\n> - use the new generic memory mapped config space helpers\n> ---\n> drivers/pci/Kconfig | 8 +++\n> drivers/pci/Makefile | 1 +\n> drivers/pci/pcie_ecam_generic.c | 143 ++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 152 insertions(+)\n> create mode 100644 drivers/pci/pcie_ecam_generic.c\n>\n> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\n> index e2a1c0a409..648dff7543 100644\n> --- a/drivers/pci/Kconfig\n> +++ b/drivers/pci/Kconfig\n> @@ -33,6 +33,14 @@ config PCI_PNP\n> help\n> Enable PCI memory and I/O space resource allocation and assignment.\n>\n> +config PCIE_ECAM_GENERIC\n> + bool \"Generic ECAM-based PCI host controller support\"\n> + default n\n\nStill 'default n' here?\n\n> + depends on DM_PCI\n> + help\n> + Say Y here if you want to enable support for generic ECAM-based\n> + PCIe host controllers, such as the one emulated by QEMU.\n> +\n> config PCIE_DW_MVEBU\n> bool \"Enable Armada-8K PCIe driver (DesignWare core)\"\n> default n\n> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\n> index ad44e83996..5eb12efbf5 100644\n> --- a/drivers/pci/Makefile\n> +++ b/drivers/pci/Makefile\n> @@ -17,6 +17,7 @@ obj-$(CONFIG_PCI) += pci.o pci_auto_old.o\n> endif\n> obj-$(CONFIG_PCI) += pci_auto_common.o pci_common.o\n>\n> +obj-$(CONFIG_PCIE_ECAM_GENERIC) += pcie_ecam_generic.o\n> obj-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o\n> obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o\n> obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o\n> diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c\n> new file mode 100644\n> index 0000000000..2758f90de1\n> --- /dev/null\n> +++ b/drivers/pci/pcie_ecam_generic.c\n> @@ -0,0 +1,143 @@\n> +/*\n> + * Generic PCIE host provided by e.g. QEMU\n> + *\n> + * Heavily based on drivers/pci/pcie_xilinx.c\n> + *\n> + * Copyright (C) 2016 Imagination Technologies\n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +\n> +/**\n> + * struct generic_ecam_pcie - generic_ecam PCIe controller state\n> + * @cfg_base: The base address of memory mapped configuration space\n> + */\n> +struct generic_ecam_pcie {\n> + void *cfg_base;\n> +};\n> +\n> +/**\n> + * pci_generic_ecam_conf_address() - Calculate the address of a config access\n\nnits: please add one blank line here\n\n> + * @bus: Pointer to the PCI bus\n> + * @bdf: Identifies the PCIe device to access\n> + * @offset: The offset into the device's configuration space\n> + * @paddress: Pointer to the pointer to write the calculates address to\n> + *\n> + * Calculates the address that should be accessed to perform a PCIe\n> + * configuration space access for a given device identified by the PCIe\n> + * controller device @pcie and the bus, device & function numbers in @bdf. If\n> + * access to the device is not valid then the function will return an error\n> + * code. Otherwise the address to access will be written to the pointer pointed\n> + * to by @paddress.\n> + */\n> +static int pci_generic_ecam_conf_address(struct udevice *bus, pci_dev_t bdf,\n> + uint offset, void **paddress)\n> +{\n> + struct generic_ecam_pcie *pcie = dev_get_priv(bus);\n> + void *addr;\n> +\n> + addr = pcie->cfg_base;\n> + addr += PCI_BUS(bdf) << 20;\n> + addr += PCI_DEV(bdf) << 15;\n> + addr += PCI_FUNC(bdf) << 12;\n> + addr += offset;\n> + *paddress = addr;\n> +\n> + return 0;\n> +}\n> +\n> +/**\n> + * pci_generic_ecam_read_config() - Read from configuration space\n\nnits: please add one blank line here\n\n> + * @bus: Pointer to the PCI bus\n> + * @bdf: Identifies the PCIe device to access\n> + * @offset: The offset into the device's configuration space\n> + * @valuep: A pointer at which to store the read value\n> + * @size: Indicates the size of access to perform\n> + *\n> + * Read a value of size @size from offset @offset within the configuration\n> + * space of the device identified by the bus, device & function numbers in @bdf\n> + * on the PCI bus @bus.\n> + */\n> +static int pci_generic_ecam_read_config(struct udevice *bus, pci_dev_t bdf,\n> + uint offset, ulong *valuep,\n> + enum pci_size_t size)\n> +{\n> + return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address,\n> + bdf, offset, valuep, size);\n> +}\n> +\n> +/**\n> + * pci_generic_ecam_write_config() - Write to configuration space\n\nnits: please add one blank line here\n\n> + * @bus: Pointer to the PCI bus\n> + * @bdf: Identifies the PCIe device to access\n> + * @offset: The offset into the device's configuration space\n> + * @value: The value to write\n> + * @size: Indicates the size of access to perform\n> + *\n> + * Write the value @value of size @size from offset @offset within the\n> + * configuration space of the device identified by the bus, device & function\n> + * numbers in @bdf on the PCI bus @bus.\n> + */\n> +static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf,\n> + uint offset, ulong value,\n> + enum pci_size_t size)\n> +{\n> + return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address,\n> + bdf, offset, value, size);\n> +}\n> +\n> +/**\n> + * pci_generic_ecam_ofdata_to_platdata() - Translate from DT to device state\n\nnits: please add one blank line here\n\n> + * @dev: A pointer to the device being operated on\n> + *\n> + * Translate relevant data from the device tree pertaining to device @dev into\n> + * state that the driver will later make use of. This state is stored in the\n> + * device's private data structure.\n> + *\n> + * Return: 0 on success, else -EINVAL\n> + */\n> +static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev)\n> +{\n> + struct generic_ecam_pcie *pcie = dev_get_priv(dev);\n> + struct fdt_resource reg_res;\n> + DECLARE_GLOBAL_DATA_PTR;\n> + int err;\n> +\n> + err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), \"reg\",\n> + 0, ®_res);\n> + if (err < 0) {\n> + error(\"\\\"reg\\\" resource not found\\n\");\n> + return err;\n> + }\n> +\n> + pcie->cfg_base = map_physmem(reg_res.start,\n> + fdt_resource_size(®_res),\n> + MAP_NOCACHE);\n> +\n> + return 0;\n> +}\n> +\n> +static const struct dm_pci_ops pci_generic_ecam_ops = {\n> + .read_config = pci_generic_ecam_read_config,\n> + .write_config = pci_generic_ecam_write_config,\n> +};\n> +\n> +static const struct udevice_id pci_generic_ecam_ids[] = {\n> + { .compatible = \"pci-host-ecam-generic\" },\n> + { }\n> +};\n> +\n> +U_BOOT_DRIVER(pci_generic_ecam) = {\n> + .name = \"pci_generic_ecam\",\n> + .id = UCLASS_PCI,\n> + .of_match = pci_generic_ecam_ids,\n> + .ops = &pci_generic_ecam_ops,\n> + .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata,\n> + .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie),\n> +};\n> --\n\nOther than above nits:\nReviewed-by: Bin Meng \n\nRegards,\nBin","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1782108,"web_url":"http://patchwork.ozlabs.org/comment/1782108/","msgid":"<20171007130758.GR25966@bill-the-cat>","list_archive_url":null,"date":"2017-10-07T13:07:58","subject":"Re: [U-Boot] [U-Boot, v2,\n\t4/6] PCI: Add driver for a 'pci-host-ecam-generic' host controller","submitter":{"id":65875,"url":"http://patchwork.ozlabs.org/api/people/65875/","name":"Tom Rini","email":"trini@konsulko.com"},"content":"On Tue, Sep 19, 2017 at 11:18:06PM +0300, Tuomas Tynkkynen wrote:\n\n> QEMU emulates such a device with '-machine virt,highmem=off' on ARM.\n> The 'highmem=off' part is required for things to work as the PCI code\n> in U-Boot doesn't seem to support 64-bit BARs.\n> \n> Signed-off-by: Tuomas Tynkkynen \n> Reviewed-by: Bin Meng \n\nApplied to u-boot/master, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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