[{"id":1771259,"web_url":"http://patchwork.ozlabs.org/comment/1771259/","msgid":"<452a304a-70e4-c3ab-2e76-a67823922e90@linaro.org>","list_archive_url":null,"date":"2017-09-19T17:47:37","subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/19/2017 09:26 AM, David Hildenbrand wrote:\n> + const uint8_t fc = env->regs[0] & 0x7fULL;\n\nDon't mask here...\n\n> + if (fc >= 128 || !test_be_bit(fc, subfunc)) {\n> + cpu_restore_state(cs, ra);\n> + program_interrupt(env, PGM_SPECIFICATION, 4);\n> + return 0;\n> + }\n\n... because you are indeed supposed to test bit 56. But you've already ensured\nthat won't be set above.\n\nDo you in fact need to set bit 63 in subfunc, since that itself is query?\nCertainly you won't get past this test, regardless...\n\n\n> +static ExitStatus op_msa(DisasContext *s, DisasOps *o)\n> +{\n> + int r1 = have_field(s->fields, r1) ? get_field(s->fields, r1) : 0;\n> + int r2 = have_field(s->fields, r2) ? get_field(s->fields, r2) : 0;\n> + int r3 = have_field(s->fields, r3) ? get_field(s->fields, r3) : 0;\n> + TCGv_i32 t_r1, t_r2, t_r3, type;\n> +\n> + switch (s->insn->data) {\n> + case S390_FEAT_TYPE_KMCTR:\n> + if (r3 & 1 || !r3) {\n> + gen_program_exception(s, PGM_SPECIFICATION);\n> + return EXIT_NORETURN;\n> + }\n> + /* FALL THROUGH */\n> + case S390_FEAT_TYPE_PPNO:\n> + case S390_FEAT_TYPE_KMF:\n> + case S390_FEAT_TYPE_KMC:\n> + case S390_FEAT_TYPE_KMO:\n> + case S390_FEAT_TYPE_KM:\n> + if (r1 & 1 || !r1) {\n> + gen_program_exception(s, PGM_SPECIFICATION);\n> + return EXIT_NORETURN;\n> + }\n> + /* FALL THROUGH */\n> + case S390_FEAT_TYPE_KMAC:\n> + case S390_FEAT_TYPE_KIMD:\n> + case S390_FEAT_TYPE_KLMD:\n> + if (r2 & 1 || !r2) {\n> + gen_program_exception(s, PGM_SPECIFICATION);\n> + return EXIT_NORETURN;\n> + }\n\nEven though it would be silly to do so, considering that r0+r1 are implicit\narguments to these insns, I see nothing that insists that r[123] are not 0,\nonly that they are even.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170919142654.16369-4-david@redhat.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:4001:c06::22f","Subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"thuth@redhat.com, cohuck@redhat.com, Alexander Graf ,\n\tAurelien Jarno ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1771323,"web_url":"http://patchwork.ozlabs.org/comment/1771323/","msgid":"<8bc7cb17-522a-48ea-5818-12bdbfb37d70@redhat.com>","list_archive_url":null,"date":"2017-09-19T19:36:55","subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","submitter":{"id":70402,"url":"http://patchwork.ozlabs.org/api/people/70402/","name":"David Hildenbrand","email":"david@redhat.com"},"content":"On 19.09.2017 19:47, Richard Henderson wrote:\n> On 09/19/2017 09:26 AM, David Hildenbrand wrote:\n>> + const uint8_t fc = env->regs[0] & 0x7fULL;\n> \n> Don't mask here...\n\nBit 56 is the mod bit (see variable \"mod\") and is checked inside the\nswitch(). The function code really is just composed of bit 57 - 63, so\nthis is correct.\n\n> \n>> + if (fc >= 128 || !test_be_bit(fc, subfunc)) {\n\n... however the fc >= 128 case can be dropped, as this can in fact never\nhappen (due to the masking).\n\n>> + cpu_restore_state(cs, ra);\n>> + program_interrupt(env, PGM_SPECIFICATION, 4);\n>> + return 0;\n>> + }\n> \n> ... because you are indeed supposed to test bit 56. But you've already ensured\n> that won't be set above.\n> \n> Do you in fact need to set bit 63 in subfunc, since that itself is query?\n> Certainly you won't get past this test, regardless...\n\nYes, it always has to be set and is guaranteed by s390_get_feat_block().\nSo test_be_bit(fc, subfunc) will always allow bit 0 (query).\n\nEspecially due to the statement:\n\n\"When a bit is one, the corresponding function is installed; otherwise,\nthe function is not installed.\"\n\nQuery is always installed.\n\n\n> \n> \n>> +static ExitStatus op_msa(DisasContext *s, DisasOps *o)\n>> +{\n>> + int r1 = have_field(s->fields, r1) ? get_field(s->fields, r1) : 0;\n>> + int r2 = have_field(s->fields, r2) ? get_field(s->fields, r2) : 0;\n>> + int r3 = have_field(s->fields, r3) ? get_field(s->fields, r3) : 0;\n>> + TCGv_i32 t_r1, t_r2, t_r3, type;\n>> +\n>> + switch (s->insn->data) {\n>> + case S390_FEAT_TYPE_KMCTR:\n>> + if (r3 & 1 || !r3) {\n>> + gen_program_exception(s, PGM_SPECIFICATION);\n>> + return EXIT_NORETURN;\n>> + }\n>> + /* FALL THROUGH */\n>> + case S390_FEAT_TYPE_PPNO:\n>> + case S390_FEAT_TYPE_KMF:\n>> + case S390_FEAT_TYPE_KMC:\n>> + case S390_FEAT_TYPE_KMO:\n>> + case S390_FEAT_TYPE_KM:\n>> + if (r1 & 1 || !r1) {\n>> + gen_program_exception(s, PGM_SPECIFICATION);\n>> + return EXIT_NORETURN;\n>> + }\n>> + /* FALL THROUGH */\n>> + case S390_FEAT_TYPE_KMAC:\n>> + case S390_FEAT_TYPE_KIMD:\n>> + case S390_FEAT_TYPE_KLMD:\n>> + if (r2 & 1 || !r2) {\n>> + gen_program_exception(s, PGM_SPECIFICATION);\n>> + return EXIT_NORETURN;\n>> + }\n> \n> Even though it would be silly to do so, considering that r0+r1 are implicit\n> arguments to these insns, I see nothing that insists that r[123] are not 0,\n> only that they are even.\n> \n\nE.g. for KMAC (7-187):\n\n\"A specification exception is recognized and no other\naction is taken if any of the following occurs:\n[...]\n The R2 field designates an odd-numbered regis-\nter or general register 0.\"\n\nOr KMCTR (7-103):\n\n\"A specification exception is recognized and no other\naction is taken if any of the following occurs:\n[...]\n The R1 R2, or R3 field designates an odd-num-\nbered register or general register 0.\"\n\n\nI implemented kvm-unit-tests that test all of these conditions.\nEspecially they also pass on KVM, so I assume they are correct (as these\ninstructions are fully interpreted by HW).\n\nhttps://www.spinics.net/lists/kvm/msg155690.html\n\nIn the test included is\na) checking that the mod bit must not be set for certain instructions\nb) r1-3 either odd or 0 for certain instructions\nc) that query is always indicated\n\n\nThanks for the review!\n\n> \n> r~\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx09.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx09.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxY8Y1Q7Rz9s7p\n\tfor ;\n\tWed, 20 Sep 2017 05:38:53 +1000 (AEST)","from localhost ([::1]:45052 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duOM7-0004pK-Aj\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 15:38:51 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43248)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duOKg-000464-FA\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 15:37:23 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duOKc-0007Sm-Hh\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 15:37:22 -0400","from mx1.redhat.com ([209.132.183.28]:41008)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1duOKc-0007Rt-9o\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 15:37:18 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 195814E334;\n\tTue, 19 Sep 2017 19:37:17 +0000 (UTC)","from [10.36.116.118] (ovpn-116-118.ams2.redhat.com [10.36.116.118])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id AB8275C882;\n\tTue, 19 Sep 2017 19:36:56 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 195814E334","To":"Richard Henderson , qemu-devel@nongnu.org","References":"<20170919142654.16369-1-david@redhat.com>\n\t<20170919142654.16369-4-david@redhat.com>\n\t<452a304a-70e4-c3ab-2e76-a67823922e90@linaro.org>","From":"David Hildenbrand ","Organization":"Red Hat GmbH","Message-ID":"<8bc7cb17-522a-48ea-5818-12bdbfb37d70@redhat.com>","Date":"Tue, 19 Sep 2017 21:36:55 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<452a304a-70e4-c3ab-2e76-a67823922e90@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.38]);\n\tTue, 19 Sep 2017 19:37:17 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"thuth@redhat.com, cohuck@redhat.com, Alexander Graf ,\n\tAurelien Jarno ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1771889,"web_url":"http://patchwork.ozlabs.org/comment/1771889/","msgid":"<3e21fee6-4560-a3c9-926a-165a6212b1ef@linaro.org>","list_archive_url":null,"date":"2017-09-20T13:23:32","subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/19/2017 02:36 PM, David Hildenbrand wrote:\n> On 19.09.2017 19:47, Richard Henderson wrote:\n>> On 09/19/2017 09:26 AM, David Hildenbrand wrote:\n>>> + const uint8_t fc = env->regs[0] & 0x7fULL;\n>>\n>> Don't mask here...\n> \n> Bit 56 is the mod bit (see variable \"mod\") and is checked inside the\n> switch(). The function code really is just composed of bit 57 - 63, so\n> this is correct.\n\n\"mod bit\"?\n\n # Bit 56 of general register 0 must be zero; oth-\n # erwise, a specification exception is recognized.\n\nI don't suppose this is a change in PoO v11? I'm still looking at v10.\n\n> E.g. for KMAC (7-187):\n> \n> \"A specification exception is recognized and no other\n> action is taken if any of the following occurs:\n> [...]\n> The R2 field designates an odd-numbered regis-\n> ter or general register 0.\"\n\nHmm, ok. There's different text earlier on page 7-178 that describes the\neven-odd requirement but omits the non-zero requirement. Irritating.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"DeG9GH+S\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xy1dw5pZ6z9s82\n\tfor ;\n\tThu, 21 Sep 2017 00:02:28 +1000 (AEST)","from localhost ([::1]:48283 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dufa6-0007c2-MT\n\tfor incoming@patchwork.ozlabs.org; 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\n\tWed, 20 Sep 2017 06:23:35 -0700 (PDT)","To":"David Hildenbrand , qemu-devel@nongnu.org","References":"<20170919142654.16369-1-david@redhat.com>\n\t<20170919142654.16369-4-david@redhat.com>\n\t<452a304a-70e4-c3ab-2e76-a67823922e90@linaro.org>\n\t<8bc7cb17-522a-48ea-5818-12bdbfb37d70@redhat.com>","From":"Richard Henderson ","Message-ID":"<3e21fee6-4560-a3c9-926a-165a6212b1ef@linaro.org>","Date":"Wed, 20 Sep 2017 08:23:32 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<8bc7cb17-522a-48ea-5818-12bdbfb37d70@redhat.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:4003:c06::22f","Subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"thuth@redhat.com, cohuck@redhat.com, Alexander Graf ,\n\tAurelien Jarno ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1771920,"web_url":"http://patchwork.ozlabs.org/comment/1771920/","msgid":"","list_archive_url":null,"date":"2017-09-20T13:37:57","subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","submitter":{"id":70402,"url":"http://patchwork.ozlabs.org/api/people/70402/","name":"David Hildenbrand","email":"david@redhat.com"},"content":"On 20.09.2017 15:23, Richard Henderson wrote:\n> On 09/19/2017 02:36 PM, David Hildenbrand wrote:\n>> On 19.09.2017 19:47, Richard Henderson wrote:\n>>> On 09/19/2017 09:26 AM, David Hildenbrand wrote:\n>>>> + const uint8_t fc = env->regs[0] & 0x7fULL;\n>>>\n>>> Don't mask here...\n>>\n>> Bit 56 is the mod bit (see variable \"mod\") and is checked inside the\n>> switch(). The function code really is just composed of bit 57 - 63, so\n>> this is correct.\n> \n> \"mod bit\"?\n> \n> # Bit 56 of general register 0 must be zero; oth-\n> # erwise, a specification exception is recognized.\n> \n> I don't suppose this is a change in PoO v11? I'm still looking at v10.\n> \n\nI'm also looking at v10.\n\nThis bit is called \"M\" bit for all cpacf instructions that allow\nen/decryption. M == modifier bit == mod bit == bit 56\n\ne.g. for KM (7-56)\n\n\"When the modifier bit in general register 0 is one, a\ndecipher operation is performed. ...\".\n\nFor instructions that don't allow switching between de/encryption (e.g.\nKLMD), the modifier bit a.k.a. bit 56 must not be set.\n\nI don't really see the need here to rename mod -> bit_56 here.\n\nThank!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xy2KQ22V1z9s82\n\tfor ;\n\tThu, 21 Sep 2017 00:33:14 +1000 (AEST)","from localhost ([::1]:48481 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dug3s-0003XY-6W\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Sep 2017 10:33:12 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43002)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dufCa-0003jT-KX\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 09:38:09 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dufCU-0002MR-OB\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 09:38:08 -0400","from mx1.redhat.com ([209.132.183.28]:42300)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dufCU-0002Lg-Gx\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 09:38:02 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id A6CE7806C2;\n\tWed, 20 Sep 2017 13:38:00 +0000 (UTC)","from [10.36.116.82] (ovpn-116-82.ams2.redhat.com [10.36.116.82])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 2E67117551;\n\tWed, 20 Sep 2017 13:37:58 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com A6CE7806C2","To":"Richard Henderson , qemu-devel@nongnu.org","References":"<20170919142654.16369-1-david@redhat.com>\n\t<20170919142654.16369-4-david@redhat.com>\n\t<452a304a-70e4-c3ab-2e76-a67823922e90@linaro.org>\n\t<8bc7cb17-522a-48ea-5818-12bdbfb37d70@redhat.com>\n\t<3e21fee6-4560-a3c9-926a-165a6212b1ef@linaro.org>","From":"David Hildenbrand ","Organization":"Red Hat GmbH","Message-ID":"","Date":"Wed, 20 Sep 2017 15:37:57 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<3e21fee6-4560-a3c9-926a-165a6212b1ef@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.26]);\n\tWed, 20 Sep 2017 13:38:01 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v2 3/3] s390x/tcg: add basic MSA features","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"thuth@redhat.com, cohuck@redhat.com, Alexander Graf ,\n\tAurelien Jarno ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]