[{"id":1775903,"web_url":"http://patchwork.ozlabs.org/comment/1775903/","msgid":"","list_archive_url":null,"date":"2017-09-26T22:04:13","subject":"Re: [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock\n\tManager driver for Stratix10 SoC","submitter":{"id":16347,"url":"http://patchwork.ozlabs.org/api/people/16347/","name":"Dinh Nguyen","email":"dinh.linux@gmail.com"},"content":"On Tue, Sep 19, 2017 at 4:22 AM, wrote:\n> From: Chin Liang See \n>\n> Add Clock Manager driver support for Stratix SoC\n>\n> Signed-off-by: Chin Liang See \n> ---\n> arch/arm/mach-socfpga/Makefile | 4 +\n> arch/arm/mach-socfpga/clock_manager.c | 4 +-\n> arch/arm/mach-socfpga/clock_manager_s10.c | 359 +++++++++++++++++++++\n> arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +\n> .../mach-socfpga/include/mach/clock_manager_s10.h | 202 ++++++++++++\n> arch/arm/mach-socfpga/include/mach/handoff_s10.h | 29 ++\n> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 46 +++\n> 7 files changed, 644 insertions(+), 2 deletions(-)\n> create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c\n> create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n> create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h\n> create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c\n>\n> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile\n> index 286bfef..e5f9dd7 100644\n> --- a/arch/arm/mach-socfpga/Makefile\n> +++ b/arch/arm/mach-socfpga/Makefile\n> @@ -30,6 +30,10 @@ obj-y += pinmux_arria10.o\n> obj-y += reset_manager_arria10.o\n> endif\n>\n> +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\n> +obj-y += clock_manager_s10.o\n> +obj-y += wrap_pll_config_s10.o\n> +endif\n> ifdef CONFIG_SPL_BUILD\n> obj-y += spl.o\n> ifdef CONFIG_TARGET_SOCFPGA_GEN5\n> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c\n> index cb6ae03..f9450a4 100644\n> --- a/arch/arm/mach-socfpga/clock_manager.c\n> +++ b/arch/arm/mach-socfpga/clock_manager.c\n> @@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)\n> do {\n> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n> inter_val = readl(&clock_manager_base->inter) & mask;\n> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> +#else\n> inter_val = readl(&clock_manager_base->stat) & mask;\n> #endif\n> /* Wait for stable lock */\n> @@ -52,7 +52,7 @@ int set_cpu_clk_info(void)\n>\n> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\n> gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;\n> -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> +#else\n> gd->bd->bi_ddr_freq = 0;\n> #endif\n>\n> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c\n> new file mode 100644\n> index 0000000..a9f9b07\n> --- /dev/null\n> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c\n> @@ -0,0 +1,359 @@\n> +/*\n> + * Copyright (C) 2016-2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +DECLARE_GLOBAL_DATA_PTR;\n> +\n> +static const struct socfpga_clock_manager *clock_manager_base =\n> + (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;\n> +\n> +/*\n> + * function to write the bypass register which requires a poll of the\n> + * busy bit\n> + */\n> +static void cm_write_bypass_mainpll(uint32_t val)\n> +{\n> + writel(val, &clock_manager_base->main_pll.bypass);\n> + cm_wait_for_fsm();\n> +}\n\nAdd a new line..\n\n> +static void cm_write_bypass_perpll(uint32_t val)\n> +{\n> + writel(val, &clock_manager_base->per_pll.bypass);\n> + cm_wait_for_fsm();\n> +}\n> +\n> +/* function to write the ctrl register which requires a poll of the busy bit */\n> +static void cm_write_ctrl(uint32_t val)\n> +{\n> + writel(val, &clock_manager_base->ctrl);\n> + cm_wait_for_fsm();\n> +}\n> +\n> +/*\n> + * Setup clocks while making no assumptions about previous state of the clocks.\n> + *\n\nRemove extra line\n\n> + */\n> +void cm_basic_init(const struct cm_config * const cfg)\n> +{\n> + uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;\n> +\n> + if (cfg == 0)\n> + return;\n> +\n> + /* Put all plls in bypass */\n> + cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);\n> + cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);\n> +\n> + /* setup main PLL dividers */\n> + /* calculate the vcocalib value */\n\nMove the above comment to where vcocalib is getting calculated, or remove.\n\n> + mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n> + CLKMGR_FDBCK_MDIV_MASK;\n> + refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n> + mscnt = 200 / (6 + mdiv) / refclkdiv;\n\nWhere are these values, 200 and 6 coming from? Should they be a #define?\n\n> + hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;\n\nSame for 6 and 9 here...\n\n> + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n> + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n> + CLKMGR_VCOCALIB_MSCNT_OFFSET);\n> +\n> + writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n> + ~CLKMGR_PLLGLOB_RST_MASK),\n> + &clock_manager_base->main_pll.pllglob);\n> + writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);\n> + writel(vcocalib, &clock_manager_base->main_pll.vcocalib);\n> + writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);\n> + writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);\n> + writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);\n> +\n> + /* setup peripheral PLL dividers */\n> + /* calculate the vcocalib value */\n> + mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n> + CLKMGR_FDBCK_MDIV_MASK;\n> + refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n> + mscnt = 200 / (6 + mdiv) / refclkdiv;\n> + hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;\n> + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n> + ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n> + CLKMGR_VCOCALIB_MSCNT_OFFSET);\n\nSame comments as above...\n\n> +\n> + writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n> + ~CLKMGR_PLLGLOB_RST_MASK),\n> + &clock_manager_base->per_pll.pllglob);\n> + writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);\n> + writel(vcocalib, &clock_manager_base->per_pll.vcocalib);\n> + writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);\n> + writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);\n> + writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);\n> + writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);\n> +\n> + /* Take both PLL out of reset and power up */\n> + setbits_le32(&clock_manager_base->main_pll.pllglob,\n> + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n> + setbits_le32(&clock_manager_base->per_pll.pllglob,\n> + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n> +\n> +#define LOCKED_MASK \\\n> + (CLKMGR_STAT_MAINPLL_LOCKED | \\\n> + CLKMGR_STAT_PERPLL_LOCKED)\n> +\n> + cm_wait_for_lock(LOCKED_MASK);\n> +\n> + /*\n> + * Dividers for C2 to C9 only init after PLLs are lock. We will a large\n> + * dividers value then final value as requested by hardware behaviour\n\nCan you update this comment? I don't understand what \"We will a large\" means.\n\n> + */\n> + writel(0xff, &clock_manager_base->main_pll.mpuclk);\n> + writel(0xff, &clock_manager_base->main_pll.nocclk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr2clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr3clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr4clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr5clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr6clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr7clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr8clk);\n> + writel(0xff, &clock_manager_base->main_pll.cntr9clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr2clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr3clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr4clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr5clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr6clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr7clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr8clk);\n> + writel(0xff, &clock_manager_base->per_pll.cntr9clk);\n> +\n> + writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);\n> + writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);\n> + writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);\n> + writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);\n> + writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);\n> + writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);\n> + writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);\n> + writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);\n> + writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);\n> + writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);\n> + writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);\n> + writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);\n> + writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);\n> + writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);\n> + writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);\n> + writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);\n> + writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);\n> + writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);\n> +\n> + /* Take all PLLs out of bypass */\n> + cm_write_bypass_mainpll(0);\n> + cm_write_bypass_perpll(0);\n> +\n> + /* clear safe mode / out of boot mode */\n> + cm_write_ctrl(readl(&clock_manager_base->ctrl)\n> + & ~(CLKMGR_CTRL_SAFEMODE));\n> +\n> + /* Now ungate non-hw-managed clocks */\n> + writel(~0, &clock_manager_base->main_pll.en);\n> + writel(~0, &clock_manager_base->per_pll.en);\n> +\n> + /* Clear the loss of lock bits (write 1 to clear) */\n> + writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,\n> + &clock_manager_base->intrclr);\n> +}\n> +\n> +static unsigned long cm_get_main_vco_clk_hz(void)\n> +{\n> + unsigned long fref, refdiv, mdiv, reg, vco;\n> +\n> + reg = readl(&clock_manager_base->main_pll.pllglob);\n> +\n> + /* get the fref */\n\nUseless comment...\n\n> + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n> + CLKMGR_PLLGLOB_VCO_PSRC_MASK;\n> + switch (fref) {\n> + case CLKMGR_VCO_PSRC_EOSC1:\n> + fref = cm_get_osc_clk_hz(0);\n> + break;\n> + case CLKMGR_VCO_PSRC_INTOSC:\n> + fref = cm_get_intosc_clk_hz();\n> + break;\n> + case CLKMGR_VCO_PSRC_F2S:\n> + fref = cm_get_fpga_clk_hz();\n> + break;\n> + }\n> +\n> + /* get the refdiv */\n\nsame..\n\n> + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n> +\n> + /* get the mdiv */\n\nsame...\n\n> + reg = readl(&clock_manager_base->main_pll.fdbck);\n> + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n> +\n> + vco = fref / refdiv;\n> + vco = vco * (6 + mdiv);\n\nWhy 6? Define?\n\n> + return vco;\n> +}\n> +\n> +static unsigned long cm_get_per_vco_clk_hz(void)\n> +{\n> + unsigned long fref, refdiv, mdiv, reg, vco;\n> +\n> + reg = readl(&clock_manager_base->per_pll.pllglob);\n> +\n> + /* get the fref */\n> + fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n> + CLKMGR_PLLGLOB_VCO_PSRC_MASK;\n> + switch (fref) {\n> + case CLKMGR_VCO_PSRC_EOSC1:\n> + fref = cm_get_osc_clk_hz(0);\n> + break;\n> + case CLKMGR_VCO_PSRC_INTOSC:\n> + fref = cm_get_intosc_clk_hz();\n> + break;\n> + case CLKMGR_VCO_PSRC_F2S:\n> + fref = cm_get_fpga_clk_hz();\n> + break;\n> + }\n> +\n> + /* get the refdiv */\n> + refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n> + CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n> +\n> + /* get the mdiv */\n> + reg = readl(&clock_manager_base->per_pll.fdbck);\n> + mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n> +\n> + vco = fref / refdiv;\n> + vco = vco * (6 + mdiv);\n> + return vco;\n> +}\n> +\n> +unsigned long cm_get_mpu_clk_hz(void)\n> +{\n> + unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);\n> + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n> +\n> + switch (clock) {\n> + case CLKMGR_CLKSRC_MAIN:\n> + clock = cm_get_main_vco_clk_hz();\n> + clock /= (readl(&clock_manager_base->main_pll.pllc0) &\n> + CLKMGR_PLLC0_DIV_MASK);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_PER:\n> + clock = cm_get_per_vco_clk_hz();\n> + clock /= (readl(&clock_manager_base->per_pll.pllc0) &\n> + CLKMGR_CLKCNT_MSK);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_OSC1:\n> + clock = cm_get_osc_clk_hz(0);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_INTOSC:\n> + clock = cm_get_intosc_clk_hz();\n> + break;\n> +\n> + case CLKMGR_CLKSRC_FPGA:\n> + clock = cm_get_fpga_clk_hz();\n> + break;\n> + }\n> +\n> + clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &\n> + CLKMGR_CLKCNT_MSK);\n> + return clock;\n> +}\n> +\n> +unsigned int cm_get_l3_main_clk_hz(void)\n> +{\n> + uint32_t clock = readl(&clock_manager_base->main_pll.nocclk);\n> + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n> +\n> + switch (clock) {\n> + case CLKMGR_CLKSRC_MAIN:\n> + clock = cm_get_main_vco_clk_hz();\n> + clock /= (readl(&clock_manager_base->main_pll.pllc1) &\n> + CLKMGR_PLLC0_DIV_MASK);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_PER:\n> + clock = cm_get_per_vco_clk_hz();\n> + clock /= (readl(&clock_manager_base->per_pll.pllc1) &\n> + CLKMGR_CLKCNT_MSK);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_OSC1:\n> + clock = cm_get_osc_clk_hz(0);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_INTOSC:\n> + clock = cm_get_intosc_clk_hz();\n> + break;\n> +\n> + case CLKMGR_CLKSRC_FPGA:\n> + clock = cm_get_fpga_clk_hz();\n> + break;\n> + }\n> +\n> + clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &\n> + CLKMGR_CLKCNT_MSK);\n> + return clock;\n> +}\n> +\n> +unsigned int cm_get_mmc_controller_clk_hz(void)\n> +{\n> + uint32_t clock = readl(&clock_manager_base->per_pll.cntr6clk);\n> + clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n> +\n> + switch (clock) {\n> + case CLKMGR_CLKSRC_MAIN:\n> + clock = cm_get_l3_main_clk_hz();\n> + clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &\n> + CLKMGR_CLKCNT_MSK);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_PER:\n> + clock = cm_get_l3_main_clk_hz();\n> + clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &\n> + CLKMGR_CLKCNT_MSK);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_OSC1:\n> + clock = cm_get_osc_clk_hz(0);\n> + break;\n> +\n> + case CLKMGR_CLKSRC_INTOSC:\n> + clock = cm_get_intosc_clk_hz();\n> + break;\n> +\n> + case CLKMGR_CLKSRC_FPGA:\n> + clock = cm_get_fpga_clk_hz();\n> + break;\n> + }\n> + return clock/4;\n\nNeed space between '/'.\n\n> +}\n> +\n> +unsigned int cm_get_l4_sp_clk_hz(void)\n> +{\n> + uint32_t clock = cm_get_l3_main_clk_hz();\n> +\n> + clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>\n> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));\n> + return clock;\n> +}\n> +\n> +void cm_print_clock_quick_summary(void)\n> +{\n> + printf(\"MPU %d kHz\\n\", (u32)(cm_get_mpu_clk_hz() / 1000));\n> + printf(\"L3 main %d kHz\\n\", cm_get_l3_main_clk_hz() / 1000);\n> + printf(\"Main VCO %d kHz\\n\", (u32)(cm_get_main_vco_clk_hz() / 1000));\n> + printf(\"Per VCO %d kHz\\n\", (u32)(cm_get_per_vco_clk_hz() / 1000));\n> + printf(\"EOSC1 %d kHz\\n\", cm_get_osc_clk_hz(0) / 1000);\n> + printf(\"HPS MMC %d kHz\\n\", cm_get_mmc_controller_clk_hz() / 1000);\n> + printf(\"UART %d kHz\\n\", cm_get_l4_sp_clk_hz() / 1000);\n> +}\n> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h\n> index 4c6b1f8..ddf814f 100644\n> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h\n> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h\n> @@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);\n> #include \n> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\n> #include \n> +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\n> +#include \n> #endif\n>\n> #endif /* _CLOCK_MANAGER_H_ */\n> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n> new file mode 100644\n> index 0000000..c99ad97\n> --- /dev/null\n> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n> @@ -0,0 +1,202 @@\n> +/*\n> + * Copyright (C) 2016-2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#ifndef _CLOCK_MANAGER_S10_\n> +#define _CLOCK_MANAGER_S10_\n> +\n> +/* Clock speed accessors */\n> +unsigned long cm_get_mpu_clk_hz(void);\n> +unsigned long cm_get_sdram_clk_hz(void);\n> +unsigned int cm_get_l4_sp_clk_hz(void);\n> +unsigned int cm_get_mmc_controller_clk_hz(void);\n> +unsigned int cm_get_qspi_controller_clk_hz(void);\n> +unsigned int cm_get_spi_controller_clk_hz(void);\n> +const unsigned int cm_get_osc_clk_hz(const int osc);\n> +const unsigned int cm_get_f2s_per_ref_clk_hz(void);\n> +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);\n> +const unsigned int cm_get_intosc_clk_hz(void);\n> +const unsigned int cm_get_fpga_clk_hz(void);\n> +\n> +/* Clock configuration accessors */\n> +const struct cm_config * const cm_get_default_config(void);\n> +\n> +struct cm_config {\n> + /* main group */\n> + uint32_t main_pll_mpuclk;\n> + uint32_t main_pll_nocclk;\n> + uint32_t main_pll_cntr2clk;\n> + uint32_t main_pll_cntr3clk;\n> + uint32_t main_pll_cntr4clk;\n> + uint32_t main_pll_cntr5clk;\n> + uint32_t main_pll_cntr6clk;\n> + uint32_t main_pll_cntr7clk;\n> + uint32_t main_pll_cntr8clk;\n> + uint32_t main_pll_cntr9clk;\n> + uint32_t main_pll_nocdiv;\n> + uint32_t main_pll_pllglob;\n> + uint32_t main_pll_fdbck;\n> + uint32_t main_pll_pllc0;\n> + uint32_t main_pll_pllc1;\n> + uint32_t spare;\n> +\n> + /* peripheral group */\n> + uint32_t per_pll_cntr2clk;\n> + uint32_t per_pll_cntr3clk;\n> + uint32_t per_pll_cntr4clk;\n> + uint32_t per_pll_cntr5clk;\n> + uint32_t per_pll_cntr6clk;\n> + uint32_t per_pll_cntr7clk;\n> + uint32_t per_pll_cntr8clk;\n> + uint32_t per_pll_cntr9clk;\n> + uint32_t per_pll_emacctl;\n> + uint32_t per_pll_gpiodiv;\n> + uint32_t per_pll_pllglob;\n> + uint32_t per_pll_fdbck;\n> + uint32_t per_pll_pllc0;\n> + uint32_t per_pll_pllc1;\n> +\n> + /* incoming clock */\n> + uint32_t hps_osc_clk_hz;\n> + uint32_t fpga_clk_hz;\n> +};\n> +\n> +void cm_basic_init(const struct cm_config * const cfg);\n> +\n> +struct socfpga_clock_manager_main_pll {\n> + u32 en;\n> + u32 ens;\n> + u32 enr;\n> + u32 bypass;\n> + u32 bypasss;\n> + u32 bypassr;\n> + u32 mpuclk;\n> + u32 nocclk;\n> + u32 cntr2clk;\n> + u32 cntr3clk;\n> + u32 cntr4clk;\n> + u32 cntr5clk;\n> + u32 cntr6clk;\n> + u32 cntr7clk;\n> + u32 cntr8clk;\n> + u32 cntr9clk;\n> + u32 nocdiv;\n> + u32 pllglob;\n> + u32 fdbck;\n> + u32 mem;\n> + u32 memstat;\n> + u32 pllc0;\n> + u32 pllc1;\n> + u32 vcocalib;\n> + u32 _pad_0x90_0xA0[5];\n> +};\n> +\n> +struct socfpga_clock_manager_per_pll {\n> + u32 en;\n> + u32 ens;\n> + u32 enr;\n> + u32 bypass;\n> + u32 bypasss;\n> + u32 bypassr;\n> + u32 cntr2clk;\n> + u32 cntr3clk;\n> + u32 cntr4clk;\n> + u32 cntr5clk;\n> + u32 cntr6clk;\n> + u32 cntr7clk;\n> + u32 cntr8clk;\n> + u32 cntr9clk;\n> + u32 emacctl;\n> + u32 gpiodiv;\n> + u32 pllglob;\n> + u32 fdbck;\n> + u32 mem;\n> + u32 memstat;\n> + u32 pllc0;\n> + u32 pllc1;\n> + u32 vcocalib;\n> + u32 _pad_0x100_0x124[10];\n> +};\n> +\n> +struct socfpga_clock_manager {\n> + u32 ctrl;\n> + u32 stat;\n> + u32 testioctrl;\n> + u32 intrgen;\n> + u32 intrmsk;\n> + u32 intrclr;\n> + u32 intrsts;\n> + u32 intrstk;\n> + u32 intrraw;\n> + u32 _pad_0x24_0x2c[3];\n> + struct socfpga_clock_manager_main_pll main_pll;\n> + struct socfpga_clock_manager_per_pll per_pll;\n> +};\n> +\n> +#define CLKMGR_CTRL_SAFEMODE (1 << 0)\n> +#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007\n> +#define CLKMGR_BYPASS_PERPLL_ALL 0x0000007f\n> +\n> +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001\n> +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002\n> +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004\n> +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008\n> +#define CLKMGR_STAT_BUSY (1 << 0)\n> +#define CLKMGR_STAT_MAINPLL_LOCKED (1 << 8)\n> +#define CLKMGR_STAT_PERPLL_LOCKED (1 << 9)\n> +\n> +#define CLKMGR_PLLGLOB_PD_MASK 0x00000001\n> +#define CLKMGR_PLLGLOB_RST_MASK 0x00000002\n> +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK 0X3\n> +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16\n> +#define CLKMGR_VCO_PSRC_EOSC1 0\n> +#define CLKMGR_VCO_PSRC_INTOSC 1\n> +#define CLKMGR_VCO_PSRC_F2S 2\n> +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK 0X3f\n> +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8\n> +\n> +#define CLKMGR_CLKSRC_MASK 0x7\n> +#define CLKMGR_CLKSRC_OFFSET 16\n> +#define CLKMGR_CLKSRC_MAIN 0\n> +#define CLKMGR_CLKSRC_PER 1\n> +#define CLKMGR_CLKSRC_OSC1 2\n> +#define CLKMGR_CLKSRC_INTOSC 3\n> +#define CLKMGR_CLKSRC_FPGA 4\n> +#define CLKMGR_CLKCNT_MSK 0x7ff\n> +\n> +#define CLKMGR_FDBCK_MDIV_MASK 0xff\n> +#define CLKMGR_FDBCK_MDIV_OFFSET 24\n> +\n> +#define CLKMGR_PLLC0_DIV_MASK 0xff\n> +#define CLKMGR_PLLC1_DIV_MASK 0xff\n> +#define CLKMGR_PLLC0_EN_OFFSET 27\n> +#define CLKMGR_PLLC1_EN_OFFSET 24\n> +\n> +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0\n> +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8\n> +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16\n> +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24\n> +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26\n> +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28\n> +\n> +#define CLKMGR_NOCDIV_L4SPCLK_MASK 0X3\n> +#define CLKMGR_NOCDIV_DIV1 0\n> +#define CLKMGR_NOCDIV_DIV2 1\n> +#define CLKMGR_NOCDIV_DIV4 2\n> +#define CLKMGR_NOCDIV_DIV8 3\n> +#define CLKMGR_CSPDBGCLK_DIV1 0\n> +#define CLKMGR_CSPDBGCLK_DIV4 1\n> +\n> +#define CLKMGR_VCOCALIB_MSCNT_MASK 0xff\n> +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 9\n> +#define CLKMGR_VCOCALIB_HSCNT_MASK 0xff\n> +\n> +#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET 26\n> +#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET 27\n> +#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET 28\n> +\n> +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020\n> +\n> +#endif /* _CLOCK_MANAGER_S10_ */\n> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h\n> new file mode 100644\n> index 0000000..d4b89ac\n> --- /dev/null\n> +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h\n> @@ -0,0 +1,29 @@\n> +/*\n> + * Copyright (C) 2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#ifndef _HANDOFF_S10_H_\n> +#define _HANDOFF_S10_H_\n> +\n> +/*\n> + * Offset for HW handoff from Quartus tools\n> + */\n> +#define CONFIG_HANDOFF_BASE 0xFFE3F000\n> +#define CONFIG_HANDOFF_MUX (CONFIG_HANDOFF_BASE + 0x10)\n> +#define CONFIG_HANDOFF_IOCTL (CONFIG_HANDOFF_BASE + 0x1A0)\n> +#define CONFIG_HANDOFF_FPGA (CONFIG_HANDOFF_BASE + 0x330)\n> +#define CONFIG_HANODFF_DELAY (CONFIG_HANDOFF_BASE + 0x3F0)\n> +#define CONFIG_HANDOFF_CLOCK (CONFIG_HANDOFF_BASE + 0x580)\n> +#define CONFIG_HANDOFF_MISC (CONFIG_HANDOFF_BASE + 0x610)\n> +#define CONFIG_HANDOFF_MAGIC_MUX 0x504D5558\n> +#define CONFIG_HANDOFF_MAGIC_IOCTL 0x494F4354\n> +#define CONFIG_HANDOFF_MAGIC_FPGA 0x46504741\n> +#define CONFIG_HANDOFF_MAGIC_DELAY 0x444C4159\n> +#define CONFIG_HANDOFF_MAGIC_CLOCK 0x434C4B53\n> +#define CONFIG_HANDOFF_MAGIC_MISC 0x4D495343\n> +#define CONFIG_HANDOFF_OFFSET_LENGTH 0x4\n> +#define CONFIG_HANDOFF_OFFSET_DATA 0x10\n> +\n> +#endif /* _HANDOFF_S10_H_ */\n> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c\n> new file mode 100644\n> index 0000000..2a624d5\n> --- /dev/null\n> +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c\n> @@ -0,0 +1,46 @@\n> +/*\n> + * Copyright (C) 2016-2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +const struct cm_config * const cm_get_default_config(void)\n> +{\n> + struct cm_config *cm_handoff_cfg = (struct cm_config *)\n> + (CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA);\n> + u32 *conversion = (u32 *)cm_handoff_cfg;\n> + u32 i;\n> +\n> + if (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) {\n> + writel(swab32(readl(CONFIG_HANDOFF_CLOCK)),\n> + CONFIG_HANDOFF_CLOCK);\n> + for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)\n> + conversion[i] = swab32(conversion[i]);\n> + return cm_handoff_cfg;\n> + } else if (readl(CONFIG_HANDOFF_CLOCK) == CONFIG_HANDOFF_MAGIC_CLOCK) {\n> + return cm_handoff_cfg;\n> + } else\n> + return 0;\n> +}\n> +\n> +const unsigned int cm_get_osc_clk_hz(const int osc)\n> +{\n> + return 25000000;\n\nNeeds to be a #define\n\n> +}\n> +\n> +const unsigned int cm_get_intosc_clk_hz(void)\n> +{\n> + /* theory maximum internal osc clock */\n> + return 460000000;\n\nSame...\n\n> +}\n> +\n> +const unsigned int cm_get_fpga_clk_hz(void)\n> +{\n> + /* assuming 50MHz */\n> + return 50000000;\n\nSame..\n\nDinh","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ikLjC1We\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1w3G3FHQz9sBW\n\tfor ;\n\tWed, 27 Sep 2017 08:04:26 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 3E947C21D19; Tue, 26 Sep 2017 22:04:25 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 73D2CC21C29;\n\tTue, 26 Sep 2017 22:04:18 +0000 (UTC)","by lists.denx.de (Postfix, from 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<1505812951-25088-4-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>\n\t<1505812951-25088-4-git-send-email-chin.liang.see@intel.com>","From":"Dinh Nguyen ","Date":"Tue, 26 Sep 2017 17:04:13 -0500","Message-ID":"","To":"Chin Liang See ","Cc":"Marek Vasut , ZY - u-boot ,\n\tTien Fong Chee ","Subject":"Re: [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock\n\tManager driver for Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777554,"web_url":"http://patchwork.ozlabs.org/comment/1777554/","msgid":"<1506776325.2766.7.camel@intel.com>","list_archive_url":null,"date":"2017-09-29T12:58:04","subject":"Re: [U-Boot] [PATCH 03/14] arm: socfpga: stratix10: Add Clock\n\tManager driver for Stratix10 SoC","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"content":"On Tue, 2017-09-26 at 17:04 -0500, Dinh Nguyen wrote:\r\n> On Tue, Sep 19, 2017 at 4:22 AM,   wrote:\r\n> > \r\n> > From: Chin Liang See \r\n> > \r\n> > Add Clock Manager driver support for Stratix SoC\r\n> > \r\n> > Signed-off-by: Chin Liang See \r\n> > ---\r\n> >  arch/arm/mach-socfpga/Makefile                     |   4 +\r\n> >  arch/arm/mach-socfpga/clock_manager.c              |   4 +-\r\n> >  arch/arm/mach-socfpga/clock_manager_s10.c          | 359\r\n> > +++++++++++++++++++++\r\n> >  arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +\r\n> >  .../mach-socfpga/include/mach/clock_manager_s10.h  | 202\r\n> > ++++++++++++\r\n> >  arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++\r\n> >  arch/arm/mach-socfpga/wrap_pll_config_s10.c        |  46 +++\r\n> >  7 files changed, 644 insertions(+), 2 deletions(-)\r\n> >  create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c\r\n> >  create mode 100644 arch/arm/mach-\r\n> > socfpga/include/mach/clock_manager_s10.h\r\n> >  create mode 100644 arch/arm/mach-\r\n> > socfpga/include/mach/handoff_s10.h\r\n> >  create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-\r\n> > socfpga/Makefile\r\n> > index 286bfef..e5f9dd7 100644\r\n> > --- a/arch/arm/mach-socfpga/Makefile\r\n> > +++ b/arch/arm/mach-socfpga/Makefile\r\n> > @@ -30,6 +30,10 @@ obj-y        += pinmux_arria10.o\r\n> >  obj-y  += reset_manager_arria10.o\r\n> >  endif\r\n> > \r\n> > +ifdef CONFIG_TARGET_SOCFPGA_STRATIX10\r\n> > +obj-y  += clock_manager_s10.o\r\n> > +obj-y  += wrap_pll_config_s10.o\r\n> > +endif\r\n> >  ifdef CONFIG_SPL_BUILD\r\n> >  obj-y  += spl.o\r\n> >  ifdef CONFIG_TARGET_SOCFPGA_GEN5\r\n> > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-\r\n> > socfpga/clock_manager.c\r\n> > index cb6ae03..f9450a4 100644\r\n> > --- a/arch/arm/mach-socfpga/clock_manager.c\r\n> > +++ b/arch/arm/mach-socfpga/clock_manager.c\r\n> > @@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)\r\n> >         do {\r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >                 inter_val = readl(&clock_manager_base->inter) &\r\n> > mask;\r\n> > -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +#else\r\n> >                 inter_val = readl(&clock_manager_base->stat) &\r\n> > mask;\r\n> >  #endif\r\n> >                 /* Wait for stable lock */\r\n> > @@ -52,7 +52,7 @@ int set_cpu_clk_info(void)\r\n> > \r\n> >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)\r\n> >         gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;\r\n> > -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> > +#else\r\n> >         gd->bd->bi_ddr_freq = 0;\r\n> >  #endif\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c\r\n> > b/arch/arm/mach-socfpga/clock_manager_s10.c\r\n> > new file mode 100644\r\n> > index 0000000..a9f9b07\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c\r\n> > @@ -0,0 +1,359 @@\r\n> > +/*\r\n> > + * Copyright (C) 2016-2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +\r\n> > +DECLARE_GLOBAL_DATA_PTR;\r\n> > +\r\n> > +static const struct socfpga_clock_manager *clock_manager_base =\r\n> > +       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;\r\n> > +\r\n> > +/*\r\n> > + * function to write the bypass register which requires a poll of\r\n> > the\r\n> > + * busy bit\r\n> > + */\r\n> > +static void cm_write_bypass_mainpll(uint32_t val)\r\n> > +{\r\n> > +       writel(val, &clock_manager_base->main_pll.bypass);\r\n> > +       cm_wait_for_fsm();\r\n> > +}\r\n> Add a new line..\r\n> \r\n> > \r\n> > +static void cm_write_bypass_perpll(uint32_t val)\r\n> > +{\r\n> > +       writel(val, &clock_manager_base->per_pll.bypass);\r\n> > +       cm_wait_for_fsm();\r\n> > +}\r\n> > +\r\n> > +/* function to write the ctrl register which requires a poll of\r\n> > the busy bit */\r\n> > +static void cm_write_ctrl(uint32_t val)\r\n> > +{\r\n> > +       writel(val, &clock_manager_base->ctrl);\r\n> > +       cm_wait_for_fsm();\r\n> > +}\r\n> > +\r\n> > +/*\r\n> > + * Setup clocks while making no assumptions about previous state\r\n> > of the clocks.\r\n> > + *\r\n> Remove extra line\r\n> \r\n> > \r\n> > + */\r\n> > +void cm_basic_init(const struct cm_config * const cfg)\r\n> > +{\r\n> > +       uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;\r\n> > +\r\n> > +       if (cfg == 0)\r\n> > +               return;\r\n> > +\r\n> > +       /* Put all plls in bypass */\r\n> > +       cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);\r\n> > +       cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);\r\n> > +\r\n> > +       /* setup main PLL dividers */\r\n> > +       /* calculate the vcocalib value */\r\n> Move the above comment to where vcocalib is getting calculated, or\r\n> remove.\r\n> \r\n> > \r\n> > +       mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\r\n> > +               CLKMGR_FDBCK_MDIV_MASK;\r\n> > +       refclkdiv = (cfg->main_pll_pllglob >>\r\n> > CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\r\n> > +                    CLKMGR_PLLGLOB_REFCLKDIV_MASK;\r\n> > +       mscnt = 200 / (6 + mdiv) / refclkdiv;\r\n> Where are these values, 200 and 6 coming from? Should they be a\r\n> #define?\r\n> \r\n\r\nYes, I can improve the readaibility here.\r\n\r\n> > \r\n> > +       hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;\r\n> Same for 6 and 9 here...\r\n> \r\n> > \r\n> > +       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\r\n> > +                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\r\n> > +                  CLKMGR_VCOCALIB_MSCNT_OFFSET);\r\n> > +\r\n> > +       writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\r\n> > +               ~CLKMGR_PLLGLOB_RST_MASK),\r\n> > +               &clock_manager_base->main_pll.pllglob);\r\n> > +       writel(cfg->main_pll_fdbck, &clock_manager_base-\r\n> > >main_pll.fdbck);\r\n> > +       writel(vcocalib, &clock_manager_base->main_pll.vcocalib);\r\n> > +       writel(cfg->main_pll_pllc0, &clock_manager_base-\r\n> > >main_pll.pllc0);\r\n> > +       writel(cfg->main_pll_pllc1, &clock_manager_base-\r\n> > >main_pll.pllc1);\r\n> > +       writel(cfg->main_pll_nocdiv, &clock_manager_base-\r\n> > >main_pll.nocdiv);\r\n> > +\r\n> > +       /* setup peripheral PLL dividers */\r\n> > +       /* calculate the vcocalib value */\r\n> > +       mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\r\n> > +               CLKMGR_FDBCK_MDIV_MASK;\r\n> > +       refclkdiv = (cfg->per_pll_pllglob >>\r\n> > CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\r\n> > +                    CLKMGR_PLLGLOB_REFCLKDIV_MASK;\r\n> > +       mscnt = 200 / (6 + mdiv) / refclkdiv;\r\n> > +       hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;\r\n> > +       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\r\n> > +                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\r\n> > +                  CLKMGR_VCOCALIB_MSCNT_OFFSET);\r\n> Same comments as above...\r\n> \r\n> > \r\n> > +\r\n> > +       writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\r\n> > +               ~CLKMGR_PLLGLOB_RST_MASK),\r\n> > +               &clock_manager_base->per_pll.pllglob);\r\n> > +       writel(cfg->per_pll_fdbck, &clock_manager_base-\r\n> > >per_pll.fdbck);\r\n> > +       writel(vcocalib, &clock_manager_base->per_pll.vcocalib);\r\n> > +       writel(cfg->per_pll_pllc0, &clock_manager_base-\r\n> > >per_pll.pllc0);\r\n> > +       writel(cfg->per_pll_pllc1, &clock_manager_base-\r\n> > >per_pll.pllc1);\r\n> > +       writel(cfg->per_pll_emacctl, &clock_manager_base-\r\n> > >per_pll.emacctl);\r\n> > +       writel(cfg->per_pll_gpiodiv, &clock_manager_base-\r\n> > >per_pll.gpiodiv);\r\n> > +\r\n> > +       /* Take both PLL out of reset and power up */\r\n> > +       setbits_le32(&clock_manager_base->main_pll.pllglob,\r\n> > +                    CLKMGR_PLLGLOB_PD_MASK |\r\n> > CLKMGR_PLLGLOB_RST_MASK);\r\n> > +       setbits_le32(&clock_manager_base->per_pll.pllglob,\r\n> > +                    CLKMGR_PLLGLOB_PD_MASK |\r\n> > CLKMGR_PLLGLOB_RST_MASK);\r\n> > +\r\n> > +#define LOCKED_MASK \\\r\n> > +       (CLKMGR_STAT_MAINPLL_LOCKED | \\\r\n> > +       CLKMGR_STAT_PERPLL_LOCKED)\r\n> > +\r\n> > +       cm_wait_for_lock(LOCKED_MASK);\r\n> > +\r\n> > +       /*\r\n> > +        * Dividers for C2 to C9 only init after PLLs are lock. We\r\n> > will a large\r\n> > +        * dividers value then final value as requested by hardware\r\n> > behaviour\r\n> Can you update this comment? I don't understand what \"We will a\r\n> large\" means.\r\n\r\nLet me rephrase to why instead how.\r\n\r\nChin Liang\r\n\r\n> \r\n> > \r\n> > +        */\r\n> > +       writel(0xff, &clock_manager_base->main_pll.mpuclk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.nocclk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr2clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr3clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr4clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr5clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr6clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr7clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr8clk);\r\n> > +       writel(0xff, &clock_manager_base->main_pll.cntr9clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr2clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr3clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr4clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr5clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr6clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr7clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr8clk);\r\n> > +       writel(0xff, &clock_manager_base->per_pll.cntr9clk);\r\n> > +\r\n> > +       writel(cfg->main_pll_mpuclk, &clock_manager_base-\r\n> > >main_pll.mpuclk);\r\n> > +       writel(cfg->main_pll_nocclk, &clock_manager_base-\r\n> > >main_pll.nocclk);\r\n> > +       writel(cfg->main_pll_cntr2clk, &clock_manager_base-\r\n> > >main_pll.cntr2clk);\r\n> > +       writel(cfg->main_pll_cntr3clk, &clock_manager_base-\r\n> > >main_pll.cntr3clk);\r\n> > +       writel(cfg->main_pll_cntr4clk, &clock_manager_base-\r\n> > >main_pll.cntr4clk);\r\n> > +       writel(cfg->main_pll_cntr5clk, &clock_manager_base-\r\n> > >main_pll.cntr5clk);\r\n> > +       writel(cfg->main_pll_cntr6clk, &clock_manager_base-\r\n> > >main_pll.cntr6clk);\r\n> > +       writel(cfg->main_pll_cntr7clk, &clock_manager_base-\r\n> > >main_pll.cntr7clk);\r\n> > +       writel(cfg->main_pll_cntr8clk, &clock_manager_base-\r\n> > >main_pll.cntr8clk);\r\n> > +       writel(cfg->main_pll_cntr9clk, &clock_manager_base-\r\n> > >main_pll.cntr9clk);\r\n> > +       writel(cfg->per_pll_cntr2clk, &clock_manager_base-\r\n> > >per_pll.cntr2clk);\r\n> > +       writel(cfg->per_pll_cntr3clk, &clock_manager_base-\r\n> > >per_pll.cntr3clk);\r\n> > +       writel(cfg->per_pll_cntr4clk, &clock_manager_base-\r\n> > >per_pll.cntr4clk);\r\n> > +       writel(cfg->per_pll_cntr5clk, &clock_manager_base-\r\n> > >per_pll.cntr5clk);\r\n> > +       writel(cfg->per_pll_cntr6clk, &clock_manager_base-\r\n> > >per_pll.cntr6clk);\r\n> > +       writel(cfg->per_pll_cntr7clk, &clock_manager_base-\r\n> > >per_pll.cntr7clk);\r\n> > +       writel(cfg->per_pll_cntr8clk, &clock_manager_base-\r\n> > >per_pll.cntr8clk);\r\n> > +       writel(cfg->per_pll_cntr9clk, &clock_manager_base-\r\n> > >per_pll.cntr9clk);\r\n> > +\r\n> > +       /* Take all PLLs out of bypass */\r\n> > +       cm_write_bypass_mainpll(0);\r\n> > +       cm_write_bypass_perpll(0);\r\n> > +\r\n> > +       /* clear safe mode / out of boot mode */\r\n> > +       cm_write_ctrl(readl(&clock_manager_base->ctrl)\r\n> > +                       & ~(CLKMGR_CTRL_SAFEMODE));\r\n> > +\r\n> > +       /* Now ungate non-hw-managed clocks */\r\n> > +       writel(~0, &clock_manager_base->main_pll.en);\r\n> > +       writel(~0, &clock_manager_base->per_pll.en);\r\n> > +\r\n> > +       /* Clear the loss of lock bits (write 1 to clear) */\r\n> > +       writel(CLKMGR_INTER_PERPLLLOST_MASK |\r\n> > CLKMGR_INTER_MAINPLLLOST_MASK,\r\n> > +              &clock_manager_base->intrclr);\r\n> > +}\r\n> > +\r\n> > +static unsigned long cm_get_main_vco_clk_hz(void)\r\n> > +{\r\n> > +        unsigned long fref, refdiv, mdiv, reg, vco;\r\n> > +\r\n> > +       reg = readl(&clock_manager_base->main_pll.pllglob);\r\n> > +\r\n> > +       /* get the fref */\r\n> Useless comment...\r\n> \r\n> > \r\n> > +       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\r\n> > +               CLKMGR_PLLGLOB_VCO_PSRC_MASK;\r\n> > +       switch (fref) {\r\n> > +       case CLKMGR_VCO_PSRC_EOSC1:\r\n> > +               fref = cm_get_osc_clk_hz(0);\r\n> > +               break;\r\n> > +       case CLKMGR_VCO_PSRC_INTOSC:\r\n> > +               fref = cm_get_intosc_clk_hz();\r\n> > +               break;\r\n> > +       case CLKMGR_VCO_PSRC_F2S:\r\n> > +               fref = cm_get_fpga_clk_hz();\r\n> > +               break;\r\n> > +       }\r\n> > +\r\n> > +       /* get the refdiv */\r\n> same..\r\n> \r\n> > \r\n> > +       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\r\n> > +                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;\r\n> > +\r\n> > +       /* get the mdiv */\r\n> same...\r\n> \r\n> > \r\n> > +       reg = readl(&clock_manager_base->main_pll.fdbck);\r\n> > +       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) &\r\n> > CLKMGR_FDBCK_MDIV_MASK;\r\n> > +\r\n> > +       vco = fref / refdiv;\r\n> > +       vco = vco * (6 + mdiv);\r\n> Why 6? Define?\r\n> \r\n> > \r\n> > +       return vco;\r\n> > +}\r\n> > +\r\n> > +static unsigned long cm_get_per_vco_clk_hz(void)\r\n> > +{\r\n> > +       unsigned long fref, refdiv, mdiv, reg, vco;\r\n> > +\r\n> > +       reg = readl(&clock_manager_base->per_pll.pllglob);\r\n> > +\r\n> > +       /* get the fref */\r\n> > +       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\r\n> > +               CLKMGR_PLLGLOB_VCO_PSRC_MASK;\r\n> > +       switch (fref) {\r\n> > +       case CLKMGR_VCO_PSRC_EOSC1:\r\n> > +               fref = cm_get_osc_clk_hz(0);\r\n> > +               break;\r\n> > +       case CLKMGR_VCO_PSRC_INTOSC:\r\n> > +               fref = cm_get_intosc_clk_hz();\r\n> > +               break;\r\n> > +       case CLKMGR_VCO_PSRC_F2S:\r\n> > +               fref = cm_get_fpga_clk_hz();\r\n> > +               break;\r\n> > +       }\r\n> > +\r\n> > +       /* get the refdiv */\r\n> > +       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\r\n> > +                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;\r\n> > +\r\n> > +       /* get the mdiv */\r\n> > +       reg = readl(&clock_manager_base->per_pll.fdbck);\r\n> > +       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) &\r\n> > CLKMGR_FDBCK_MDIV_MASK;\r\n> > +\r\n> > +       vco = fref / refdiv;\r\n> > +       vco = vco * (6 + mdiv);\r\n> > +       return vco;\r\n> > +}\r\n> > +\r\n> > +unsigned long cm_get_mpu_clk_hz(void)\r\n> > +{\r\n> > +       unsigned long clock = readl(&clock_manager_base-\r\n> > >main_pll.mpuclk);\r\n> > +       clock = (clock >> CLKMGR_CLKSRC_OFFSET) &\r\n> > CLKMGR_CLKSRC_MASK;\r\n> > +\r\n> > +       switch (clock) {\r\n> > +       case CLKMGR_CLKSRC_MAIN:\r\n> > +               clock = cm_get_main_vco_clk_hz();\r\n> > +               clock /= (readl(&clock_manager_base-\r\n> > >main_pll.pllc0) &\r\n> > +                         CLKMGR_PLLC0_DIV_MASK);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_PER:\r\n> > +               clock = cm_get_per_vco_clk_hz();\r\n> > +               clock /= (readl(&clock_manager_base->per_pll.pllc0) \r\n> > &\r\n> > +                         CLKMGR_CLKCNT_MSK);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_OSC1:\r\n> > +               clock = cm_get_osc_clk_hz(0);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_INTOSC:\r\n> > +               clock = cm_get_intosc_clk_hz();\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_FPGA:\r\n> > +               clock = cm_get_fpga_clk_hz();\r\n> > +               break;\r\n> > +       }\r\n> > +\r\n> > +       clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &\r\n> > +               CLKMGR_CLKCNT_MSK);\r\n> > +       return clock;\r\n> > +}\r\n> > +\r\n> > +unsigned int cm_get_l3_main_clk_hz(void)\r\n> > +{\r\n> > +       uint32_t clock = readl(&clock_manager_base-\r\n> > >main_pll.nocclk);\r\n> > +       clock = (clock >> CLKMGR_CLKSRC_OFFSET) &\r\n> > CLKMGR_CLKSRC_MASK;\r\n> > +\r\n> > +       switch (clock) {\r\n> > +       case CLKMGR_CLKSRC_MAIN:\r\n> > +               clock = cm_get_main_vco_clk_hz();\r\n> > +               clock /= (readl(&clock_manager_base-\r\n> > >main_pll.pllc1) &\r\n> > +                         CLKMGR_PLLC0_DIV_MASK);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_PER:\r\n> > +               clock = cm_get_per_vco_clk_hz();\r\n> > +               clock /= (readl(&clock_manager_base->per_pll.pllc1) \r\n> > &\r\n> > +                         CLKMGR_CLKCNT_MSK);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_OSC1:\r\n> > +               clock = cm_get_osc_clk_hz(0);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_INTOSC:\r\n> > +               clock = cm_get_intosc_clk_hz();\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_FPGA:\r\n> > +               clock = cm_get_fpga_clk_hz();\r\n> > +               break;\r\n> > +       }\r\n> > +\r\n> > +       clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &\r\n> > +               CLKMGR_CLKCNT_MSK);\r\n> > +       return clock;\r\n> > +}\r\n> > +\r\n> > +unsigned int cm_get_mmc_controller_clk_hz(void)\r\n> > +{\r\n> > +       uint32_t clock = readl(&clock_manager_base-\r\n> > >per_pll.cntr6clk);\r\n> > +       clock = (clock >> CLKMGR_CLKSRC_OFFSET) &\r\n> > CLKMGR_CLKSRC_MASK;\r\n> > +\r\n> > +       switch (clock) {\r\n> > +       case CLKMGR_CLKSRC_MAIN:\r\n> > +               clock = cm_get_l3_main_clk_hz();\r\n> > +               clock /= 1 + (readl(&clock_manager_base-\r\n> > >main_pll.cntr6clk) &\r\n> > +                       CLKMGR_CLKCNT_MSK);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_PER:\r\n> > +               clock = cm_get_l3_main_clk_hz();\r\n> > +               clock /= 1 + (readl(&clock_manager_base-\r\n> > >per_pll.cntr6clk) &\r\n> > +                       CLKMGR_CLKCNT_MSK);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_OSC1:\r\n> > +               clock = cm_get_osc_clk_hz(0);\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_INTOSC:\r\n> > +               clock = cm_get_intosc_clk_hz();\r\n> > +               break;\r\n> > +\r\n> > +       case CLKMGR_CLKSRC_FPGA:\r\n> > +               clock = cm_get_fpga_clk_hz();\r\n> > +               break;\r\n> > +       }\r\n> > +       return clock/4;\r\n> Need space between '/'.\r\n> \r\n> > \r\n> > +}\r\n> > +\r\n> > +unsigned int cm_get_l4_sp_clk_hz(void)\r\n> > +{\r\n> > +       uint32_t clock = cm_get_l3_main_clk_hz();\r\n> > +\r\n> > +       clock /= (1 << ((readl(&clock_manager_base-\r\n> > >main_pll.nocdiv) >>\r\n> > +                 CLKMGR_NOCDIV_L4SPCLK_OFFSET) &\r\n> > CLKMGR_CLKCNT_MSK));\r\n> > +       return clock;\r\n> > +}\r\n> > +\r\n> > +void cm_print_clock_quick_summary(void)\r\n> > +{\r\n> > +       printf(\"MPU         %d kHz\\n\", (u32)(cm_get_mpu_clk_hz() /\r\n> > 1000));\r\n> > +       printf(\"L3 main     %d kHz\\n\", cm_get_l3_main_clk_hz() /\r\n> > 1000);\r\n> > +       printf(\"Main VCO    %d kHz\\n\",\r\n> > (u32)(cm_get_main_vco_clk_hz() / 1000));\r\n> > +       printf(\"Per VCO     %d kHz\\n\",\r\n> > (u32)(cm_get_per_vco_clk_hz() / 1000));\r\n> > +       printf(\"EOSC1       %d kHz\\n\", cm_get_osc_clk_hz(0) /\r\n> > 1000);\r\n> > +       printf(\"HPS MMC     %d kHz\\n\",\r\n> > cm_get_mmc_controller_clk_hz() / 1000);\r\n> > +       printf(\"UART        %d kHz\\n\", cm_get_l4_sp_clk_hz() /\r\n> > 1000);\r\n> > +}\r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h\r\n> > b/arch/arm/mach-socfpga/include/mach/clock_manager.h\r\n> > index 4c6b1f8..ddf814f 100644\r\n> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h\r\n> > @@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);\r\n> >  #include \r\n> >  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)\r\n> >  #include \r\n> > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)\r\n> > +#include \r\n> >  #endif\r\n> > \r\n> >  #endif /* _CLOCK_MANAGER_H_ */\r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h \r\n> > b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\r\n> > new file mode 100644\r\n> > index 0000000..c99ad97\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\r\n> > @@ -0,0 +1,202 @@\r\n> > +/*\r\n> > + * Copyright (C) 2016-2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +#ifndef        _CLOCK_MANAGER_S10_\r\n> > +#define        _CLOCK_MANAGER_S10_\r\n> > +\r\n> > +/* Clock speed accessors */\r\n> > +unsigned long cm_get_mpu_clk_hz(void);\r\n> > +unsigned long cm_get_sdram_clk_hz(void);\r\n> > +unsigned int cm_get_l4_sp_clk_hz(void);\r\n> > +unsigned int cm_get_mmc_controller_clk_hz(void);\r\n> > +unsigned int cm_get_qspi_controller_clk_hz(void);\r\n> > +unsigned int cm_get_spi_controller_clk_hz(void);\r\n> > +const unsigned int cm_get_osc_clk_hz(const int osc);\r\n> > +const unsigned int cm_get_f2s_per_ref_clk_hz(void);\r\n> > +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);\r\n> > +const unsigned int cm_get_intosc_clk_hz(void);\r\n> > +const unsigned int cm_get_fpga_clk_hz(void);\r\n> > +\r\n> > +/* Clock configuration accessors */\r\n> > +const struct cm_config * const cm_get_default_config(void);\r\n> > +\r\n> > +struct cm_config {\r\n> > +       /* main group */\r\n> > +       uint32_t main_pll_mpuclk;\r\n> > +       uint32_t main_pll_nocclk;\r\n> > +       uint32_t main_pll_cntr2clk;\r\n> > +       uint32_t main_pll_cntr3clk;\r\n> > +       uint32_t main_pll_cntr4clk;\r\n> > +       uint32_t main_pll_cntr5clk;\r\n> > +       uint32_t main_pll_cntr6clk;\r\n> > +       uint32_t main_pll_cntr7clk;\r\n> > +       uint32_t main_pll_cntr8clk;\r\n> > +       uint32_t main_pll_cntr9clk;\r\n> > +       uint32_t main_pll_nocdiv;\r\n> > +       uint32_t main_pll_pllglob;\r\n> > +       uint32_t main_pll_fdbck;\r\n> > +       uint32_t main_pll_pllc0;\r\n> > +       uint32_t main_pll_pllc1;\r\n> > +       uint32_t spare;\r\n> > +\r\n> > +       /* peripheral group */\r\n> > +       uint32_t per_pll_cntr2clk;\r\n> > +       uint32_t per_pll_cntr3clk;\r\n> > +       uint32_t per_pll_cntr4clk;\r\n> > +       uint32_t per_pll_cntr5clk;\r\n> > +       uint32_t per_pll_cntr6clk;\r\n> > +       uint32_t per_pll_cntr7clk;\r\n> > +       uint32_t per_pll_cntr8clk;\r\n> > +       uint32_t per_pll_cntr9clk;\r\n> > +       uint32_t per_pll_emacctl;\r\n> > +       uint32_t per_pll_gpiodiv;\r\n> > +       uint32_t per_pll_pllglob;\r\n> > +       uint32_t per_pll_fdbck;\r\n> > +       uint32_t per_pll_pllc0;\r\n> > +       uint32_t per_pll_pllc1;\r\n> > +\r\n> > +       /* incoming clock */\r\n> > +       uint32_t hps_osc_clk_hz;\r\n> > +       uint32_t fpga_clk_hz;\r\n> > +};\r\n> > +\r\n> > +void cm_basic_init(const struct cm_config * const cfg);\r\n> > +\r\n> > +struct socfpga_clock_manager_main_pll {\r\n> > +       u32     en;\r\n> > +       u32     ens;\r\n> > +       u32     enr;\r\n> > +       u32     bypass;\r\n> > +       u32     bypasss;\r\n> > +       u32     bypassr;\r\n> > +       u32     mpuclk;\r\n> > +       u32     nocclk;\r\n> > +       u32     cntr2clk;\r\n> > +       u32     cntr3clk;\r\n> > +       u32     cntr4clk;\r\n> > +       u32     cntr5clk;\r\n> > +       u32     cntr6clk;\r\n> > +       u32     cntr7clk;\r\n> > +       u32     cntr8clk;\r\n> > +       u32     cntr9clk;\r\n> > +       u32     nocdiv;\r\n> > +       u32     pllglob;\r\n> > +       u32     fdbck;\r\n> > +       u32     mem;\r\n> > +       u32     memstat;\r\n> > +       u32     pllc0;\r\n> > +       u32     pllc1;\r\n> > +       u32     vcocalib;\r\n> > +       u32     _pad_0x90_0xA0[5];\r\n> > +};\r\n> > +\r\n> > +struct socfpga_clock_manager_per_pll {\r\n> > +       u32     en;\r\n> > +       u32     ens;\r\n> > +       u32     enr;\r\n> > +       u32     bypass;\r\n> > +       u32     bypasss;\r\n> > +       u32     bypassr;\r\n> > +       u32     cntr2clk;\r\n> > +       u32     cntr3clk;\r\n> > +       u32     cntr4clk;\r\n> > +       u32     cntr5clk;\r\n> > +       u32     cntr6clk;\r\n> > +       u32     cntr7clk;\r\n> > +       u32     cntr8clk;\r\n> > +       u32     cntr9clk;\r\n> > +       u32     emacctl;\r\n> > +       u32     gpiodiv;\r\n> > +       u32     pllglob;\r\n> > +       u32     fdbck;\r\n> > +       u32     mem;\r\n> > +       u32     memstat;\r\n> > +       u32     pllc0;\r\n> > +       u32     pllc1;\r\n> > +       u32     vcocalib;\r\n> > +       u32     _pad_0x100_0x124[10];\r\n> > +};\r\n> > +\r\n> > +struct socfpga_clock_manager {\r\n> > +       u32     ctrl;\r\n> > +       u32     stat;\r\n> > +       u32     testioctrl;\r\n> > +       u32     intrgen;\r\n> > +       u32     intrmsk;\r\n> > +       u32     intrclr;\r\n> > +       u32     intrsts;\r\n> > +       u32     intrstk;\r\n> > +       u32     intrraw;\r\n> > +       u32     _pad_0x24_0x2c[3];\r\n> > +       struct socfpga_clock_manager_main_pll main_pll;\r\n> > +       struct socfpga_clock_manager_per_pll per_pll;\r\n> > +};\r\n> > +\r\n> > +#define CLKMGR_CTRL_SAFEMODE                           (1 << 0)\r\n> > +#define CLKMGR_BYPASS_MAINPLL_ALL                      0x00000007\r\n> > +#define CLKMGR_BYPASS_PERPLL_ALL                       0x0000007f\r\n> > +\r\n> > +#define\r\n> > CLKMGR_INTER_MAINPLLLOCKED_MASK                        0x00000001\r\n> > +#define CLKMGR_INTER_PERPLLLOCKED_MASK                 0x00000002\r\n> > +#define CLKMGR_INTER_MAINPLLLOST_MASK                  0x00000004\r\n> > +#define CLKMGR_INTER_PERPLLLOST_MASK                   0x00000008\r\n> > +#define CLKMGR_STAT_BUSY                               (1 << 0)\r\n> > +#define CLKMGR_STAT_MAINPLL_LOCKED                     (1 << 8)\r\n> > +#define CLKMGR_STAT_PERPLL_LOCKED                      (1 << 9)\r\n> > +\r\n> > +#define CLKMGR_PLLGLOB_PD_MASK                         0x00000001\r\n> > +#define\r\n> > CLKMGR_PLLGLOB_RST_MASK                                0x00000002\r\n> > +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK                   0X3\r\n> > +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET                 16\r\n> > +#define CLKMGR_VCO_PSRC_EOSC1                          0\r\n> > +#define CLKMGR_VCO_PSRC_INTOSC                         1\r\n> > +#define CLKMGR_VCO_PSRC_F2S                            2\r\n> > +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK                  0X3f\r\n> > +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET                        8\r\n> > +\r\n> > +#define CLKMGR_CLKSRC_MASK                             0x7\r\n> > +#define CLKMGR_CLKSRC_OFFSET                           16\r\n> > +#define CLKMGR_CLKSRC_MAIN                             0\r\n> > +#define CLKMGR_CLKSRC_PER                              1\r\n> > +#define CLKMGR_CLKSRC_OSC1                             2\r\n> > +#define CLKMGR_CLKSRC_INTOSC                           3\r\n> > +#define CLKMGR_CLKSRC_FPGA                             4\r\n> > +#define CLKMGR_CLKCNT_MSK                              0x7ff\r\n> > +\r\n> > +#define CLKMGR_FDBCK_MDIV_MASK                         0xff\r\n> > +#define CLKMGR_FDBCK_MDIV_OFFSET                       24\r\n> > +\r\n> > +#define CLKMGR_PLLC0_DIV_MASK                          0xff\r\n> > +#define CLKMGR_PLLC1_DIV_MASK                          0xff\r\n> > +#define CLKMGR_PLLC0_EN_OFFSET                         27\r\n> > +#define CLKMGR_PLLC1_EN_OFFSET                         24\r\n> > +\r\n> > +#define CLKMGR_NOCDIV_L4MAIN_OFFSET                    0\r\n> > +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET                   8\r\n> > +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET                   16\r\n> > +#define CLKMGR_NOCDIV_CSATCLK_OFFSET                   24\r\n> > +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET                        26\r\n> > +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET                 28\r\n> > +\r\n> > +#define CLKMGR_NOCDIV_L4SPCLK_MASK                     0X3\r\n> > +#define CLKMGR_NOCDIV_DIV1                             0\r\n> > +#define CLKMGR_NOCDIV_DIV2                             1\r\n> > +#define CLKMGR_NOCDIV_DIV4                             2\r\n> > +#define CLKMGR_NOCDIV_DIV8                             3\r\n> > +#define CLKMGR_CSPDBGCLK_DIV1                          0\r\n> > +#define CLKMGR_CSPDBGCLK_DIV4                          1\r\n> > +\r\n> > +#define CLKMGR_VCOCALIB_MSCNT_MASK                     0xff\r\n> > +#define CLKMGR_VCOCALIB_MSCNT_OFFSET                   9\r\n> > +#define CLKMGR_VCOCALIB_HSCNT_MASK                     0xff\r\n> > +\r\n> > +#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET                 26\r\n> > +#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET                 27\r\n> > +#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET                 28\r\n> > +\r\n> > +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK              0x00000020\r\n> > +\r\n> > +#endif /* _CLOCK_MANAGER_S10_ */\r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h\r\n> > b/arch/arm/mach-socfpga/include/mach/handoff_s10.h\r\n> > new file mode 100644\r\n> > index 0000000..d4b89ac\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h\r\n> > @@ -0,0 +1,29 @@\r\n> > +/*\r\n> > + *  Copyright (C) 2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +#ifndef _HANDOFF_S10_H_\r\n> > +#define _HANDOFF_S10_H_\r\n> > +\r\n> > +/*\r\n> > + * Offset for HW handoff from Quartus tools\r\n> > + */\r\n> > +#define CONFIG_HANDOFF_BASE            0xFFE3F000\r\n> > +#define CONFIG_HANDOFF_MUX             (CONFIG_HANDOFF_BASE +\r\n> > 0x10)\r\n> > +#define CONFIG_HANDOFF_IOCTL           (CONFIG_HANDOFF_BASE +\r\n> > 0x1A0)\r\n> > +#define CONFIG_HANDOFF_FPGA            (CONFIG_HANDOFF_BASE +\r\n> > 0x330)\r\n> > +#define CONFIG_HANODFF_DELAY           (CONFIG_HANDOFF_BASE +\r\n> > 0x3F0)\r\n> > +#define CONFIG_HANDOFF_CLOCK           (CONFIG_HANDOFF_BASE +\r\n> > 0x580)\r\n> > +#define CONFIG_HANDOFF_MISC            (CONFIG_HANDOFF_BASE +\r\n> > 0x610)\r\n> > +#define CONFIG_HANDOFF_MAGIC_MUX       0x504D5558\r\n> > +#define CONFIG_HANDOFF_MAGIC_IOCTL     0x494F4354\r\n> > +#define CONFIG_HANDOFF_MAGIC_FPGA      0x46504741\r\n> > +#define CONFIG_HANDOFF_MAGIC_DELAY     0x444C4159\r\n> > +#define CONFIG_HANDOFF_MAGIC_CLOCK     0x434C4B53\r\n> > +#define CONFIG_HANDOFF_MAGIC_MISC      0x4D495343\r\n> > +#define CONFIG_HANDOFF_OFFSET_LENGTH   0x4\r\n> > +#define CONFIG_HANDOFF_OFFSET_DATA     0x10\r\n> > +\r\n> > +#endif /* _HANDOFF_S10_H_ */\r\n> > diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c\r\n> > b/arch/arm/mach-socfpga/wrap_pll_config_s10.c\r\n> > new file mode 100644\r\n> > index 0000000..2a624d5\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c\r\n> > @@ -0,0 +1,46 @@\r\n> > +/*\r\n> > + * Copyright (C) 2016-2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +#include \r\n> > +\r\n> > +const struct cm_config * const cm_get_default_config(void)\r\n> > +{\r\n> > +       struct cm_config *cm_handoff_cfg = (struct cm_config *)\r\n> > +               (CONFIG_HANDOFF_CLOCK +\r\n> > CONFIG_HANDOFF_OFFSET_DATA);\r\n> > +       u32 *conversion = (u32 *)cm_handoff_cfg;\r\n> > +       u32 i;\r\n> > +\r\n> > +       if (swab32(readl(CONFIG_HANDOFF_CLOCK)) ==\r\n> > CONFIG_HANDOFF_MAGIC_CLOCK) {\r\n> > +               writel(swab32(readl(CONFIG_HANDOFF_CLOCK)),\r\n> > +                       CONFIG_HANDOFF_CLOCK);\r\n> > +               for (i = 0; i < (sizeof(*cm_handoff_cfg) /\r\n> > sizeof(u32)); i++)\r\n> > +                       conversion[i] = swab32(conversion[i]);\r\n> > +               return cm_handoff_cfg;\r\n> > +       } else if (readl(CONFIG_HANDOFF_CLOCK) ==\r\n> > CONFIG_HANDOFF_MAGIC_CLOCK) {\r\n> > +               return cm_handoff_cfg;\r\n> > +       } else\r\n> > +               return 0;\r\n> > +}\r\n> > +\r\n> > +const unsigned int cm_get_osc_clk_hz(const int osc)\r\n> > +{\r\n> > +       return 25000000;\r\n> Needs to be a #define\r\n> \r\n> > \r\n> > +}\r\n> > +\r\n> > +const unsigned int cm_get_intosc_clk_hz(void)\r\n> > +{\r\n> > +       /* theory maximum internal osc clock */\r\n> > +       return 460000000;\r\n> Same...\r\n> \r\n> > \r\n> > +}\r\n> > +\r\n> > +const unsigned int cm_get_fpga_clk_hz(void)\r\n> > +{\r\n> > +       /* assuming 50MHz */\r\n> > +       return 50000000;\r\n> Same..\r\n> \r\n> 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