[{"id":1775873,"web_url":"http://patchwork.ozlabs.org/comment/1775873/","msgid":"","list_archive_url":null,"date":"2017-09-26T21:34:29","subject":"Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","submitter":{"id":16347,"url":"http://patchwork.ozlabs.org/api/people/16347/","name":"Dinh Nguyen","email":"dinh.linux@gmail.com"},"content":"On Tue, Sep 19, 2017 at 4:22 AM, wrote:\n> From: Chin Liang See \n>\n> Device tree for Stratix10 SoC\n>\n> Signed-off-by: Chin Liang See \n> ---\n> arch/arm/dts/Makefile | 3 +-\n> arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++++++++++++++++++++++++++++++\n> 2 files changed, 143 insertions(+), 1 deletion(-)\n> create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts\n>\n> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\n> index fee4680..4cf5fd0 100644\n> --- a/arch/arm/dts/Makefile\n> +++ b/arch/arm/dts/Makefile\n> @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \\\n> socfpga_cyclone5_sockit.dtb \\\n> socfpga_cyclone5_socrates.dtb \\\n> socfpga_cyclone5_sr1500.dtb \\\n> - socfpga_cyclone5_vining_fpga.dtb\n> + socfpga_cyclone5_vining_fpga.dtb \\\n> + socfpga_stratix10_socdk.dtb\n>\n> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \\\n> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb\n> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts\n> new file mode 100644\n> index 0000000..484c630\n> --- /dev/null\n> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts\n> @@ -0,0 +1,141 @@\n> +/*\n> + * Copyright (C) 2016-2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +/dts-v1/;\n> +#include \"skeleton.dtsi\"\n> +#include \n\nYou don't add the patch for this include file until patch 4/14, which means\nthe build will fail until patch 4 is applied. You need to move this patch\nafter 4/14.\n\n> +\n> +/ {\n> + model = \"Intel SOCFPGA Stratix 10 SoC Development Kit\";\n> + compatible = \"altr,socfpga-stratix10\", \"altr,socfpga\";\n> +\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> +\n> + chosen {\n> + bootargs = \"console=ttyS0,115200\";\n> + };\n> +\n> + aliases {\n> + ethernet0 = &gmac0;\n> + spi0 = &qspi;\n> + };\n> +\n> + memory {\n> + name = \"memory\";\n> + device_type = \"memory\";\n> + reg = <0x0 0x80000000>; /* 2GB */\n> + };\n> +\n> + regulator_3_3v: 3-3-v-regulator {\n> + compatible = \"regulator-fixed\";\n> + regulator-name = \"3.3V\";\n> + regulator-min-microvolt = <3300000>;\n> + regulator-max-microvolt = <3300000>;\n> + };\n> +\n> + soc {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + compatible = \"simple-bus\";\n> + device_type = \"soc\";\n> + ranges;\n> + u-boot,dm-pre-reloc;\n> +\n> + rst: rstmgr@ffd11000 {\n> + #reset-cells = <1>;\n> + compatible = \"altr,rst-mgr\";\n> + reg = <0xffd11000 0x100>;\n> + altr,modrst-offset = <0x20>;\n> + };\n> +\n> + gmac0: ethernet@ff800000 {\n> + compatible = \"altr,socfpga-stmmac\", \"snps,dwmac-3.74a\", \"snps,dwmac\";\n> + reg = <0xff800000 0x2000>;\n> + interrupts = <0 90 4>;\n> + interrupt-names = \"macirq\";\n> + mac-address = [00 00 00 00 00 00];\n> + resets = <&rst EMAC0_RESET>;\n> + reset-names = \"stmmaceth\";\n> + phy-mode = \"rgmii\";\n> + phy-addr = <0xffffffff>; /* probe for phy addr */\n> + max-speed = <1000>;\n> + txd0-skew-ps = <0>; /* -420ps */\n> + txd1-skew-ps = <0>; /* -420ps */\n> + txd2-skew-ps = <0>; /* -420ps */\n> + txd3-skew-ps = <0>; /* -420ps */\n> + rxd0-skew-ps = <420>; /* 0ps */\n> + rxd1-skew-ps = <420>; /* 0ps */\n> + rxd2-skew-ps = <420>; /* 0ps */\n> + rxd3-skew-ps = <420>; /* 0ps */\n> + txen-skew-ps = <0>; /* -420ps */\n> + txc-skew-ps = <1860>; /* 960ps */\n> + rxdv-skew-ps = <420>; /* 0ps */\n> + rxc-skew-ps = <1680>; /* 780ps */\n\nThese are PHY properties, which should be in a separate PHY node.\n\nDinh","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"lurZ9LrP\"; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775878,"web_url":"http://patchwork.ozlabs.org/comment/1775878/","msgid":"","list_archive_url":null,"date":"2017-09-26T21:37:47","subject":"Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","submitter":{"id":16347,"url":"http://patchwork.ozlabs.org/api/people/16347/","name":"Dinh Nguyen","email":"dinh.linux@gmail.com"},"content":"On Tue, Sep 19, 2017 at 4:22 AM, wrote:\n> From: Chin Liang See \n>\n> Device tree for Stratix10 SoC\n>\n> Signed-off-by: Chin Liang See \n> ---\n> arch/arm/dts/Makefile | 3 +-\n> arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++++++++++++++++++++++++++++++\n> 2 files changed, 143 insertions(+), 1 deletion(-)\n> create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts\n>\n> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\n> index fee4680..4cf5fd0 100644\n> --- a/arch/arm/dts/Makefile\n> +++ b/arch/arm/dts/Makefile\n> @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \\\n> socfpga_cyclone5_sockit.dtb \\\n> socfpga_cyclone5_socrates.dtb \\\n> socfpga_cyclone5_sr1500.dtb \\\n> - socfpga_cyclone5_vining_fpga.dtb\n> + socfpga_cyclone5_vining_fpga.dtb \\\n> + socfpga_stratix10_socdk.dtb\n>\n> dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \\\n> dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb\n> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts\n> new file mode 100644\n> index 0000000..484c630\n> --- /dev/null\n> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts\n> @@ -0,0 +1,141 @@\n> +/*\n> + * Copyright (C) 2016-2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +/dts-v1/;\n> +#include \"skeleton.dtsi\"\n> +#include \n> +\n> +/ {\n> + model = \"Intel SOCFPGA Stratix 10 SoC Development Kit\";\n> + compatible = \"altr,socfpga-stratix10\", \"altr,socfpga\";\n> +\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> +\n> + chosen {\n> + bootargs = \"console=ttyS0,115200\";\n> + };\n> +\n> + aliases {\n> + ethernet0 = &gmac0;\n> + spi0 = &qspi;\n> + };\n> +\n> + memory {\n> + name = \"memory\";\n> + device_type = \"memory\";\n> + reg = <0x0 0x80000000>; /* 2GB */\n> + };\n> +\n> + regulator_3_3v: 3-3-v-regulator {\n> + compatible = \"regulator-fixed\";\n> + regulator-name = \"3.3V\";\n> + regulator-min-microvolt = <3300000>;\n> + regulator-max-microvolt = <3300000>;\n> + };\n> +\n> + soc {\n> + #address-cells = <1>;\n> + #size-cells = <1>;\n> + compatible = \"simple-bus\";\n> + device_type = \"soc\";\n> + ranges;\n> + u-boot,dm-pre-reloc;\n> +\n> + rst: rstmgr@ffd11000 {\n> + #reset-cells = <1>;\n> + compatible = \"altr,rst-mgr\";\n> + reg = <0xffd11000 0x100>;\n> + altr,modrst-offset = <0x20>;\n> + };\n\nWhere are the cpu nodes?\n\nDinh","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KLJaGAQS\"; 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\n\tTue, 26 Sep 2017 14:37:48 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1505812951-25088-3-git-send-email-chin.liang.see@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>\n\t<1505812951-25088-3-git-send-email-chin.liang.see@intel.com>","From":"Dinh Nguyen ","Date":"Tue, 26 Sep 2017 16:37:47 -0500","Message-ID":"","To":"Chin Liang See ","Cc":"Marek Vasut , ZY - u-boot ,\n\tTien Fong Chee ","Subject":"Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777541,"web_url":"http://patchwork.ozlabs.org/comment/1777541/","msgid":"<1506776839.2766.8.camel@intel.com>","list_archive_url":null,"date":"2017-09-29T13:06:32","subject":"Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"content":"On Tue, 2017-09-26 at 16:34 -0500, Dinh Nguyen wrote:\r\n> On Tue, Sep 19, 2017 at 4:22 AM,   wrote:\r\n> > \r\n> > From: Chin Liang See \r\n> > \r\n> > Device tree for Stratix10 SoC\r\n> > \r\n> > Signed-off-by: Chin Liang See \r\n> > ---\r\n> >  arch/arm/dts/Makefile                    |   3 +-\r\n> >  arch/arm/dts/socfpga_stratix10_socdk.dts | 141\r\n> > +++++++++++++++++++++++++++++++\r\n> >  2 files changed, 143 insertions(+), 1 deletion(-)\r\n> >  create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > \r\n> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\r\n> > index fee4680..4cf5fd0 100644\r\n> > --- a/arch/arm/dts/Makefile\r\n> > +++ b/arch/arm/dts/Makefile\r\n> > @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA)\r\n> > +=                               \\\r\n> >         socfpga_cyclone5_sockit.dtb                     \\\r\n> >         socfpga_cyclone5_socrates.dtb                   \\\r\n> >         socfpga_cyclone5_sr1500.dtb                     \\\r\n> > -       socfpga_cyclone5_vining_fpga.dtb\r\n> > +       socfpga_cyclone5_vining_fpga.dtb                \\\r\n> > +       socfpga_stratix10_socdk.dtb\r\n> > \r\n> >  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \\\r\n> >         dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb\r\n> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > b/arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > new file mode 100644\r\n> > index 0000000..484c630\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > @@ -0,0 +1,141 @@\r\n> > +/*\r\n> > + * Copyright (C) 2016-2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +/dts-v1/;\r\n> > +#include \"skeleton.dtsi\"\r\n> > +#include \r\n> You don't add the patch for this include file until patch 4/14, which\r\n> means\r\n> the build will fail until patch 4 is applied. You need to move this\r\n> patch\r\n> after 4/14.\r\n\r\nYes, good catch. Let shuffle this\r\n\r\n> \r\n> > \r\n> > +\r\n> > +/ {\r\n> > +       model = \"Intel SOCFPGA Stratix 10 SoC Development Kit\";\r\n> > +       compatible = \"altr,socfpga-stratix10\", \"altr,socfpga\";\r\n> > +\r\n> > +       #address-cells = <1>;\r\n> > +       #size-cells = <1>;\r\n> > +\r\n> > +       chosen {\r\n> > +               bootargs = \"console=ttyS0,115200\";\r\n> > +       };\r\n> > +\r\n> > +       aliases {\r\n> > +               ethernet0 = &gmac0;\r\n> > +               spi0 = &qspi;\r\n> > +       };\r\n> > +\r\n> > +       memory {\r\n> > +               name = \"memory\";\r\n> > +               device_type = \"memory\";\r\n> > +               reg = <0x0 0x80000000>; /* 2GB */\r\n> > +       };\r\n> > +\r\n> > +       regulator_3_3v: 3-3-v-regulator {\r\n> > +               compatible = \"regulator-fixed\";\r\n> > +               regulator-name = \"3.3V\";\r\n> > +               regulator-min-microvolt = <3300000>;\r\n> > +               regulator-max-microvolt = <3300000>;\r\n> > +       };\r\n> > +\r\n> > +       soc {\r\n> > +               #address-cells = <1>;\r\n> > +               #size-cells = <1>;\r\n> > +               compatible = \"simple-bus\";\r\n> > +               device_type = \"soc\";\r\n> > +               ranges;\r\n> > +               u-boot,dm-pre-reloc;\r\n> > +\r\n> > +               rst: rstmgr@ffd11000 {\r\n> > +                       #reset-cells = <1>;\r\n> > +                       compatible = \"altr,rst-mgr\";\r\n> > +                       reg = <0xffd11000 0x100>;\r\n> > +                       altr,modrst-offset = <0x20>;\r\n> > +               };\r\n> > +\r\n> > +               gmac0: ethernet@ff800000 {\r\n> > +                       compatible = \"altr,socfpga-stmmac\",\r\n> > \"snps,dwmac-3.74a\", \"snps,dwmac\";\r\n> > +                       reg = <0xff800000 0x2000>;\r\n> > +                       interrupts = <0 90 4>;\r\n> > +                       interrupt-names = \"macirq\";\r\n> > +                       mac-address = [00 00 00 00 00 00];\r\n> > +                       resets = <&rst EMAC0_RESET>;\r\n> > +                       reset-names = \"stmmaceth\";\r\n> > +                       phy-mode = \"rgmii\";\r\n> > +                       phy-addr = <0xffffffff>; /* probe for phy\r\n> > addr */\r\n> > +                       max-speed = <1000>;\r\n> > +                       txd0-skew-ps = <0>; /* -420ps */\r\n> > +                       txd1-skew-ps = <0>; /* -420ps */\r\n> > +                       txd2-skew-ps = <0>; /* -420ps */\r\n> > +                       txd3-skew-ps = <0>; /* -420ps */\r\n> > +                       rxd0-skew-ps = <420>; /* 0ps */\r\n> > +                       rxd1-skew-ps = <420>; /* 0ps */\r\n> > +                       rxd2-skew-ps = <420>; /* 0ps */\r\n> > +                       rxd3-skew-ps = <420>; /* 0ps */\r\n> > +                       txen-skew-ps = <0>; /* -420ps */\r\n> > +                       txc-skew-ps = <1860>; /* 960ps */\r\n> > +                       rxdv-skew-ps = <420>; /* 0ps */\r\n> > +                       rxc-skew-ps = <1680>; /* 780ps */\r\n> These are PHY properties, which should be in a separate PHY node.\r\n\r\nLet me check on the PHY driver\r\n\r\nChin Liang\r\n\r\n> \r\n> Dinh","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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29 Sep 2017 06:06:35 -0700","from pgsmsx109.gar.corp.intel.com ([169.254.14.159]) by\n\tPGSMSX104.gar.corp.intel.com ([169.254.3.223]) with mapi id\n\t14.03.0319.002; Fri, 29 Sep 2017 21:06:33 +0800"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.42,452,1500966000\"; d=\"scan'208\";\n\ta=\"1019822081\"","From":"\"See, Chin Liang\" ","To":"\"dinh.linux@gmail.com\" ","Thread-Topic":"[U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","Thread-Index":"AQHTMSkSN4lSrYT9+0iAi8WHkua09aLHNgmAgAW7n4A=","Date":"Fri, 29 Sep 2017 13:06:32 +0000","Message-ID":"<1506776839.2766.8.camel@intel.com>","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>\n\t<1505812951-25088-3-git-send-email-chin.liang.see@intel.com>\n\t","In-Reply-To":"","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[172.30.190.99]","Content-ID":"<96E15F3F05520F49B8DD039BE4A7BFD4@intel.com>","MIME-Version":"1.0","Cc":"\"marex@denx.de\" ,\n\t\"u-boot@lists.denx.de\" , \"Chee,\n\tTien Fong\" ","Subject":"Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777555,"web_url":"http://patchwork.ozlabs.org/comment/1777555/","msgid":"<1506776869.2766.9.camel@intel.com>","list_archive_url":null,"date":"2017-09-29T13:07:00","subject":"Re: [U-Boot] [PATCH 02/14] arm: dts: Add dts for Stratix10 SoC","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"content":"On Tue, 2017-09-26 at 16:37 -0500, Dinh Nguyen wrote:\r\n> On Tue, Sep 19, 2017 at 4:22 AM,   wrote:\r\n> > \r\n> > From: Chin Liang See \r\n> > \r\n> > Device tree for Stratix10 SoC\r\n> > \r\n> > Signed-off-by: Chin Liang See \r\n> > ---\r\n> >  arch/arm/dts/Makefile                    |   3 +-\r\n> >  arch/arm/dts/socfpga_stratix10_socdk.dts | 141\r\n> > +++++++++++++++++++++++++++++++\r\n> >  2 files changed, 143 insertions(+), 1 deletion(-)\r\n> >  create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > \r\n> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\r\n> > index fee4680..4cf5fd0 100644\r\n> > --- a/arch/arm/dts/Makefile\r\n> > +++ b/arch/arm/dts/Makefile\r\n> > @@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA)\r\n> > +=                               \\\r\n> >         socfpga_cyclone5_sockit.dtb                     \\\r\n> >         socfpga_cyclone5_socrates.dtb                   \\\r\n> >         socfpga_cyclone5_sr1500.dtb                     \\\r\n> > -       socfpga_cyclone5_vining_fpga.dtb\r\n> > +       socfpga_cyclone5_vining_fpga.dtb                \\\r\n> > +       socfpga_stratix10_socdk.dtb\r\n> > \r\n> >  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \\\r\n> >         dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb\r\n> > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > b/arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > new file mode 100644\r\n> > index 0000000..484c630\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts\r\n> > @@ -0,0 +1,141 @@\r\n> > +/*\r\n> > + * Copyright (C) 2016-2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:    GPL-2.0\r\n> > + */\r\n> > +\r\n> > +/dts-v1/;\r\n> > +#include \"skeleton.dtsi\"\r\n> > +#include \r\n> > +\r\n> > +/ {\r\n> > +       model = \"Intel SOCFPGA Stratix 10 SoC Development Kit\";\r\n> > +       compatible = \"altr,socfpga-stratix10\", \"altr,socfpga\";\r\n> > +\r\n> > +       #address-cells = <1>;\r\n> > +       #size-cells = <1>;\r\n> > +\r\n> > +       chosen {\r\n> > +               bootargs = \"console=ttyS0,115200\";\r\n> > +       };\r\n> > +\r\n> > +       aliases {\r\n> > +               ethernet0 = &gmac0;\r\n> > +               spi0 = &qspi;\r\n> > +       };\r\n> > +\r\n> > +       memory {\r\n> > +               name = \"memory\";\r\n> > +               device_type = \"memory\";\r\n> > +               reg = <0x0 0x80000000>; /* 2GB */\r\n> > +       };\r\n> > +\r\n> > +       regulator_3_3v: 3-3-v-regulator {\r\n> > +               compatible = \"regulator-fixed\";\r\n> > +               regulator-name = \"3.3V\";\r\n> > +               regulator-min-microvolt = <3300000>;\r\n> > +               regulator-max-microvolt = <3300000>;\r\n> > +       };\r\n> > +\r\n> > +       soc {\r\n> > +               #address-cells = <1>;\r\n> > +               #size-cells = <1>;\r\n> > +               compatible = \"simple-bus\";\r\n> > +               device_type = \"soc\";\r\n> > +               ranges;\r\n> > +               u-boot,dm-pre-reloc;\r\n> > +\r\n> > +               rst: rstmgr@ffd11000 {\r\n> > +                       #reset-cells = <1>;\r\n> > +                       compatible = \"altr,rst-mgr\";\r\n> > +                       reg = <0xffd11000 0x100>;\r\n> > +                       altr,modrst-offset = <0x20>;\r\n> > +               };\r\n> Where are the cpu nodes?\r\n\r\nyes, need to be added\r\n\r\nCHin Liang\r\n> \r\n> Dinh","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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