[{"id":1771764,"web_url":"http://patchwork.ozlabs.org/comment/1771764/","msgid":"<20170920113321.GA32496@localhost.localdomain>","list_archive_url":null,"date":"2017-09-20T11:33:21","subject":"Re: [PATCH v4] PCI: quirks: update Cavium ThunderX ACS quirk\n\timplementation","submitter":{"id":70764,"url":"http://patchwork.ozlabs.org/api/people/70764/","name":"Vadim Lomovtsev","email":"Vadim.Lomovtsev@caviumnetworks.com"},"content":"Hi guys,\n\nSorry for annoying topic ..\nCould you please provide your comments/objections on this if any ?\n\nWBR,\nVadim\n\nOn Mon, Sep 18, 2017 at 01:48:01AM -0700, Vadim Lomovtsev wrote:\n> This commit makes Cavium PCI ACS quirk applicable only to Cavium\n> ThunderX (CN81/83/88XX) PCIE Root Ports which has limited PCI capabilities\n> in terms of no ACS support advertisement. However, the RTL internally\n> implements similar protection as if ACS had completion/request redirection,\n> upstream forwarding and validation features enabled.\n> \n> Current quirk implementation doesn't take into account PCIERCs which\n> also needs to be quirked. So the pci device id check mask is updated\n> and check of device ID moved into separate function.\n> \n> Signed-off-by: Vadim Lomovtsev \n> ---\n> \tv1\t: put device check into separate function and extend it to all\n> \t\t Cavium PCIERC/PCCBR devices;\n> \tv1 -> v2: update match function in order to filter only ThunderX devices by device\n> \t \t ids to properly filter CN8XXX devices, update subject & description with\n> \t\t ACS register info (rejected by maillist due to triple X in subject);\n> \tv2 -> v3: update subject: remove CN8XXX from subject line, replace it with ThunderX;\n> \tv3 -> v4: update ACS mask (remove TB and TD bits), update commit message (remove\n> \t \t ACS register printout);\n> \n> drivers/pci/quirks.c | 26 ++++++++++++++++----------\n> 1 file changed, 16 insertions(+), 10 deletions(-)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index a4d3361..e6b904a 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -4211,20 +4211,26 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)\n> #endif\n> }\n> \n> -static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)\n> +/*\n> + * Cavium devices matching this quirk do not perform peer-to-peer\n> + * with other functions, allowing masking out these bits as if they\n> + * were unimplemented in the ACS capability.\n> + */\n> +#define CAVIUM_CN8XXX_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF)\n> +\n> +static __inline__ bool pci_quirk_cavium_acs_match(struct pci_dev *dev)\n> {\n> -\t/*\n> -\t * Cavium devices matching this quirk do not perform peer-to-peer\n> -\t * with other functions, allowing masking out these bits as if they\n> -\t * were unimplemented in the ACS capability.\n> -\t */\n> -\tacs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |\n> -\t\t PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);\n> +\treturn (pci_is_pcie(dev) &&\n> +\t\t(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&\n> +\t\t((dev->device & 0xf800) == 0xa000));\n> +}\n> \n> -\tif (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))\n> +static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)\n> +{\n> +\tif (!pci_quirk_cavium_acs_match(dev))\n> \t\treturn -ENOTTY;\n> \n> -\treturn acs_flags ? 0 : 1;\n> +\treturn acs_flags & ~(CAVIUM_CN8XXX_ACS_FLAGS) ? 0 : 1;\n> }\n> \n> static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)\n> -- \n> 2.9.5\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Wed, 20 Sep 2017 11:33:25 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=oKP/OExHpkGjW47jy3af268XgpWE+acvn2zMCT7/sG8=;\n\tb=LPLAyVutiFVQZc4WouAOBcYM/fY4FuDMd67ggtZTDfeW50tQf+l1IB6ZktgHWF23oK3MjAL3l55jpwppj6toV+4Cg8VpjIqxuaRuEopXAAH1/AvTueZ8wsyu3JxOLSHmP32n3Q+AuP+2BWojzQeRZYcQoZ/o7xH8MEMglXWvZH8=","Date":"Wed, 20 Sep 2017 04:33:21 -0700","From":"Vadim Lomovtsev ","To":"bhelgaas@google.com, linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, alex.williamson@redhat.com","Cc":"Wilson.Snyder@cavium.com, Vadim.Lomovtsev@cavium.com","Subject":"Re: [PATCH v4] PCI: quirks: update Cavium ThunderX ACS quirk\n\timplementation","Message-ID":"<20170920113321.GA32496@localhost.localdomain>","References":"<1505480233-22694-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>\n\t<1505724481-28413-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>","MIME-Version":"1.0","Content-Type":"text/plain; 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SFP:1101; SCL:1; SRVR:MWHPR07MB3008;\n\tH:localhost.localdomain; FPR:; SPF:None; PTR:InfoNoRecords;\n\tA:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"caviumnetworks.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"20 Sep 2017 11:33:25.9798\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"711e4ccf-2e9b-4bcf-a551-4094005b6194","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MWHPR07MB3008","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1772045,"web_url":"http://patchwork.ozlabs.org/comment/1772045/","msgid":"<20170920103151.7e3fdb77@w520.home>","list_archive_url":null,"date":"2017-09-20T16:31:51","subject":"Re: [PATCH v4] PCI: quirks: update Cavium ThunderX ACS quirk\n\timplementation","submitter":{"id":4123,"url":"http://patchwork.ozlabs.org/api/people/4123/","name":"Alex Williamson","email":"alex.williamson@redhat.com"},"content":"On Mon, 18 Sep 2017 01:48:01 -0700\nVadim Lomovtsev wrote:\n\n> This commit makes Cavium PCI ACS quirk applicable only to Cavium\n> ThunderX (CN81/83/88XX) PCIE Root Ports which has limited PCI capabilities\n> in terms of no ACS support advertisement. However, the RTL internally\n> implements similar protection as if ACS had completion/request redirection,\n> upstream forwarding and validation features enabled.\n> \n> Current quirk implementation doesn't take into account PCIERCs which\n> also needs to be quirked. So the pci device id check mask is updated\n> and check of device ID moved into separate function.\n> \n> Signed-off-by: Vadim Lomovtsev \n> ---\n> \tv1\t: put device check into separate function and extend it to all\n> \t\t Cavium PCIERC/PCCBR devices;\n> \tv1 -> v2: update match function in order to filter only ThunderX devices by device\n> \t \t ids to properly filter CN8XXX devices, update subject & description with\n> \t\t ACS register info (rejected by maillist due to triple X in subject);\n> \tv2 -> v3: update subject: remove CN8XXX from subject line, replace it with ThunderX;\n> \tv3 -> v4: update ACS mask (remove TB and TD bits), update commit message (remove\n> \t \t ACS register printout);\n> \n> drivers/pci/quirks.c | 26 ++++++++++++++++----------\n> 1 file changed, 16 insertions(+), 10 deletions(-)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index a4d3361..e6b904a 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -4211,20 +4211,26 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)\n> #endif\n> }\n> \n> -static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)\n> +/*\n> + * Cavium devices matching this quirk do not perform peer-to-peer\n> + * with other functions, allowing masking out these bits as if they\n> + * were unimplemented in the ACS capability.\n\nnit, the description here still steals too much from the multifunction\nquirk. Multifunction devices can often support ACS with unimplemented\ncapabilities, which indicate that the device does not support the\nbehavior described by that capability bit. However, downstream ports\nare required to implement certain ACS capabilities if they implement\nACS at all. So the code is actually asserting that the hardware\nimplements *and* enables equivalent ACS functionality for these flags.\n\n> + */\n> +#define CAVIUM_CN8XXX_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF)\n> +\n> +static __inline__ bool pci_quirk_cavium_acs_match(struct pci_dev *dev)\n> {\n> -\t/*\n> -\t * Cavium devices matching this quirk do not perform peer-to-peer\n> -\t * with other functions, allowing masking out these bits as if they\n> -\t * were unimplemented in the ACS capability.\n> -\t */\n> -\tacs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |\n> -\t\t PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);\n> +\treturn (pci_is_pcie(dev) &&\n> +\t\t(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&\n> +\t\t((dev->device & 0xf800) == 0xa000));\n\nThat's effectively 2k device IDs, 0xa000-0xa7ff that you and Cavium are\nvouching for ACS equivalent isolation. How many of these actually\nexist? The PCI IDs database gets really sparse after the first 64\nentries. Internally are these device IDs allocated to programs based on\nthe same ASICs or is this just a slightly more restricted crystal ball\n(ie. wishful thinking)? Thanks,\n\nAlex\n\n> +}\n> \n> -\tif (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))\n> +static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)\n> +{\n> +\tif (!pci_quirk_cavium_acs_match(dev))\n> \t\treturn -ENOTTY;\n> \n> -\treturn acs_flags ? 0 : 1;\n> +\treturn acs_flags & ~(CAVIUM_CN8XXX_ACS_FLAGS) ? 0 : 1;\n> }\n> \n> static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx07.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=alex.williamson@redhat.com"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xy4yc0KCcz9t2Q\n\tfor ;\n\tThu, 21 Sep 2017 02:32:08 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751998AbdITQby (ORCPT );\n\tWed, 20 Sep 2017 12:31:54 -0400","from mx1.redhat.com ([209.132.183.28]:44156 \"EHLO mx1.redhat.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751378AbdITQbw (ORCPT );\n\tWed, 20 Sep 2017 12:31:52 -0400","from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 01767C047B79;\n\tWed, 20 Sep 2017 16:31:52 +0000 (UTC)","from w520.home (ovpn-116-96.phx2.redhat.com [10.3.116.96])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 8ED346060A;\n\tWed, 20 Sep 2017 16:31:51 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 01767C047B79","Date":"Wed, 20 Sep 2017 10:31:51 -0600","From":"Alex Williamson ","To":"Vadim Lomovtsev ","Cc":"bhelgaas@google.com, linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Wilson.Snyder@cavium.com","Subject":"Re: [PATCH v4] PCI: quirks: update Cavium ThunderX ACS quirk\n\timplementation","Message-ID":"<20170920103151.7e3fdb77@w520.home>","In-Reply-To":"<1505724481-28413-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>","References":"<1505480233-22694-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>\n\t<1505724481-28413-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.13","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.31]);\n\tWed, 20 Sep 2017 16:31:52 +0000 (UTC)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1772550,"web_url":"http://patchwork.ozlabs.org/comment/1772550/","msgid":"<20170921083921.GA2135@localhost.localdomain>","list_archive_url":null,"date":"2017-09-21T08:39:21","subject":"Re: [PATCH v4] PCI: quirks: update Cavium ThunderX ACS quirk\n\timplementation","submitter":{"id":70764,"url":"http://patchwork.ozlabs.org/api/people/70764/","name":"Vadim Lomovtsev","email":"Vadim.Lomovtsev@caviumnetworks.com"},"content":"On Wed, Sep 20, 2017 at 10:31:51AM -0600, Alex Williamson wrote:\n> On Mon, 18 Sep 2017 01:48:01 -0700\n> Vadim Lomovtsev wrote:\n> \n> > This commit makes Cavium PCI ACS quirk applicable only to Cavium\n> > ThunderX (CN81/83/88XX) PCIE Root Ports which has limited PCI capabilities\n> > in terms of no ACS support advertisement. However, the RTL internally\n> > implements similar protection as if ACS had completion/request redirection,\n> > upstream forwarding and validation features enabled.\n> > \n> > Current quirk implementation doesn't take into account PCIERCs which\n> > also needs to be quirked. So the pci device id check mask is updated\n> > and check of device ID moved into separate function.\n> > \n> > Signed-off-by: Vadim Lomovtsev \n> > ---\n> > \tv1\t: put device check into separate function and extend it to all\n> > \t\t Cavium PCIERC/PCCBR devices;\n> > \tv1 -> v2: update match function in order to filter only ThunderX devices by device\n> > \t \t ids to properly filter CN8XXX devices, update subject & description with\n> > \t\t ACS register info (rejected by maillist due to triple X in subject);\n> > \tv2 -> v3: update subject: remove CN8XXX from subject line, replace it with ThunderX;\n> > \tv3 -> v4: update ACS mask (remove TB and TD bits), update commit message (remove\n> > \t \t ACS register printout);\n> > \n> > drivers/pci/quirks.c | 26 ++++++++++++++++----------\n> > 1 file changed, 16 insertions(+), 10 deletions(-)\n> > \n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> > index a4d3361..e6b904a 100644\n> > --- a/drivers/pci/quirks.c\n> > +++ b/drivers/pci/quirks.c\n> > @@ -4211,20 +4211,26 @@ static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)\n> > #endif\n> > }\n> > \n> > -static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)\n> > +/*\n> > + * Cavium devices matching this quirk do not perform peer-to-peer\n> > + * with other functions, allowing masking out these bits as if they\n> > + * were unimplemented in the ACS capability.\n> \n> nit,\n\nput this down for later use..\n\n> the description here still steals too much from the multifunction\n> quirk.\n\ndescription was just moved (and needs to be rewrited) since the orignal idea was\njust to extend quirk for all ThunderX family which has that limitation.\n\nWould the following be more suitable here:\n\n\"The Cavium downstream ports doesn't advertise their ACS capability registers.\nHowever, the RTL internally implements similar protection as if ACS had completion redirection,\nforwarding and validation features enabled.\" ?\n\n> Multifunction devices can often support ACS with unimplemented\n> capabilities, which indicate that the device does not support the\n> behavior described by that capability bit. However, downstream ports\n> are required to implement certain ACS capabilities if they implement\n> ACS at all. So the code is actually asserting that the hardware\n> implements *and* enables equivalent ACS functionality for these flags.\n\nYes it is. The hardware doesn't advertise ACS caps which is desing limitation,\nhowever it implements similar functionality to ACS provided flags which allows code to assert this.\n\n> \n> > + */\n> > +#define CAVIUM_CN8XXX_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF)\n> > +\n> > +static __inline__ bool pci_quirk_cavium_acs_match(struct pci_dev *dev)\n> > {\n> > -\t/*\n> > -\t * Cavium devices matching this quirk do not perform peer-to-peer\n> > -\t * with other functions, allowing masking out these bits as if they\n> > -\t * were unimplemented in the ACS capability.\n> > -\t */\n> > -\tacs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |\n> > -\t\t PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);\n> > +\treturn (pci_is_pcie(dev) &&\n> > +\t\t(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&\n> > +\t\t((dev->device & 0xf800) == 0xa000));\n> \n> That's effectively 2k device IDs, 0xa000-0xa7ff that you and Cavium are\n> vouching for ACS equivalent isolation. How many of these actually\n> exist? The PCI IDs database gets really sparse after the first 64\n> entries. Internally are these device IDs allocated to programs based on\n> the same ASICs or is this just a slightly more restricted crystal ball\n> (ie. wishful thinking)? Thanks,\n\nThe latter; this represents 8 SoCs, the lower 8 bits of the DEVID are used\nto indicate which subdevice is used within the SoC.\n\nVadim\n\n> \n> Alex\n> \n> > +}\n> > \n> > -\tif (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))\n> > +static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)\n> > +{\n> > +\tif (!pci_quirk_cavium_acs_match(dev))\n> > \t\treturn -ENOTTY;\n> > \n> > -\treturn acs_flags ? 0 : 1;\n> > +\treturn acs_flags & ~(CAVIUM_CN8XXX_ACS_FLAGS) ? 0 : 1;\n> > }\n> > \n> > static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=CAVIUMNETWORKS.onmicrosoft.com\n\theader.i=@CAVIUMNETWORKS.onmicrosoft.com header.b=\"kltJ+u4h\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=Vadim.Lomovtsev@cavium.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyVQs4JYFz9t3v\n\tfor ;\n\tThu, 21 Sep 2017 18:39:33 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751798AbdIUIjb (ORCPT );\n\tThu, 21 Sep 2017 04:39:31 -0400","from mail-sn1nam02on0069.outbound.protection.outlook.com\n\t([104.47.36.69]:45280\n\t\"EHLO NAM02-SN1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751635AbdIUIja (ORCPT );\n\tThu, 21 Sep 2017 04:39:30 -0400","from localhost.localdomain (50.233.148.156) by\n\tBN6PR07MB2996.namprd07.prod.outlook.com (10.172.106.14) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 21 Sep 2017 08:39:25 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=65BuPev2c2xGiak80QiF8ckNNcmIiXUonGfPSGXs7ds=;\n\tb=kltJ+u4hXC2ZyppfyKqM2ldCW+ZMxCT6JgX2HqwptrZ/2BC00L9cKGmXQCsMI+Bu54k2PAWv+D1eVRpHmeD2OM30Q6eCchuvnWkaLzqSjHn8iby9f5kKW71GGMELphE47056CCQXvtdlKoZtXOiqQLaSyI0LKODnt80gRBEOt/I=","Date":"Thu, 21 Sep 2017 01:39:21 -0700","From":"Vadim Lomovtsev ","To":"Alex Williamson ","Cc":"bhelgaas@google.com, linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Wilson.Snyder@cavium.com, jcm@redhat.com","Subject":"Re: [PATCH v4] PCI: quirks: update Cavium ThunderX ACS quirk\n\timplementation","Message-ID":"<20170921083921.GA2135@localhost.localdomain>","References":"<1505480233-22694-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>\n\t<1505724481-28413-1-git-send-email-Vadim.Lomovtsev@caviumnetworks.com>\n\t<20170920103151.7e3fdb77@w520.home>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170920103151.7e3fdb77@w520.home>","User-Agent":"Mutt/1.6.1 (2016-04-27)","X-Originating-IP":"[50.233.148.156]","X-ClientProxiedBy":"BN6PR1301CA0006.namprd13.prod.outlook.com (10.174.84.147)\n\tTo BN6PR07MB2996.namprd07.prod.outlook.com (10.172.106.14)","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"60e4e1da-28e8-40b6-89eb-08d500cc4433","X-Microsoft-Antispam":"UriScan:; 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