[{"id":1770036,"web_url":"http://patchwork.ozlabs.org/comment/1770036/","msgid":"<20170918115052.4606d8e5@bbrezillon>","list_archive_url":null,"date":"2017-09-18T09:50:52","subject":"Re: [PATCH v2 4/9] mtd: nand: atmel: Avoid ECC errors when leaving\n\tbackup mode","submitter":{"id":63120,"url":"http://patchwork.ozlabs.org/api/people/63120/","name":"Boris Brezillon","email":"boris.brezillon@free-electrons.com"},"content":"Hi Romain,\n\nOn Fri, 15 Sep 2017 16:04:06 +0200\nRomain Izard wrote:\n\n> During backup mode, the contents of all registers will be cleared as the\n> SoC will be completely powered down. For a product that boots on NAND\n> Flash memory, the bootloader will obviously use the related controller\n> to read the Flash and correct any detected error in the memory, before\n> handling back control to the kernel's resuming entry point.\n> \n> In normal devices, it is up to the driver's suspend/resume code to\n> restore the registers in a valid state. But the PMECC is not a regular\n> device in the driver model when used with the legacy device tree binding\n> for the Atmel NAND controller, and suspend/resume code is not called.\n> \n> As in my case the bootloader leaves the PMECC controller in a programmed\n> state, and the controller is only reset at boot or after a NAND access,\n> the first NAND Flash access with the Atmel controller will report\n> uncorrectable ECC errors.\n> \n> To avoid this, systematically reset the PMECC controller before using\n> it.\n> \n> Signed-off-by: Romain Izard \n> ---\n> drivers/mtd/nand/atmel/pmecc.c | 11 +++--------\n> 1 file changed, 3 insertions(+), 8 deletions(-)\n> \n> diff --git a/drivers/mtd/nand/atmel/pmecc.c b/drivers/mtd/nand/atmel/pmecc.c\n> index 8c210a5776bc..8d1208f38025 100644\n> --- a/drivers/mtd/nand/atmel/pmecc.c\n> +++ b/drivers/mtd/nand/atmel/pmecc.c\n> @@ -777,6 +777,9 @@ int atmel_pmecc_enable(struct atmel_pmecc_user *user, int op)\n> \n> \tmutex_lock(&user->pmecc->lock);\n> \n> +\twritel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);\n> +\twritel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);\n> +\n> \tcfg = user->cache.cfg;\n> \tif (op == NAND_ECC_WRITE)\n> \t\tcfg |= PMECC_CFG_WRITE_OP;\n> @@ -797,10 +800,6 @@ EXPORT_SYMBOL_GPL(atmel_pmecc_enable);\n> \n> void atmel_pmecc_disable(struct atmel_pmecc_user *user)\n> {\n> -\tstruct atmel_pmecc *pmecc = user->pmecc;\n> -\n> -\twritel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);\n> -\twritel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);\n\nSo know you leave the ECC engine enabled even when it's not in use? Not\nsure what kind of implication this has on power-consumption, but I\nthink I'd prefer to keep the write RST+DISABLE sequence in the disable\npath.\n\nHow about creating a atmel_pmecc_reset() function that you'd call from\nthe nand-controller resume hook. Something like:\n\nvoid atmel_pmecc_reset(struct atmel_pmecc *pmecc)\n{\n\twritel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);\n\twritel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);\n}\n\nThis way you can re-use the same function and call it from the probe\nand disable path as well.\n\nRegards,\n\nBoris\n\n> \tmutex_unlock(&user->pmecc->lock);\n> }\n> EXPORT_SYMBOL_GPL(atmel_pmecc_disable);\n> @@ -856,10 +855,6 @@ static struct atmel_pmecc *atmel_pmecc_create(struct platform_device *pdev,\n> \t/* Disable all interrupts before registering the PMECC handler. */\n> \twritel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR);\n> \n> -\t/* Reset the ECC engine */\n> -\twritel(PMECC_CTRL_RST, pmecc->regs.base + ATMEL_PMECC_CTRL);\n> -\twritel(PMECC_CTRL_DISABLE, pmecc->regs.base + ATMEL_PMECC_CTRL);\n> -\n> \treturn pmecc;\n> }\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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