[{"id":1769960,"web_url":"http://patchwork.ozlabs.org/comment/1769960/","msgid":"<3ac16f01-4ccc-b97b-932e-131f9702e613@rock-chips.com>","list_archive_url":null,"date":"2017-09-18T08:17:19","subject":"Re: [U-Boot] [PATCH 2/3] rockchip: back-to-bootrom: replace\n\tassembly-implementation with C-code","submitter":{"id":65124,"url":"http://patchwork.ozlabs.org/api/people/65124/","name":"Andy Yan","email":"andy.yan@rock-chips.com"},"content":"Hi Philipp:\n\n\nOn 2017年09月15日 20:02, Philipp Tomsich wrote:\n> The back-to-bootrom implementation for Rockchip has always relied on\n> the stack-pointer being valid on entry, so there was little reason to\n> have this as an assembly implementation.\n>\n> This provides a new C-only implementation of save_boot_params and\n> back_to_bootrom (relying on setjmp/longjmp) and removes the older\n> assembly-only implementation.\n>\n> Signed-off-by: Philipp Tomsich \n> ---\n>\n> arch/arm/include/asm/arch-rockchip/bootrom.h | 27 ++++++++---\n> arch/arm/mach-rockchip/Makefile | 4 +-\n> arch/arm/mach-rockchip/bootrom.c | 52 ++++++++++++++++++++-\n> arch/arm/mach-rockchip/save_boot_param.S | 69 ----------------------------\n> 4 files changed, 73 insertions(+), 79 deletions(-)\n> delete mode 100644 arch/arm/mach-rockchip/save_boot_param.S\n>\n> diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h\n> index 169cc5e..2f61a33 100644\n> --- a/arch/arm/include/asm/arch-rockchip/bootrom.h\n> +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h\n> @@ -1,5 +1,6 @@\n> /*\n> * (C) Copyright 2017 Heiko Stuebner \n> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH\n> *\n> * SPDX-License-Identifier:\tGPL-2.0\n> */\n> @@ -14,15 +15,27 @@\n> extern u32 SAVE_SP_ADDR;\n> \n> /**\n> - * Hand control back to the bootrom to load another\n> - * boot stage.\n> + * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a\n> + * result code\n> + *\n> + * Transfer control back to the Rockchip BROM, restoring necessary\n> + * register context and passing a command/result code to the BROM\n> + * to instruct its next actions (e.g. continue boot sequence, enter\n> + * download mode, ...).\n> + *\n> + * This function does not return.\n> */\n> -void back_to_bootrom(void);\n> +enum rockchip_bootrom_cmd {\n> +\t/*\n> +\t * These can not start at 0, as 0 has a special meaning\n> +\t * for setjmp().\n> +\t */\n> \n> -/**\n> - * Assembler component for the above (do not call this directly)\n> - */\n> -void _back_to_bootrom_s(void);\n> +\tBROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */\n> +\tBROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */\n> +};\n> +\n> +void back_to_bootrom(void);\n> \n> /**\n> * Boot-device identifiers as used by the BROM\n> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile\n> index 79e9704..f8b23ea 100644\n> --- a/arch/arm/mach-rockchip/Makefile\n> +++ b/arch/arm/mach-rockchip/Makefile\n> @@ -8,8 +8,8 @@\n> # this may have entered from ATF with the stack-pointer pointing to\n> # inaccessible/protected memory (and the bootrom-helper assumes that\n> # the stack-pointer is valid before switching to the U-Boot stack).\n> -obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o\n> -obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o\n> +obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o\n> +obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o\n> \n> obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o\n> obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o\n> diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c\n> index 8380e4e..7b9b307 100644\n> --- a/arch/arm/mach-rockchip/bootrom.c\n> +++ b/arch/arm/mach-rockchip/bootrom.c\n> @@ -6,11 +6,61 @@\n> \n> #include \n> #include \n> +#include \n> +#include \n> +\n> +/*\n> + * Force the jmp_buf to the data-section, as .bss will not be valid\n> + * when save_boot_params is invoked.\n> + */\n> +static jmp_buf brom_ctx __section(\".data\");\n> \n> void back_to_bootrom(void)\n> {\n> #if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)\n> \tputs(\"Returning to boot ROM...\\n\");\n> #endif\n> -\t_back_to_bootrom_s();\n> +\tlongjmp(brom_ctx, BROM_BOOT_NEXTSTAGE);\n> +}\n> +\n> +/*\n> + * All Rockchip BROM implementations enter with a valid stack-pointer,\n> + * so this can safely be implemented in C (providing a single\n> + * implementation both for ARMv7 and AArch64).\n> + */\n> +int save_boot_params(void)\n> +{\n> +\tint ret = setjmp(brom_ctx);\n> +\n> +\tswitch (ret) {\n> +\tcase 0:\n> +\t\t/*\n> +\t\t * This is the initial pass through this function\n> +\t\t * (i.e. saving the context), setjmp just setup up the\n> +\t\t * brom_ctx: transfer back into the startup-code at\n> +\t\t * 'save_boot_params_ret' and let the compiler know\n> +\t\t * that this will not return.\n> +\t\t */\n> +\t\tsave_boot_params_ret();\n\n\n This function works fine on ARM64 platform, But I got problems on \nARMv7. When trace the code flow with DS5 I found the core switch\nto thumb state when jump to save_boot_params_ret[0], but this code can't \nonly execute in arm state as thumb instruction can't access\ncpsr register. I don't know how to make sure the core in arm state when \njump to save_boot_params_ret.\n\n\nsave_boot_params_ret:\n#ifdef CONFIG_ARMV7_LPAE\n/*\n * check for Hypervisor support\n */\n mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1\n and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits\n cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)\n beq switch_to_hypervisor\nswitch_to_hypervisor_ret:\n#endif\n /*\n * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 \nmode,\n * except if in HYP mode already\n */\n mrs r0, cpsr\n and r1, r0, #0x1f @ mask mode bits\n teq r1, #0x1a @ test for HYP mode\n bicne r0, r0, #0x1f @ clear all mode bits\n orrne r0, r0, #0x13 @ set SVC mode\n orr r0, r0, #0xc0 @ disable FIQ and IRQ\n msr cpsr,r0\n\n> +\t\twhile (true)\n> +\t\t\t/* does not return */;\n> +\t\tbreak;\n> +\n> +\tcase BROM_BOOT_NEXTSTAGE:\n> +\t\t/*\n> +\t\t * To instruct the BROM to boot the next stage, we\n> +\t\t * need to return 0 to it: i.e. we need to rewrite\n> +\t\t * the return code once more.\n> +\t\t */\n> +\t\tret = 0;\n> +\t\tbreak;\n> +\n> +\tdefault:\n> +#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)\n> +\t\tputs(\"FATAL: unexpected command to back_to_bootrom()\\n\");\n> +#endif\n> +\t\thang();\n> +\t};\n> +\n> +\treturn ret;\n> }\n> diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S\n> deleted file mode 100644\n> index 50fce20..0000000\n> --- a/arch/arm/mach-rockchip/save_boot_param.S\n> +++ /dev/null\n> @@ -1,69 +0,0 @@\n> -/*\n> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd\n> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH\n> - *\n> - * SPDX-License-Identifier: GPL-2.0+\n> - */\n> -\n> -#include \n> -\n> -#if defined(CONFIG_ARM64)\n> -.globl\tSAVE_SP_ADDR\n> -SAVE_SP_ADDR:\n> -\t.quad 0\n> -\n> -ENTRY(save_boot_params)\n> -\tsub\tsp, sp, #0x60\n> -\tstp\tx29, x30, [sp, #0x50]\n> -\tstp\tx27, x28, [sp, #0x40]\n> -\tstp\tx25, x26, [sp, #0x30]\n> -\tstp\tx23, x24, [sp, #0x20]\n> -\tstp\tx21, x22, [sp, #0x10]\n> -\tstp\tx19, x20, [sp, #0]\n> -\tldr\tx8, =SAVE_SP_ADDR\n> -\tmov\tx9, sp\n> -\tstr\tx9, [x8]\n> -\tb\tsave_boot_params_ret /* back to my caller */\n> -ENDPROC(save_boot_params)\n> -\n> -.globl _back_to_bootrom_s\n> -ENTRY(_back_to_bootrom_s)\n> -\tldr\tx0, =SAVE_SP_ADDR\n> -\tldr\tx0, [x0]\n> -\tmov\tsp, x0\n> -\tldp\tx29, x30, [sp, #0x50]\n> -\tldp\tx27, x28, [sp, #0x40]\n> -\tldp\tx25, x26, [sp, #0x30]\n> -\tldp\tx23, x24, [sp, #0x20]\n> -\tldp\tx21, x22, [sp, #0x10]\n> -\tldp\tx19, x20, [sp]\n> -\tadd\tsp, sp, #0x60\n> -\tmov\tx0, xzr\n> -\tret\n> -ENDPROC(_back_to_bootrom_s)\n> -#else\n> -.globl\tSAVE_SP_ADDR\n> -SAVE_SP_ADDR:\n> -\t.word 0\n> -\n> -/*\n> - * void save_boot_params\n> - *\n> - * Save sp, lr, r1~r12\n> - */\n> -ENTRY(save_boot_params)\n> -\tpush\t{r1-r12, lr}\n> -\tldr\tr0, =SAVE_SP_ADDR\n> -\tstr\tsp, [r0]\n> -\tb\tsave_boot_params_ret\t\t@ back to my caller\n> -ENDPROC(save_boot_params)\n> -\n> -\n> -.globl _back_to_bootrom_s\n> -ENTRY(_back_to_bootrom_s)\n> -\tldr\tr0, =SAVE_SP_ADDR\n> -\tldr\tsp, [r0]\n> -\tmov\tr0, #0\n> -\tpop\t{r1-r12, pc}\n> -ENDPROC(_back_to_bootrom_s)\n> -#endif","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwf5268tNz9s3w\n\tfor ;\n\tMon, 18 Sep 2017 18:17:41 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 44CFBC21EFF; Mon, 18 Sep 2017 08:17:38 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 37CFFC21D57;\n\tMon, 18 Sep 2017 08:17:33 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 98798C21D57; Mon, 18 Sep 2017 08:17:32 +0000 (UTC)","from regular1.263xmail.com (regular1.263xmail.com [211.150.99.136])\n\tby lists.denx.de (Postfix) with ESMTPS id 30A86C21C5C\n\tfor ; Mon, 18 Sep 2017 08:17:31 +0000 (UTC)","from andy.yan?rock-chips.com (unknown [192.168.167.163])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 7DD2F80;\n\tMon, 18 Sep 2017 16:17:26 +0800 (CST)","from [172.16.12.133] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id B9AF13CD;\n\tMon, 18 Sep 2017 16:17:20 +0800 (CST)","from [172.16.12.133] (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 35332M638Y;\n\tMon, 18 Sep 2017 16:17:23 +0800 (CST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.6 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H2,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no\n\tversion=3.4.0","X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"andy.yan@rock-chips.com","X-FST-TO":"heiko@sntech.de","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"andy.yan@rock-chips.com","X-UNIQUE-TAG":"","X-ATTACHMENT-NUM":"0","X-SENDER":"yxj@rock-chips.com","X-DNS-TYPE":"0","To":"Philipp Tomsich ,\n\tu-boot@lists.denx.de","References":"<1505476946-64991-1-git-send-email-philipp.tomsich@theobroma-systems.com>\n\t<1505476946-64991-3-git-send-email-philipp.tomsich@theobroma-systems.com>","From":"Andy Yan ","Message-ID":"<3ac16f01-4ccc-b97b-932e-131f9702e613@rock-chips.com>","Date":"Mon, 18 Sep 2017 16:17:19 +0800","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1505476946-64991-3-git-send-email-philipp.tomsich@theobroma-systems.com>","Content-Language":"en-US","Cc":"Klaus Goger ","Subject":"Re: [U-Boot] [PATCH 2/3] rockchip: back-to-bootrom: replace\n\tassembly-implementation with C-code","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1769994,"web_url":"http://patchwork.ozlabs.org/comment/1769994/","msgid":"","list_archive_url":null,"date":"2017-09-18T09:00:59","subject":"Re: [U-Boot] [PATCH 2/3] rockchip: back-to-bootrom: replace\n\tassembly-implementation with C-code","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"On 18 Sep 2017, at 10:17, Andy Yan wrote:\n> \n> Hi Philipp:\n> \n> \n> On 2017年09月15日 20:02, Philipp Tomsich wrote:\n>> The back-to-bootrom implementation for Rockchip has always relied on\n>> the stack-pointer being valid on entry, so there was little reason to\n>> have this as an assembly implementation.\n>> \n>> This provides a new C-only implementation of save_boot_params and\n>> back_to_bootrom (relying on setjmp/longjmp) and removes the older\n>> assembly-only implementation.\n>> \n>> Signed-off-by: Philipp Tomsich \n>> ---\n>> \n>> arch/arm/include/asm/arch-rockchip/bootrom.h | 27 ++++++++---\n>> arch/arm/mach-rockchip/Makefile | 4 +-\n>> arch/arm/mach-rockchip/bootrom.c | 52 ++++++++++++++++++++-\n>> arch/arm/mach-rockchip/save_boot_param.S | 69 ----------------------------\n>> 4 files changed, 73 insertions(+), 79 deletions(-)\n>> delete mode 100644 arch/arm/mach-rockchip/save_boot_param.S\n>> \n>> diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h\n>> index 169cc5e..2f61a33 100644\n>> --- a/arch/arm/include/asm/arch-rockchip/bootrom.h\n>> +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h\n>> @@ -1,5 +1,6 @@\n>> /*\n>> * (C) Copyright 2017 Heiko Stuebner \n>> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH\n>> *\n>> * SPDX-License-Identifier:\tGPL-2.0\n>> */\n>> @@ -14,15 +15,27 @@\n>> extern u32 SAVE_SP_ADDR;\n>> /**\n>> - * Hand control back to the bootrom to load another\n>> - * boot stage.\n>> + * back_to_bootrom() - return to bootrom (for TPL/SPL), passing a\n>> + * result code\n>> + *\n>> + * Transfer control back to the Rockchip BROM, restoring necessary\n>> + * register context and passing a command/result code to the BROM\n>> + * to instruct its next actions (e.g. continue boot sequence, enter\n>> + * download mode, ...).\n>> + *\n>> + * This function does not return.\n>> */\n>> -void back_to_bootrom(void);\n>> +enum rockchip_bootrom_cmd {\n>> +\t/*\n>> +\t * These can not start at 0, as 0 has a special meaning\n>> +\t * for setjmp().\n>> +\t */\n>> -/**\n>> - * Assembler component for the above (do not call this directly)\n>> - */\n>> -void _back_to_bootrom_s(void);\n>> +\tBROM_BOOT_NEXTSTAGE = 1, /* continue boot-sequence */\n>> +\tBROM_BOOT_ENTER_DNL, /* have BROM enter download-mode */\n>> +};\n>> +\n>> +void back_to_bootrom(void);\n>> /**\n>> * Boot-device identifiers as used by the BROM\n>> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile\n>> index 79e9704..f8b23ea 100644\n>> --- a/arch/arm/mach-rockchip/Makefile\n>> +++ b/arch/arm/mach-rockchip/Makefile\n>> @@ -8,8 +8,8 @@\n>> # this may have entered from ATF with the stack-pointer pointing to\n>> # inaccessible/protected memory (and the bootrom-helper assumes that\n>> # the stack-pointer is valid before switching to the U-Boot stack).\n>> -obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o\n>> -obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o\n>> +obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o\n>> +obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o\n>> obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o\n>> obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o\n>> diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c\n>> index 8380e4e..7b9b307 100644\n>> --- a/arch/arm/mach-rockchip/bootrom.c\n>> +++ b/arch/arm/mach-rockchip/bootrom.c\n>> @@ -6,11 +6,61 @@\n>> #include \n>> #include \n>> +#include \n>> +#include \n>> +\n>> +/*\n>> + * Force the jmp_buf to the data-section, as .bss will not be valid\n>> + * when save_boot_params is invoked.\n>> + */\n>> +static jmp_buf brom_ctx __section(\".data\");\n>> void back_to_bootrom(void)\n>> {\n>> #if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)\n>> \tputs(\"Returning to boot ROM...\\n\");\n>> #endif\n>> -\t_back_to_bootrom_s();\n>> +\tlongjmp(brom_ctx, BROM_BOOT_NEXTSTAGE);\n>> +}\n>> +\n>> +/*\n>> + * All Rockchip BROM implementations enter with a valid stack-pointer,\n>> + * so this can safely be implemented in C (providing a single\n>> + * implementation both for ARMv7 and AArch64).\n>> + */\n>> +int save_boot_params(void)\n>> +{\n>> +\tint ret = setjmp(brom_ctx);\n>> +\n>> +\tswitch (ret) {\n>> +\tcase 0:\n>> +\t\t/*\n>> +\t\t * This is the initial pass through this function\n>> +\t\t * (i.e. saving the context), setjmp just setup up the\n>> +\t\t * brom_ctx: transfer back into the startup-code at\n>> +\t\t * 'save_boot_params_ret' and let the compiler know\n>> +\t\t * that this will not return.\n>> +\t\t */\n>> +\t\tsave_boot_params_ret();\n> \n> \n> This function works fine on ARM64 platform, But I got problems on ARMv7. When trace the code flow with DS5 I found the core switch\n> to thumb state when jump to save_boot_params_ret[0], but this code can't only execute in arm state as thumb instruction can't access\n> cpsr register. I don't know how to make sure the core in arm state when jump to save_boot_params_ret.\n\nThanks for the detailed diagnosis. I’ll take a look on how to best force\nthe compiler to emit this function in ARM state: I hope to be able to use\na target(arm) function attribute (see https://gcc.gnu.org/onlinedocs/gcc/ARM-Function-Attributes.html)\n\n> \n> \n> save_boot_params_ret:\n> #ifdef CONFIG_ARMV7_LPAE\n> /*\n> * check for Hypervisor support\n> */\n> mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1\n> and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits\n> cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)\n> beq switch_to_hypervisor\n> switch_to_hypervisor_ret:\n> #endif\n> /*\n> * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,\n> * except if in HYP mode already\n> */\n> mrs r0, cpsr\n> and r1, r0, #0x1f @ mask mode bits\n> teq r1, #0x1a @ test for HYP mode\n> bicne r0, r0, #0x1f @ clear all mode bits\n> orrne r0, r0, #0x13 @ set SVC mode\n> orr r0, r0, #0xc0 @ disable FIQ and IRQ\n> msr cpsr,r0\n> \n>> +\t\twhile (true)\n>> +\t\t\t/* does not return */;\n>> +\t\tbreak;\n>> +\n>> +\tcase BROM_BOOT_NEXTSTAGE:\n>> +\t\t/*\n>> +\t\t * To instruct the BROM to boot the next stage, we\n>> +\t\t * need to return 0 to it: i.e. we need to rewrite\n>> +\t\t * the return code once more.\n>> +\t\t */\n>> +\t\tret = 0;\n>> +\t\tbreak;\n>> +\n>> +\tdefault:\n>> +#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT)\n>> +\t\tputs(\"FATAL: unexpected command to back_to_bootrom()\\n\");\n>> +#endif\n>> +\t\thang();\n>> +\t};\n>> +\n>> +\treturn ret;\n>> }\n>> diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S\n>> deleted file mode 100644\n>> index 50fce20..0000000\n>> --- a/arch/arm/mach-rockchip/save_boot_param.S\n>> +++ /dev/null\n>> @@ -1,69 +0,0 @@\n>> -/*\n>> - * (C) Copyright 2016 Rockchip Electronics Co., Ltd\n>> - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH\n>> - *\n>> - * SPDX-License-Identifier: GPL-2.0+\n>> - */\n>> -\n>> -#include \n>> -\n>> -#if defined(CONFIG_ARM64)\n>> -.globl\tSAVE_SP_ADDR\n>> -SAVE_SP_ADDR:\n>> -\t.quad 0\n>> -\n>> -ENTRY(save_boot_params)\n>> -\tsub\tsp, sp, #0x60\n>> -\tstp\tx29, x30, [sp, #0x50]\n>> -\tstp\tx27, x28, [sp, #0x40]\n>> -\tstp\tx25, x26, [sp, #0x30]\n>> -\tstp\tx23, x24, [sp, #0x20]\n>> -\tstp\tx21, x22, [sp, #0x10]\n>> -\tstp\tx19, x20, [sp, #0]\n>> -\tldr\tx8, =SAVE_SP_ADDR\n>> -\tmov\tx9, sp\n>> -\tstr\tx9, [x8]\n>> -\tb\tsave_boot_params_ret /* back to my caller */\n>> -ENDPROC(save_boot_params)\n>> -\n>> -.globl _back_to_bootrom_s\n>> -ENTRY(_back_to_bootrom_s)\n>> -\tldr\tx0, =SAVE_SP_ADDR\n>> -\tldr\tx0, [x0]\n>> -\tmov\tsp, x0\n>> -\tldp\tx29, x30, [sp, #0x50]\n>> -\tldp\tx27, x28, [sp, #0x40]\n>> -\tldp\tx25, x26, [sp, #0x30]\n>> -\tldp\tx23, x24, [sp, #0x20]\n>> -\tldp\tx21, x22, [sp, #0x10]\n>> -\tldp\tx19, x20, [sp]\n>> -\tadd\tsp, sp, #0x60\n>> -\tmov\tx0, xzr\n>> -\tret\n>> -ENDPROC(_back_to_bootrom_s)\n>> -#else\n>> -.globl\tSAVE_SP_ADDR\n>> -SAVE_SP_ADDR:\n>> -\t.word 0\n>> -\n>> -/*\n>> - * void save_boot_params\n>> - *\n>> - * Save sp, lr, r1~r12\n>> - */\n>> -ENTRY(save_boot_params)\n>> -\tpush\t{r1-r12, lr}\n>> -\tldr\tr0, =SAVE_SP_ADDR\n>> -\tstr\tsp, [r0]\n>> -\tb\tsave_boot_params_ret\t\t@ back to my caller\n>> -ENDPROC(save_boot_params)\n>> -\n>> -\n>> -.globl _back_to_bootrom_s\n>> -ENTRY(_back_to_bootrom_s)\n>> -\tldr\tr0, =SAVE_SP_ADDR\n>> -\tldr\tsp, [r0]\n>> -\tmov\tr0, #0\n>> -\tpop\t{r1-r12, pc}\n>> -ENDPROC(_back_to_bootrom_s)\n>> -#endif","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwg3R6Kgjz9s7c\n\tfor ;\n\tMon, 18 Sep 2017 19:01:21 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 55E86C21E61; Mon, 18 Sep 2017 09:01:11 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 45EC2C21C5C;\n\tMon, 18 Sep 2017 09:01:07 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 975E5C21C5C; Mon, 18 Sep 2017 09:01:05 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id AEDB0C21C41\n\tfor ; Mon, 18 Sep 2017 09:01:02 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:58163\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dtrvJ-0004gv-18; Mon, 18 Sep 2017 11:01:01 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<3ac16f01-4ccc-b97b-932e-131f9702e613@rock-chips.com>","Date":"Mon, 18 Sep 2017 11:00:59 +0200","Message-Id":"","References":"<1505476946-64991-1-git-send-email-philipp.tomsich@theobroma-systems.com>\n\t<1505476946-64991-3-git-send-email-philipp.tomsich@theobroma-systems.com>\n\t<3ac16f01-4ccc-b97b-932e-131f9702e613@rock-chips.com>","To":"Andy Yan ","X-Mailer":"Apple Mail (2.3273)","Cc":"U-Boot Mailing List ,\n\tKlaus Goger ","Subject":"Re: [U-Boot] [PATCH 2/3] rockchip: back-to-bootrom: replace\n\tassembly-implementation with C-code","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1770423,"web_url":"http://patchwork.ozlabs.org/comment/1770423/","msgid":"","list_archive_url":null,"date":"2017-09-18T18:49:40","subject":"Re: [U-Boot] [PATCH 2/3] rockchip: back-to-bootrom: replace\n\tassembly-implementation with C-code","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"Andy,\n\n> This function works fine on ARM64 platform, But I got problems on ARMv7. When trace the code flow with DS5 I found the core switch\n> to thumb state when jump to save_boot_params_ret[0], but this code can't only execute in arm state as thumb instruction can't access\n> cpsr register. I don't know how to make sure the core in arm state when jump to save_boot_params_ret.\n> \n> \n> save_boot_params_ret:\n> #ifdef CONFIG_ARMV7_LPAE\n> /*\n> * check for Hypervisor support\n> */\n> mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1\n> and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits\n> cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)\n> beq switch_to_hypervisor\n> switch_to_hypervisor_ret:\n> #endif\n> /*\n> * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,\n> * except if in HYP mode already\n> */\n> mrs r0, cpsr\n> and r1, r0, #0x1f @ mask mode bits\n> teq r1, #0x1a @ test for HYP mode\n> bicne r0, r0, #0x1f @ clear all mode bits\n> orrne r0, r0, #0x13 @ set SVC mode\n> orr r0, r0, #0xc0 @ disable FIQ and IRQ\n> msr cpsr,r0\n\nThanks for tracing this to the missing T32->A32 transition on the return path.\nI update the series and things should now work better (I hope):\n\thttps://patchwork.ozlabs.org/user/todo/uboot/?series=3697\n\nI also had to touch the RK3188 support (and don’t have a board to test), so\nany testing for the RK3188 change will also be appreciated.\n\n—Philipp.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xww6W2r3bz9rxl\n\tfor ;\n\tTue, 19 Sep 2017 04:49:54 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid DDDCBC21D19; Mon, 18 Sep 2017 18:49:47 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 020FFC21C41;\n\tMon, 18 Sep 2017 18:49:45 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid A3CDDC21C41; Mon, 18 Sep 2017 18:49:43 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 65F39C21C2B\n\tfor ; Mon, 18 Sep 2017 18:49:43 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:50393\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1du16z-000620-Hm; Mon, 18 Sep 2017 20:49:41 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<3ac16f01-4ccc-b97b-932e-131f9702e613@rock-chips.com>","Date":"Mon, 18 Sep 2017 20:49:40 +0200","Message-Id":"","References":"<1505476946-64991-1-git-send-email-philipp.tomsich@theobroma-systems.com>\n\t<1505476946-64991-3-git-send-email-philipp.tomsich@theobroma-systems.com>\n\t<3ac16f01-4ccc-b97b-932e-131f9702e613@rock-chips.com>","To":"Andy Yan ","X-Mailer":"Apple Mail (2.3273)","Cc":"U-Boot Mailing List ,\n\tKlaus Goger ","Subject":"Re: [U-Boot] [PATCH 2/3] rockchip: back-to-bootrom: replace\n\tassembly-implementation with C-code","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]