[{"id":1769050,"web_url":"http://patchwork.ozlabs.org/comment/1769050/","msgid":"<20170915084018.GI5432@drishya.in.ibm.com>","list_archive_url":null,"date":"2017-09-15T08:40:18","subject":"Re: [Skiboot] [PATCH v4 8/8] Add Documenation for opal_slw_set_reg","submitter":{"id":497,"url":"http://patchwork.ozlabs.org/api/people/497/","name":"Vaidyanathan Srinivasan","email":"svaidy@linux.vnet.ibm.com"},"content":"* Akshay Adiga [2017-09-15 13:04:36]:\n\n> Signed-off-by: Akshay Adiga \n\nReviewed-by: Vaidyanathan Srinivasan \n\n\n> ---\n> doc/opal-api/opal-slw-set-reg-100.rst | 46 +++++++++++++++++++++++++++++++++++\n> 1 file changed, 46 insertions(+)\n> create mode 100644 doc/opal-api/opal-slw-set-reg-100.rst\n> \n> diff --git a/doc/opal-api/opal-slw-set-reg-100.rst b/doc/opal-api/opal-slw-set-reg-100.rst\n> new file mode 100644\n> index 0000000..64ecdee\n> --- /dev/null\n> +++ b/doc/opal-api/opal-slw-set-reg-100.rst\n> @@ -0,0 +1,46 @@\n> +OPAL_SLW_SET_REG\n> +==============================\n> +::\n> +\n> + int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)\n> +\n> +\n> +OPAL_SLW_SET_REG is used to inform low-level firmware to restore a\n> +given value of SPR when there is a state loss. The actual set of SPR\n> +that is supported is platform dependent.\n> +\n> +\n> +In Power 8, it uses p8_pore_gen_cpufreq_fixed(), api provided by pore engine,\n> +to inform the spr with their corresponding values with which they\n> +must be restored.\n> +\n> +\n> +In Power 9, it uses p9_stop_save_cpureg(), api provided by self restore code,\n> +to inform the spr with their corresponding values with which they\n> +must be restored.\n> +\n> +\n> +Parameters\n> +----------\n> +\n> +``uint64_t cpu_pir``\n> +This parameter specifies the pir of the cpu for which the call is being made.\n> +\n> +``uint64_t sprn``\n> +This parameter specifies the spr number as mentioned in p9_stop_api.H for\n> +Power9 and p8_pore_table_gen_api.H for Power8.\n> +\n> +``uint64_t val``\n> +This parameter specifices value with which the spr should be restored.\n> +\n> +Returns\n> +-------\n> +\n> +``OPAL_INTERNAL_ERROR``\n> +On failure. The actual error code from the platform specific code is logged in the OPAL logs\n> +\n> +``OPAL_UNSUPPORTED``\n> +In power8 only, if spr restore is not supported by pore engine.\n\nIf the low-level firmware does not support this feature or the given SPR is not supported by the pore engine or stop api. \n\n> +\n> +``OPAL_SUCCESS``\n> +On success\n> -- \n> 2.5.5\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtpmK64Qhz9s3w\n\tfor ;\n\tFri, 15 Sep 2017 18:41:53 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xtpmK4btRzDrYf\n\tfor ;\n\tFri, 15 Sep 2017 18:41:53 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xtpkn0xcXzDrZX\n\tfor ; Fri, 15 Sep 2017 18:40:32 +1000 (AEST)","from pps.filterd (m0098414.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8F8dbBS041268\n\tfor ; Fri, 15 Sep 2017 04:40:29 -0400","from e23smtp04.au.ibm.com (e23smtp04.au.ibm.com [202.81.31.146])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2d0b540ywh-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Fri, 15 Sep 2017 04:40:29 -0400","from localhost\n\tby e23smtp04.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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