[{"id":1769038,"web_url":"http://patchwork.ozlabs.org/comment/1769038/","msgid":"<20170915083105.GE5432@drishya.in.ibm.com>","list_archive_url":null,"date":"2017-09-15T08:31:05","subject":"Re: [Skiboot] [PATCH v4 4/8] SLW: Add opal_slw_set_reg support for\n\tpower9","submitter":{"id":497,"url":"http://patchwork.ozlabs.org/api/people/497/","name":"Vaidyanathan Srinivasan","email":"svaidy@linux.vnet.ibm.com"},"content":"* Akshay Adiga [2017-09-15 13:04:32]:\n\n> This OPAL call is made from Linux to OPAL to configure values in\n> various SPRs after wakeup from a deep idle state.\n\nThe opal_slw_set_reg() OPAL call is used by Linux during init to setup\ncertain SPR values that should be loaded by microcode on wakeup from\na deep idle states where some SPR states are lost.\n\nThis helps to speed up wakeup by restoring key registers like HSPRG0,\nLPCR and MSR. On POWER9 platform Linux MSR need to be set using this\nAPI since the micro-code running on host processor may have\na different MSR context.\n \n> Signed-off-by: Akshay Adiga \n\nReviewed-by: Vaidyanathan Srinivasan \n\n\n> ---\n> hw/slw.c | 60 ++++++++++++++++++++++++++++++++++++++++--------------------\n> 1 file changed, 40 insertions(+), 20 deletions(-)\n> \n> diff --git a/hw/slw.c b/hw/slw.c\n> index d8829a6..a1ed7ba 100644\n> --- a/hw/slw.c\n> +++ b/hw/slw.c\n> @@ -30,6 +30,7 @@\n> #include \n> #include \n> \n> +#include \n> #include \n> #include \n> \n> @@ -1402,41 +1403,60 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)\n> \n> \tstruct cpu_thread *c = find_cpu_by_pir(cpu_pir);\n> \tstruct proc_chip *chip;\n> -\tvoid *image;\n> \tint rc;\n> -\tint i;\n> -\tint spr_is_supported = 0;\n> \n> \tassert(c);\n> \tchip = get_chip(c->chip_id);\n> \tassert(chip);\n> -\timage = (void *) chip->slw_base;\n> \n> -\t/* Check of the SPR is supported by libpore */\n> -\tfor ( i=0; i < SLW_SPR_REGS_SIZE ; i++) {\n> -\t\tif (sprn == SLW_SPR_REGS[i].value) {\n> -\t\t\tspr_is_supported = 1;\n> -\t\t\tbreak;\n> +\tif (proc_gen == proc_gen_p9) {\n> +\t\tif (!chip->homer_base) {\n> +\t\t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n> +\t\t\t\t\t \"SLW: HOMER base not set %x\\n\",\n> +\t\t\t\t\t chip->id);\n> +\t\t\treturn OPAL_INTERNAL_ERROR;\n> \t\t}\n> -\t}\n> -\tif (!spr_is_supported) {\n> -\t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n> +\t\trc = p9_stop_save_cpureg((void *)chip->homer_base,\n> +\t\t\t\t\t sprn, val, cpu_pir);\n> +\n> +\t} else if (proc_gen == proc_gen_p8) {\n> +\t\tint spr_is_supported = 0;\n> +\t\tvoid *image;\n> +\t\tint i;\n> +\n> +\t\t/* Check of the SPR is supported by libpore */\n> +\t\tfor (i = 0; i < SLW_SPR_REGS_SIZE ; i++) {\n> +\t\t\tif (sprn == SLW_SPR_REGS[i].value) {\n> +\t\t\t\tspr_is_supported = 1;\n> +\t\t\t\tbreak;\n> +\t\t\t}\n> +\t\t}\n> +\t\tif (!spr_is_supported) {\n> +\t\t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n> \t\t\t\"SLW: Trying to set unsupported spr for CPU %x\\n\",\n> -\t\t\tc->pir);\n> +\t\t\t\tc->pir);\n> +\t\t\treturn OPAL_UNSUPPORTED;\n> +\t\t}\n> +\t\timage = (void *)chip->slw_base;\n> +\t\trc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,\n> +\t\t\t\t\t sprn, val,\n> +\t\t\t\t\t cpu_get_core_index(c),\n> +\t\t\t\t\t cpu_get_thread_index(c));\n> +\t} else {\n> +\t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n> +\t\t\"SLW: proc_gen not supported\\n\");\n> \t\treturn OPAL_UNSUPPORTED;\n> -\t}\n> \n> -\trc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, sprn,\n> -\t\t\t\t\t\tval, cpu_get_core_index(c),\n> -\t\t\t\t\t\tcpu_get_thread_index(c));\n> +\t}\n> \n> \tif (rc) {\n> \t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n> -\t\t\t\"SLW: Failed to set spr for CPU %x\\n\",\n> -\t\t\tc->pir);\n> +\t\t\t\"SLW: Failed to set spr %llx for CPU %x, RC=0x%x\\n\",\n> +\t\t\tsprn, c->pir, rc);\n> \t\treturn OPAL_INTERNAL_ERROR;\n> \t}\n> -\n> +\tprlog(PR_DEBUG, \"SLW: restore spr:0x%llx on c:0x%x with 0x%llx\\n\",\n> +\t sprn, c->pir, val);\n> \treturn OPAL_SUCCESS;\n> \n> }\n> -- \n> 2.5.5\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtpXC5vcYz9sPr\n\tfor ;\n\tFri, 15 Sep 2017 18:31:23 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xtpXC50nzzDrX7\n\tfor ;\n\tFri, 15 Sep 2017 18:31:23 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xtpX84slszDrWR\n\tfor ; Fri, 15 Sep 2017 18:31:20 +1000 (AEST)","from pps.filterd (m0098396.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8F8TbnO016650\n\tfor ; Fri, 15 Sep 2017 04:31:18 -0400","from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2d07g8jg3q-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Fri, 15 Sep 2017 04:31:18 -0400","from localhost\n\tby e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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