[{"id":1768653,"web_url":"http://patchwork.ozlabs.org/comment/1768653/","msgid":"<20170914143454.GB27601@lunn.ch>","list_archive_url":null,"date":"2017-09-14T14:34:54","subject":"Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register.","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:\n> To clear Speed Selection in MDIO control register(0x10),\n> ie, clear bits 6 and 13 to zero while keeping other bits same.\n> Before AND operation,The Mask value has to be perform with bitwise NOT\n> operation (ie, ~ operator)\n> \n> This patch clears current speed selection before writing the\n> new speed settings to gmii2rgmii converter\n\nHi Fahad\n\nI expect you will find other issues with this driver. I pointed some\nout at the time it is submitted, but the developers went quiet as soon\nas it was accepted.\n\nAnyway, please ensure David Miller gets a copy.\n\nThe subject line should be:\n\n[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register.\n\nand include a fixes tag:\n\nFixes: f411a6160bd4 (\"net: phy: Add gmiitorgmii converter support\")\n\nReviewed-by: Andrew Lunn \n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtMFN5Bz7z9sP1\n\tfor ;\n\tFri, 15 Sep 2017 01:02:00 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751479AbdINPBt (ORCPT );\n\tThu, 14 Sep 2017 11:01:49 -0400","from vps0.lunn.ch ([185.16.172.187]:43408 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751255AbdINPBs (ORCPT );\n\tThu, 14 Sep 2017 11:01:48 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dsVEE-0006xf-UE; Thu, 14 Sep 2017 16:34:54 +0200"],"X-Greylist":"delayed 1609 seconds by postgrey-1.27 at vger.kernel.org;\n\tThu, 14 Sep 2017 11:01:47 EDT","Date":"Thu, 14 Sep 2017 16:34:54 +0200","From":"Andrew Lunn ","To":"Fahad Kunnathadi ","Cc":"f.fainelli@gmail.com, netdev@vger.kernel.org,\n\tmichal.simek@xilinx.com, linux-kernel@vger.kernel.org,\n\tsoren.brinkmann@xilinx.com, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register.","Message-ID":"<20170914143454.GB27601@lunn.ch>","References":"<1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1768982,"web_url":"http://patchwork.ozlabs.org/comment/1768982/","msgid":"<597180344.2790975.1505459785154.JavaMail.zimbra@dexceldesigns.com>","list_archive_url":null,"date":"2017-09-15T07:16:25","subject":"Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register.","submitter":{"id":72361,"url":"http://patchwork.ozlabs.org/api/people/72361/","name":"Fahad Kunnathadi","email":"fahad.kunnathadi@dexceldesigns.com"},"content":"Hi Andrew,\n\nThank you for review and comments.\n\nI will review this driver code with any review comments before, and update you if I could find any..\n\nBest Regards\nFahad K \n\n----- Original Message -----\nFrom: \"Andrew Lunn\" \nTo: \"Fahad Kunnathadi\" \nCc: \"f fainelli\" , netdev@vger.kernel.org, \"Michal Simek\" , linux-kernel@vger.kernel.org, \"soren brinkmann\" , linux-arm-kernel@lists.infradead.org\nSent: Thursday, September 14, 2017 8:04:54 PM\nSubject: Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter speed register.\n\nOn Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:\n> To clear Speed Selection in MDIO control register(0x10),\n> ie, clear bits 6 and 13 to zero while keeping other bits same.\n> Before AND operation,The Mask value has to be perform with bitwise NOT\n> operation (ie, ~ operator)\n> \n> This patch clears current speed selection before writing the\n> new speed settings to gmii2rgmii converter\n\nHi Fahad\n\nI expect you will find other issues with this driver. I pointed some\nout at the time it is submitted, but the developers went quiet as soon\nas it was accepted.\n\nAnyway, please ensure David Miller gets a copy.\n\nThe subject line should be:\n\n[PATCH net] net: phy: Fix mask value write on gmii2rgmii converter speed register.\n\nand include a fixes tag:\n\nFixes: f411a6160bd4 (\"net: phy: Add gmiitorgmii converter support\")\n\nReviewed-by: Andrew Lunn \n\n Andrew","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtmxP0jPxz9t2Z\n\tfor ;\n\tFri, 15 Sep 2017 17:19:37 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751197AbdIOHTX (ORCPT );\n\tFri, 15 Sep 2017 03:19:23 -0400","from bizsmtp.net4india.com ([118.67.236.10]:43409 \"EHLO\n\tsmtp.bizmail.net4india.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1750865AbdIOHTW (ORCPT\n\t); Fri, 15 Sep 2017 03:19:22 -0400","from [122.166.48.236] (helo=mailserver.dexceldesigns.com)\n\tby smtp.bizmail.net4india.com with esmtp (Exim 4.72)\n\t(envelope-from )\n\tid 1dsktq-0004ut-GA; Fri, 15 Sep 2017 12:48:54 +0530","from mailserver.dexceldesigns.com (localhost [127.0.0.1])\n\tby mailserver.dexceldesigns.com (Postfix) with ESMTPS id 94B061CE0755;\n\tFri, 15 Sep 2017 12:46:25 +0530 (IST)","from localhost (localhost [127.0.0.1])\n\tby mailserver.dexceldesigns.com (Postfix) with ESMTP id 80CF11CE0754; \n\tFri, 15 Sep 2017 12:46:25 +0530 (IST)","from mailserver.dexceldesigns.com ([127.0.0.1])\n\tby localhost (mailserver.dexceldesigns.com [127.0.0.1]) (amavisd-new,\n\tport 10026)\n\twith ESMTP id vApAtYTDG5Pp; Fri, 15 Sep 2017 12:46:25 +0530 (IST)","from mailserver.dexceldesigns.com (localhost [127.0.0.1])\n\tby mailserver.dexceldesigns.com (Postfix) with ESMTP id 5D14C1CE0751; \n\tFri, 15 Sep 2017 12:46:25 +0530 (IST)"],"Date":"Fri, 15 Sep 2017 12:46:25 +0530 (IST)","From":"Fahad Kunnathadi ","To":"Andrew Lunn ","Cc":"f fainelli , netdev@vger.kernel.org,\n\tMichal Simek , linux-kernel@vger.kernel.org,\n\tsoren brinkmann ,\n\tlinux-arm-kernel@lists.infradead.org","Message-ID":"<597180344.2790975.1505459785154.JavaMail.zimbra@dexceldesigns.com>","In-Reply-To":"<20170914143454.GB27601@lunn.ch>","References":"<1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>\n\t<20170914143454.GB27601@lunn.ch>","Subject":"Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register.","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[192.168.0.222]","X-Mailer":"Zimbra 8.7.0_GA_1659 (ZimbraWebClient - FF49 (Linux)/8.7.0_GA_1659)","Thread-Topic":"Fix mask value write on gmii2rgmii converter speed register.","Thread-Index":"n+jEvAnBIiuSmYjoXO4VFful/A05mQ==","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1769003,"web_url":"http://patchwork.ozlabs.org/comment/1769003/","msgid":"<5f4bd003-d251-5a14-497a-9cc72dd0f160@xilinx.com>","list_archive_url":null,"date":"2017-09-15T07:49:41","subject":"Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register.","submitter":{"id":18585,"url":"http://patchwork.ozlabs.org/api/people/18585/","name":"Michal Simek","email":"michal.simek@xilinx.com"},"content":"On 14.9.2017 16:34, Andrew Lunn wrote:\n> On Thu, Sep 14, 2017 at 12:46:31PM +0530, Fahad Kunnathadi wrote:\n>> To clear Speed Selection in MDIO control register(0x10),\n>> ie, clear bits 6 and 13 to zero while keeping other bits same.\n>> Before AND operation,The Mask value has to be perform with bitwise NOT\n>> operation (ie, ~ operator)\n>>\n>> This patch clears current speed selection before writing the\n>> new speed settings to gmii2rgmii converter\n> \n> Hi Fahad\n> \n> I expect you will find other issues with this driver. I pointed some\n> out at the time it is submitted, but the developers went quiet as soon\n> as it was accepted.\n\nCan you please point me to that email?\nI will create ticket about it in our system to get them resolved.\n\nThanks,\nMichal","headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=xilinx.onmicrosoft.com\n\theader.i=@xilinx.onmicrosoft.com header.b=\"ytdrhF9P\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtncw4mfcz9sPr\n\tfor ;\n\tFri, 15 Sep 2017 17:50:24 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751260AbdIOHt4 (ORCPT );\n\tFri, 15 Sep 2017 03:49:56 -0400","from mail-cys01nam02on0084.outbound.protection.outlook.com\n\t([104.47.37.84]:52895\n\t\"EHLO NAM02-CY1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1750787AbdIOHty (ORCPT );\n\tFri, 15 Sep 2017 03:49:54 -0400","from SN4PR0201CA0018.namprd02.prod.outlook.com (10.161.238.156) by\n\tSN1PR0201MB1936.namprd02.prod.outlook.com (10.163.87.158) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.35.12; 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helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xty406pylz9s72\n\tfor ;\n\tSat, 16 Sep 2017 00:10:56 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751422AbdIOOKp (ORCPT );\n\tFri, 15 Sep 2017 10:10:45 -0400","from vps0.lunn.ch ([185.16.172.187]:44372 \"EHLO vps0.lunn.ch\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751259AbdIOOKo (ORCPT );\n\tFri, 15 Sep 2017 10:10:44 -0400","from andrew by vps0.lunn.ch with local (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dsrKL-0006BS-GT; Fri, 15 Sep 2017 16:10:41 +0200"],"Date":"Fri, 15 Sep 2017 16:10:41 +0200","From":"Andrew Lunn ","To":"Michal Simek ","Cc":"Fahad Kunnathadi ,\n\tf.fainelli@gmail.com, netdev@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, soren.brinkmann@xilinx.com,\n\tlinux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH] net: phy: Fix mask value write on gmii2rgmii converter\n\tspeed register.","Message-ID":"<20170915141041.GE3084@lunn.ch>","References":"<1505373391-18697-1-git-send-email-fahad.kunnathadi@dexceldesigns.com>\n\t<20170914143454.GB27601@lunn.ch>\n\t<5f4bd003-d251-5a14-497a-9cc72dd0f160@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; 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