[{"id":1768324,"web_url":"http://patchwork.ozlabs.org/comment/1768324/","msgid":"","list_archive_url":null,"date":"2017-09-14T03:47:20","subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"Hi Igor,\n\nawesome clean refactor!\n\njust 1 comment inlined.\n\nOn 09/13/2017 01:04 PM, Igor Mammedov wrote:\n> there are 2 use cases to deal with:\n> 1: fixed CPU models per board/soc\n> 2: boards with user configurable cpu_model and fallback to\n> default cpu_model if user hasn't specified one explicitly\n> \n> For the 1st\n> drop intermediate cpu_model parsing and use const cpu type\n> directly, which replaces:\n> typename = object_class_get_name(\n> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> object_new(typename)\n> with\n> object_new(FOO_CPU_TYPE_NAME)\n> or\n> cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> with\n> cpu_create(FOO_CPU_TYPE_NAME)\n> \n> as result 1st use case doesn't have to invoke not necessary\n> translation and not needed code is removed.\n> \n> For the 2nd\n> 1: set default cpu type with MachineClass::default_cpu_type and\n> 2: use generic cpu_model parsing that done before machine_init()\n> is run and:\n> 2.1: drop custom cpu_model parsing where pattern is:\n> typename = object_class_get_name(\n> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> [parse_features(typename, cpu_model, &err) ]\n> \n> 2.2: or replace cpu_generic_init() which does what\n> 2.1 does + create_cpu(typename) with just\n> create_cpu(machine->cpu_type)\n> as result cpu_name -> cpu_type translation is done using\n> generic machine code one including parsing optional features\n> if supported/present (removes a bunch of duplicated cpu_model\n> parsing code) and default cpu type is defined in an uniform way\n> within machine_class_init callbacks instead of adhoc places\n> in boadr's machine_init code.\n> \n> Signed-off-by: Igor Mammedov \n> Reviewed-by: Eduardo Habkost \n> ---\n> v2:\n> - fix merge conflicts with ignore_memory_transaction_failures\n> - fix couple merge conflicts where SoC type string where replaced by type macro\n> - keep plain prefix string in: strncmp(cpu_type, \"pxa27\", 5)\n> - s/\"%s\" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME(\"%s\")/\n> ---\n> include/hw/arm/armv7m.h | 2 +-\n> include/hw/arm/aspeed_soc.h | 2 +-\n> include/hw/arm/stm32f205_soc.h | 2 +-\n> target/arm/cpu.h | 3 +++\n> hw/arm/armv7m.c | 40 +++++-------------------------------\n> hw/arm/aspeed_soc.c | 13 +++++-------\n> hw/arm/collie.c | 10 +++------\n> hw/arm/exynos4210.c | 6 +-----\n> hw/arm/gumstix.c | 5 +++--\n> hw/arm/highbank.c | 10 ++++-----\n> hw/arm/integratorcp.c | 30 ++-------------------------\n> hw/arm/mainstone.c | 9 ++++-----\n> hw/arm/mps2.c | 17 +++++++---------\n> hw/arm/musicpal.c | 7 ++-----\n> hw/arm/netduino2.c | 2 +-\n> hw/arm/nseries.c | 4 +++-\n> hw/arm/omap1.c | 7 ++-----\n> hw/arm/omap2.c | 4 ++--\n> hw/arm/omap_sx1.c | 5 ++++-\n> hw/arm/palm.c | 5 +++--\n> hw/arm/pxa2xx.c | 10 ++++-----\n> hw/arm/realview.c | 25 +++++------------------\n> hw/arm/spitz.c | 12 ++++++-----\n> hw/arm/stellaris.c | 16 +++++++--------\n> hw/arm/stm32f205_soc.c | 4 ++--\n> hw/arm/strongarm.c | 10 +++------\n> hw/arm/tosa.c | 4 ----\n> hw/arm/versatilepb.c | 15 +++-----------\n> hw/arm/vexpress.c | 32 +++++++++--------------------\n> hw/arm/virt.c | 46 +++++++++---------------------------------\n> hw/arm/xilinx_zynq.c | 10 ++-------\n> hw/arm/z2.c | 9 +++------\n> target/arm/cpu.c | 2 +-\n> 33 files changed, 114 insertions(+), 264 deletions(-)\n> \n> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h\n> index 10eb058..68cb30d 100644\n> --- a/include/hw/arm/armv7m.h\n> +++ b/include/hw/arm/armv7m.h\n> @@ -55,7 +55,7 @@ typedef struct ARMv7MState {\n> MemoryRegion container;\n> \n> /* Properties */\n> - char *cpu_model;\n> + char *cpu_type;\n> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */\n> MemoryRegion *board_memory;\n> } ARMv7MState;\n> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\n> index 0b88baa..f26914a 100644\n> --- a/include/hw/arm/aspeed_soc.h\n> +++ b/include/hw/arm/aspeed_soc.h\n> @@ -49,7 +49,7 @@ typedef struct AspeedSoCState {\n> \n> typedef struct AspeedSoCInfo {\n> const char *name;\n> - const char *cpu_model;\n> + const char *cpu_type;\n> uint32_t silicon_rev;\n> hwaddr sdram_base;\n> uint64_t sram_size;\n> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h\n> index e2dce11..922a733 100644\n> --- a/include/hw/arm/stm32f205_soc.h\n> +++ b/include/hw/arm/stm32f205_soc.h\n> @@ -52,7 +52,7 @@ typedef struct STM32F205State {\n> SysBusDevice parent_obj;\n> /*< public >*/\n> \n> - char *cpu_model;\n> + char *cpu_type;\n> \n> ARMv7MState armv7m;\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 98b9b26..1bfdd8d 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -2088,6 +2088,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,\n> \n> #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)\n> \n> +#define ARM_CPU_TYPE_SUFFIX \"-\" TYPE_ARM_CPU\n> +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)\n> +\n> #define cpu_signal_handler cpu_arm_signal_handler\n> #define cpu_list arm_cpu_list\n> \n> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c\n> index b64a409..57a6806 100644\n> --- a/hw/arm/armv7m.c\n> +++ b/hw/arm/armv7m.c\n> @@ -151,10 +151,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> SysBusDevice *sbd;\n> Error *err = NULL;\n> int i;\n> - char **cpustr;\n> - ObjectClass *oc;\n> - const char *typename;\n> - CPUClass *cc;\n> \n> if (!s->board_memory) {\n> error_setg(errp, \"memory property was not set\");\n> @@ -163,29 +159,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> \n> memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);\n> \n> - cpustr = g_strsplit(s->cpu_model, \",\", 2);\n> -\n> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!oc) {\n> - error_setg(errp, \"Unknown CPU model %s\", cpustr[0]);\n> - g_strfreev(cpustr);\n> - return;\n> - }\n> -\n> - cc = CPU_CLASS(oc);\n> - typename = object_class_get_name(oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_propagate(errp, err);\n> - return;\n> - }\n> -\n> - s->cpu = ARM_CPU(object_new(typename));\n> - if (!s->cpu) {\n> - error_setg(errp, \"Unknown CPU model %s\", s->cpu_model);\n> - return;\n> - }\n> + s->cpu = ARM_CPU(object_new(s->cpu_type));\n> \n> object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), \"memory\",\n> &error_abort);\n> @@ -241,7 +215,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> }\n> \n> static Property armv7m_properties[] = {\n> - DEFINE_PROP_STRING(\"cpu-model\", ARMv7MState, cpu_model),\n> + DEFINE_PROP_STRING(\"cpu-type\", ARMv7MState, cpu_type),\n> DEFINE_PROP_LINK(\"memory\", ARMv7MState, board_memory, TYPE_MEMORY_REGION,\n> MemoryRegion *),\n> DEFINE_PROP_END_OF_LIST(),\n> @@ -275,20 +249,16 @@ static void armv7m_reset(void *opaque)\n> Returns the ARMv7M device. */\n> \n> DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n> - const char *kernel_filename, const char *cpu_model)\n> + const char *kernel_filename, const char *cpu_type)\n> {\n> DeviceState *armv7m;\n> \n> - if (cpu_model == NULL) {\n> - cpu_model = \"cortex-m3\";\n> - }\n> -\n> armv7m = qdev_create(NULL, TYPE_ARMV7M);\n> qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n> - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n> object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n> \"memory\", &error_abort);\n> - /* This will exit with an error if the user passed us a bad cpu_model */\n> + /* This will exit with an error if the user passed us a bad cpu_type */\n> qdev_init_nofail(armv7m);\n> \n> armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);\n> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c\n> index 13c6393..5aa3d2d 100644\n> --- a/hw/arm/aspeed_soc.c\n> +++ b/hw/arm/aspeed_soc.c\n> @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {\n> static const AspeedSoCInfo aspeed_socs[] = {\n> {\n> .name = \"ast2400-a0\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A0_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2400-a1\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A1_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2400\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A0_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2500-a1\",\n> - .cpu_model = \"arm1176\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm1176\"),\n> .silicon_rev = AST2500_A1_SILICON_REV,\n> .sdram_base = AST2500_SDRAM_BASE,\n> .sram_size = 0x9000,\n> @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)\n> {\n> AspeedSoCState *s = ASPEED_SOC(obj);\n> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);\n> - char *cpu_typename;\n> int i;\n> \n> - cpu_typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, sc->info->cpu_model);\n> - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);\n> + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);\n> object_property_add_child(obj, \"cpu\", OBJECT(&s->cpu), NULL);\n> - g_free(cpu_typename);\n> \n> object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);\n> object_property_add_child(obj, \"vic\", OBJECT(&s->vic), NULL);\n> diff --git a/hw/arm/collie.c b/hw/arm/collie.c\n> index 8830192..f8c566e 100644\n> --- a/hw/arm/collie.c\n> +++ b/hw/arm/collie.c\n> @@ -18,7 +18,7 @@\n> #include \"hw/block/flash.h\"\n> #include \"sysemu/block-backend.h\"\n> #include \"exec/address-spaces.h\"\n> -#include \"qom/cpu.h\"\n> +#include \"cpu.h\"\n> \n> static struct arm_boot_info collie_binfo = {\n> .loader_start = SA_SDCS0,\n> @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {\n> \n> static void collie_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)\n> DriveInfo *dinfo;\n> MemoryRegion *sysmem = get_system_memory();\n> \n> - if (!cpu_model) {\n> - cpu_model = \"sa1110\";\n> - }\n> -\n> - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);\n> + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);\n> \n> dinfo = drive_get(IF_PFLASH, 0, 0);\n> pflash_cfi01_register(SA_CS0, NULL, \"collie.fl1\", 0x02000000,\n> @@ -65,6 +60,7 @@ static void collie_machine_init(MachineClass *mc)\n> mc->desc = \"Sharp SL-5500 (Collie) PDA (SA-1110)\";\n> mc->init = collie_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"sa1110\");\n> }\n> \n> DEFINE_MACHINE(\"collie\", collie_machine_init)\n> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c\n> index ee1438a..e8e1d81 100644\n> --- a/hw/arm/exynos4210.c\n> +++ b/hw/arm/exynos4210.c\n> @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)\n> Exynos4210State *s = g_new(Exynos4210State, 1);\n> qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];\n> SysBusDevice *busdev;\n> - ObjectClass *cpu_oc;\n> DeviceState *dev;\n> int i, n;\n> \n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, \"cortex-a9\");\n> - assert(cpu_oc);\n> -\n> for (n = 0; n < EXYNOS4210_NCPUS; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME(\"cortex-a9\"));\n> \n> /* By default A9 CPUs have EL3 enabled. This board does not currently\n> * support EL3 so the CPU EL3 property is disabled before realization.\n> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c\n> index 092ce36..bba9e9f 100644\n> --- a/hw/arm/gumstix.c\n> +++ b/hw/arm/gumstix.c\n> @@ -44,6 +44,7 @@\n> #include \"sysemu/block-backend.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n> \n> static const int sector_len = 128 * 1024;\n> \n> @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)\n> \n> static void verdex_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> PXA2xxState *cpu;\n> DriveInfo *dinfo;\n> int be;\n> @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)\n> uint32_t verdex_rom = 0x02000000;\n> uint32_t verdex_ram = 0x10000000;\n> \n> - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: \"pxa270-c0\");\n> + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);\n> \n> dinfo = drive_get(IF_PFLASH, 0, 0);\n> if (!dinfo && !qtest_enabled()) {\n> @@ -144,6 +144,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Gumstix Verdex (PXA270)\";\n> mc->init = verdex_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo verdex_type = {\n> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n> index ba27789..354c6b2 100644\n> --- a/hw/arm/highbank.c\n> +++ b/hw/arm/highbank.c\n> @@ -222,7 +222,6 @@ enum cxmachines {\n> static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -239,19 +238,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> \n> switch (machine_id) {\n> case CALXEDA_HIGHBANK:\n> - cpu_model = \"cortex-a9\";\n> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> break;\n> case CALXEDA_MIDWAY:\n> - cpu_model = \"cortex-a15\";\n> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> break;\n> + default:\n> + assert(0);\n> }\n> \n> for (n = 0; n < smp_cpus; n++) {\n> - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> Object *cpuobj;\n> ARMCPU *cpu;\n> \n> - cpuobj = object_new(object_class_get_name(oc));\n> + cpuobj = object_new(machine->cpu_type);\n> cpu = ARM_CPU(cpuobj);\n> \n> object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,\n> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c\n> index d603af9..e8303b8 100644\n> --- a/hw/arm/integratorcp.c\n> +++ b/hw/arm/integratorcp.c\n> @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {\n> static void integratorcp_init(MachineState *machine)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> - char **cpustr;\n> - ObjectClass *cpu_oc;\n> - CPUClass *cc;\n> Object *cpuobj;\n> ARMCPU *cpu;\n> - const char *typename;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *ram_alias = g_new(MemoryRegion, 1);\n> qemu_irq pic[32];\n> DeviceState *dev, *sic, *icp;\n> int i;\n> - Error *err = NULL;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"arm926\";\n> - }\n> -\n> - cpustr = g_strsplit(cpu_model, \",\", 2);\n> -\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> - typename = object_class_get_name(cpu_oc);\n> -\n> - cc = CPU_CLASS(cpu_oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_report_err(err);\n> - exit(1);\n> - }\n> -\n> - cpuobj = object_new(typename);\n> + cpuobj = object_new(machine->cpu_type);\n> \n> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -682,6 +655,7 @@ static void integratorcp_machine_init(MachineClass *mc)\n> mc->desc = \"ARM Integrator/CP (ARM926EJ-S)\";\n> mc->init = integratorcp_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> DEFINE_MACHINE(\"integratorcp\", integratorcp_machine_init)\n> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c\n> index 637f52c..d07972a 100644\n> --- a/hw/arm/mainstone.c\n> +++ b/hw/arm/mainstone.c\n> @@ -24,6 +24,7 @@\n> #include \"hw/sysbus.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n> \n> /* Device addresses */\n> #define MST_FPGA_PHYS\t0x08000000\n> @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,\n> int i;\n> int be;\n> MemoryRegion *rom = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> -\n> - if (!cpu_model)\n> - cpu_model = \"pxa270-c5\";\n> \n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,\n> + machine->cpu_type);\n> memory_region_init_ram(rom, NULL, \"mainstone.rom\", MAINSTONE_ROM,\n> &error_fatal);\n> memory_region_set_readonly(rom, true);\n> @@ -197,6 +195,7 @@ static void mainstone2_machine_init(MachineClass *mc)\n> mc->desc = \"Mainstone II (PXA27x)\";\n> mc->init = mainstone_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n> \n> DEFINE_MACHINE(\"mainstone\", mainstone2_machine_init)\n> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c\n> index abb0ab6..aeaad80 100644\n> --- a/hw/arm/mps2.c\n> +++ b/hw/arm/mps2.c\n> @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {\n> typedef struct {\n> MachineClass parent;\n> MPS2FPGAType fpga_type;\n> - const char *cpu_model;\n> uint32_t scc_id;\n> } MPS2MachineClass;\n> \n> @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)\n> MPS2MachineState *mms = MPS2_MACHINE(machine);\n> MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);\n> MemoryRegion *system_memory = get_system_memory();\n> + MachineClass *mc = MACHINE_GET_CLASS(machine);\n> DeviceState *armv7m, *sccdev;\n> \n> - if (!machine->cpu_model) {\n> - machine->cpu_model = mmc->cpu_model;\n> - }\n> -\n> - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {\n> - error_report(\"This board can only be used with CPU %s\", mmc->cpu_model);\n> + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {\n> + error_report(\"This board can only be used with CPU %s\",\n> + mc->default_cpu_type);\n> exit(1);\n> }\n> \n> @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)\n> default:\n> g_assert_not_reached();\n> }\n> - qdev_prop_set_string(armv7m, \"cpu-model\", machine->cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", machine->cpu_type);\n> object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),\n> \"memory\", &error_abort);\n> object_property_set_bool(OBJECT(&mms->armv7m), true, \"realized\",\n> @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"ARM MPS2 with AN385 FPGA image for Cortex-M3\";\n> mmc->fpga_type = FPGA_AN385;\n> - mmc->cpu_model = \"cortex-m3\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> mmc->scc_id = 0x41040000 | (385 << 4);\n> }\n> \n> @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)\n> \n> mc->desc = \"ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3\";\n> mmc->fpga_type = FPGA_AN511;\n> - mmc->cpu_model = \"cortex-m3\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> mmc->scc_id = 0x4104000 | (511 << 4);\n> }\n> \n> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c\n> index 7a6c0a6..b648770 100644\n> --- a/hw/arm/musicpal.c\n> +++ b/hw/arm/musicpal.c\n> @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {\n> \n> static void musicpal_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *sram = g_new(MemoryRegion, 1);\n> \n> - if (!cpu_model) {\n> - cpu_model = \"arm926\";\n> - }\n> - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));\n> + cpu = ARM_CPU(cpu_create(machine->cpu_type));\n> \n> /* For now we use a fixed - the original - RAM size */\n> memory_region_allocate_system_memory(ram, NULL, \"musicpal.ram\",\n> @@ -1715,6 +1711,7 @@ static void musicpal_machine_init(MachineClass *mc)\n> mc->desc = \"Marvell 88w8618 / MusicPal (ARM926EJ-S)\";\n> mc->init = musicpal_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> DEFINE_MACHINE(\"musicpal\", musicpal_machine_init)\n> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c\n> index 9d34d4c..f936017 100644\n> --- a/hw/arm/netduino2.c\n> +++ b/hw/arm/netduino2.c\n> @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)\n> DeviceState *dev;\n> \n> dev = qdev_create(NULL, TYPE_STM32F205_SOC);\n> - qdev_prop_set_string(dev, \"cpu-model\", \"cortex-m3\");\n> + qdev_prop_set_string(dev, \"cpu-type\", ARM_CPU_TYPE_NAME(\"cortex-m3\"));\n> object_property_set_bool(OBJECT(dev), true, \"realized\", &error_fatal);\n> \n> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,\n> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c\n> index a32ac82..58005b6 100644\n> --- a/hw/arm/nseries.c\n> +++ b/hw/arm/nseries.c\n> @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,\n> struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));\n> int sdram_size = binfo->ram_size;\n> \n> - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);\n> + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);\n> \n> /* Setup peripherals\n> *\n> @@ -1426,6 +1426,7 @@ static void n800_class_init(ObjectClass *oc, void *data)\n> mc->init = n800_init;\n> mc->default_boot_order = \"\";\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n> }\n> \n> static const TypeInfo n800_type = {\n> @@ -1442,6 +1443,7 @@ static void n810_class_init(ObjectClass *oc, void *data)\n> mc->init = n810_init;\n> mc->default_boot_order = \"\";\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n> }\n> \n> static const TypeInfo n810_type = {\n> diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c\n> index 04e65ce..b3e7625 100644\n> --- a/hw/arm/omap1.c\n> +++ b/hw/arm/omap1.c\n> @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,\n> \n> struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n> unsigned long sdram_size,\n> - const char *core)\n> + const char *cpu_type)\n> {\n> int i;\n> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n> @@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n> DriveInfo *dinfo;\n> SysBusDevice *busdev;\n> \n> - if (!core)\n> - core = \"ti925t\";\n> -\n> /* Core */\n> s->mpu_model = omap310;\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->sdram_size = sdram_size;\n> s->sram_size = OMAP15XX_SRAM_SIZE;\n> \n> diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c\n> index 5821477..3f6076e 100644\n> --- a/hw/arm/omap2.c\n> +++ b/hw/arm/omap2.c\n> @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {\n> \n> struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n> unsigned long sdram_size,\n> - const char *core)\n> + const char *cpu_type)\n> {\n> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n> qemu_irq dma_irqs[4];\n> @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n> \n> /* Core */\n> s->mpu_model = omap2420;\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: \"arm1136-r2\"));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->sdram_size = sdram_size;\n> s->sram_size = OMAP242X_SRAM_SIZE;\n> \n> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c\n> index 4535617..9a14270 100644\n> --- a/hw/arm/omap_sx1.c\n> +++ b/hw/arm/omap_sx1.c\n> @@ -36,6 +36,7 @@\n> #include \"sysemu/block-backend.h\"\n> #include \"sysemu/qtest.h\"\n> #include \"exec/address-spaces.h\"\n> +#include \"cpu.h\"\n> \n> /*****************************************************************************/\n> /* Siemens SX1 Cellphone V1 */\n> @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)\n> }\n> \n> mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,\n> - machine->cpu_model);\n> + machine->cpu_type);\n> \n> /* External Flash (EMIFS) */\n> memory_region_init_ram(flash, NULL, \"omap_sx1.flash0-0\", flash_size,\n> @@ -224,6 +225,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Siemens SX1 (OMAP310) V2\";\n> mc->init = sx1_init_v2;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n> \n> static const TypeInfo sx1_machine_v2_type = {\n> @@ -239,6 +241,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Siemens SX1 (OMAP310) V1\";\n> mc->init = sx1_init_v1;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n> \n> static const TypeInfo sx1_machine_v1_type = {\n> diff --git a/hw/arm/palm.c b/hw/arm/palm.c\n> index bf070a2..b8753e2 100644\n> --- a/hw/arm/palm.c\n> +++ b/hw/arm/palm.c\n> @@ -29,6 +29,7 @@\n> #include \"hw/devices.h\"\n> #include \"hw/loader.h\"\n> #include \"exec/address-spaces.h\"\n> +#include \"cpu.h\"\n> \n> static uint32_t static_readb(void *opaque, hwaddr offset)\n> {\n> @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {\n> \n> static void palmte_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)\n> MemoryRegion *flash = g_new(MemoryRegion, 1);\n> MemoryRegion *cs = g_new(MemoryRegion, 4);\n> \n> - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);\n> + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);\n> \n> /* External Flash (EMIFS) */\n> memory_region_init_ram(flash, NULL, \"palmte.flash\", flash_size,\n> @@ -275,6 +275,7 @@ static void palmte_machine_init(MachineClass *mc)\n> mc->desc = \"Palm Tungsten|E aka. Cheetah PDA (OMAP310)\";\n> mc->init = palmte_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n> \n> DEFINE_MACHINE(\"cheetah\", palmte_machine_init)\n> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n> index c16657d..cf07234 100644\n> --- a/hw/arm/pxa2xx.c\n> +++ b/hw/arm/pxa2xx.c\n> @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n> \n> /* Initialise a PXA270 integrated chip (ARM based core). */\n> PXA2xxState *pxa270_init(MemoryRegion *address_space,\n> - unsigned int sdram_size, const char *revision)\n> + unsigned int sdram_size, const char *cpu_type)\n> {\n> PXA2xxState *s;\n> int i;\n> DriveInfo *dinfo;\n> s = g_new0(PXA2xxState, 1);\n> \n> - if (revision && strncmp(revision, \"pxa27\", 5)) {\n> + if (strncmp(cpu_type, \"pxa27\", 5)) {\n> fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n> exit(1);\n> }\n> - if (!revision)\n> - revision = \"pxa270\";\n> \n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n> \n> /* SDRAM & Internal Memory Storage */\n> @@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)\n> \n> s = g_new0(PXA2xxState, 1);\n> \n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, \"pxa255\"));\n> + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME(\"pxa255\")));\n> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n> \n> /* SDRAM & Internal Memory Storage */\n> diff --git a/hw/arm/realview.c b/hw/arm/realview.c\n> index f3a49b6..87cd1e5 100644\n> --- a/hw/arm/realview.c\n> +++ b/hw/arm/realview.c\n> @@ -57,7 +57,6 @@ static void realview_init(MachineState *machine,\n> {\n> ARMCPU *cpu = NULL;\n> CPUARMState *env;\n> - ObjectClass *cpu_oc;\n> MemoryRegion *sysmem = get_system_memory();\n> MemoryRegion *ram_lo;\n> MemoryRegion *ram_hi = g_new(MemoryRegion, 1);\n> @@ -98,14 +97,8 @@ static void realview_init(MachineState *machine,\n> break;\n> }\n> \n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> for (n = 0; n < smp_cpus; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(machine->cpu_type);\n> \n> /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board\n> * does not currently support EL3 so the CPU EL3 property is disabled\n> @@ -361,33 +354,21 @@ static void realview_init(MachineState *machine,\n> \n> static void realview_eb_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm926\";\n> - }\n> realview_init(machine, BOARD_EB);\n> }\n> \n> static void realview_eb_mpcore_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm11mpcore\";\n> - }\n> realview_init(machine, BOARD_EB_MPCORE);\n> }\n> \n> static void realview_pb_a8_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"cortex-a8\";\n> - }\n> realview_init(machine, BOARD_PB_A8);\n> }\n> \n> static void realview_pbx_a9_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"cortex-a9\";\n> - }\n> realview_init(machine, BOARD_PBX_A9);\n> }\n> \n> @@ -399,6 +380,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)\n> mc->init = realview_eb_init;\n> mc->block_default_type = IF_SCSI;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> static const TypeInfo realview_eb_type = {\n> @@ -416,6 +398,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)\n> mc->block_default_type = IF_SCSI;\n> mc->max_cpus = 4;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm11mpcore\");\n> }\n> \n> static const TypeInfo realview_eb_mpcore_type = {\n> @@ -431,6 +414,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"ARM RealView Platform Baseboard for Cortex-A8\";\n> mc->init = realview_pb_a8_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a8\");\n> }\n> \n> static const TypeInfo realview_pb_a8_type = {\n> @@ -447,6 +431,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)\n> mc->init = realview_pbx_a9_init;\n> mc->max_cpus = 4;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> }\n> \n> static const TypeInfo realview_pbx_a9_type = {\n> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c\n> index 6406421..feccdb0 100644\n> --- a/hw/arm/spitz.c\n> +++ b/hw/arm/spitz.c\n> @@ -30,6 +30,7 @@\n> #include \"hw/sysbus.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/sysemu.h\"\n> +#include \"cpu.h\"\n> \n> #undef REG_FMT\n> #define REG_FMT\t\t\t\"0x%02lx\"\n> @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,\n> DeviceState *scp0, *scp1 = NULL;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *rom = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> -\n> - if (!cpu_model)\n> - cpu_model = (model == terrier) ? \"pxa270-c5\" : \"pxa270-c0\";\n> \n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,\n> + machine->cpu_type);\n> \n> sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);\n> \n> @@ -984,6 +982,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Sharp SL-C1000 (Akita) PDA (PXA270)\";\n> mc->init = akita_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo akitapda_type = {\n> @@ -1000,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)\n> mc->init = spitz_init;\n> mc->block_default_type = IF_IDE;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo spitzpda_type = {\n> @@ -1016,6 +1016,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)\n> mc->init = borzoi_init;\n> mc->block_default_type = IF_IDE;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n> \n> static const TypeInfo borzoipda_type = {\n> @@ -1032,6 +1033,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)\n> mc->init = terrier_init;\n> mc->block_default_type = IF_IDE;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n> \n> static const TypeInfo terrierpda_type = {\n> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c\n> index b3aad23..de7c0fc 100644\n> --- a/hw/arm/stellaris.c\n> +++ b/hw/arm/stellaris.c\n> @@ -22,6 +22,7 @@\n> #include \"sysemu/sysemu.h\"\n> #include \"hw/char/pl011.h\"\n> #include \"hw/misc/unimp.h\"\n> +#include \"cpu.h\"\n> \n> #define GPIO_A 0\n> #define GPIO_B 1\n> @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {\n> }\n> };\n> \n> -static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> - stellaris_board_info *board)\n> +static void stellaris_init(MachineState *ms, stellaris_board_info *board)\n> {\n> static const int uart_irq[] = {5, 6, 33, 34};\n> static const int timer_irq[] = {19, 21, 23, 35};\n> @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> memory_region_add_subregion(system_memory, 0x20000000, sram);\n> \n> nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,\n> - kernel_filename, cpu_model);\n> + ms->kernel_filename, ms->cpu_type);\n> \n> qdev_connect_gpio_out_named(nvic, \"SYSRESETREQ\", 0,\n> qemu_allocate_irq(&do_sys_reset, NULL, 0));\n> @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> /* FIXME: Figure out how to generate these from stellaris_boards. */\n> static void lm3s811evb_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> - const char *kernel_filename = machine->kernel_filename;\n> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);\n> + stellaris_init(machine, &stellaris_boards[0]);\n> }\n> \n> static void lm3s6965evb_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> - const char *kernel_filename = machine->kernel_filename;\n> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);\n> + stellaris_init(machine, &stellaris_boards[1]);\n> }\n> \n> static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n> @@ -1454,6 +1450,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Stellaris LM3S811EVB\";\n> mc->init = lm3s811evb_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> }\n> \n> static const TypeInfo lm3s811evb_type = {\n> @@ -1469,6 +1466,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Stellaris LM3S6965EVB\";\n> mc->init = lm3s6965evb_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> }\n> \n> static const TypeInfo lm3s6965evb_type = {\n> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> index f61e735..1cd6374 100644\n> --- a/hw/arm/stm32f205_soc.c\n> +++ b/hw/arm/stm32f205_soc.c\n> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> \n> armv7m = DEVICE(&s->armv7m);\n> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> \"memory\", &error_abort);\n> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> }\n> \n> static Property stm32f205_soc_properties[] = {\n> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n> DEFINE_PROP_END_OF_LIST(),\n> };\n> \n> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c\n> index c1145dd..3d1a231 100644\n> --- a/hw/arm/strongarm.c\n> +++ b/hw/arm/strongarm.c\n> @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {\n> \n> /* Main CPU functions */\n> StrongARMState *sa1110_init(MemoryRegion *sysmem,\n> - unsigned int sdram_size, const char *rev)\n> + unsigned int sdram_size, const char *cpu_type)\n> {\n> StrongARMState *s;\n> int i;\n> \n> s = g_new0(StrongARMState, 1);\n> \n> - if (!rev) {\n> - rev = \"sa1110-b5\";\n> - }\n> -\n> - if (strncmp(rev, \"sa1110\", 6)) {\n> + if (strncmp(cpu_type, \"sa1110\", 6)) {\n> error_report(\"Machine requires a SA1110 processor.\");\n> exit(1);\n> }\n> \n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> \n> memory_region_allocate_system_memory(&s->sdram, NULL, \"strongarm.sdram\",\n> sdram_size);\n> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c\n> index 1134cf7..0447963 100644\n> --- a/hw/arm/tosa.c\n> +++ b/hw/arm/tosa.c\n> @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {\n> \n> static void tosa_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)\n> TC6393xbState *tmio;\n> DeviceState *scp0, *scp1;\n> \n> - if (!cpu_model)\n> - cpu_model = \"pxa255\";\n> -\n> mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);\n> \n> memory_region_init_ram(rom, NULL, \"tosa.rom\", TOSA_ROM, &error_fatal);\n> diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c\n> index 76664e4..418792c 100644\n> --- a/hw/arm/versatilepb.c\n> +++ b/hw/arm/versatilepb.c\n> @@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo;\n> \n> static void versatile_init(MachineState *machine, int board_id)\n> {\n> - ObjectClass *cpu_oc;\n> Object *cpuobj;\n> ARMCPU *cpu;\n> MemoryRegion *sysmem = get_system_memory();\n> @@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id)\n> exit(1);\n> }\n> \n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm926\";\n> - }\n> -\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> - cpuobj = object_new(object_class_get_name(cpu_oc));\n> + cpuobj = object_new(machine->cpu_type);\n> \n> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -404,6 +393,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)\n> mc->init = vpb_init;\n> mc->block_default_type = IF_SCSI;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> static const TypeInfo versatilepb_type = {\n> @@ -420,6 +410,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)\n> mc->init = vab_init;\n> mc->block_default_type = IF_SCSI;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n> \n> static const TypeInfo versatileab_type = {\n> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c\n> index e3acab6..2e5f670 100644\n> --- a/hw/arm/vexpress.c\n> +++ b/hw/arm/vexpress.c\n> @@ -186,7 +186,7 @@ typedef struct {\n> \n> typedef void DBoardInitFn(const VexpressMachineState *machine,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic);\n> \n> struct VEDBoardInfo {\n> @@ -202,22 +202,16 @@ struct VEDBoardInfo {\n> DBoardInitFn *init;\n> };\n> \n> -static void init_cpus(const char *cpu_model, const char *privdev,\n> +static void init_cpus(const char *cpu_type, const char *privdev,\n> hwaddr periphbase, qemu_irq *pic, bool secure)\n> {\n> - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> DeviceState *dev;\n> SysBusDevice *busdev;\n> int n;\n> \n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> /* Create the actual CPUs */\n> for (n = 0; n < smp_cpus; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(cpu_type);\n> \n> if (!secure) {\n> object_property_set_bool(cpuobj, false, \"has_el3\", NULL);\n> @@ -262,7 +256,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,\n> \n> static void a9_daughterboard_init(const VexpressMachineState *vms,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic)\n> {\n> MemoryRegion *sysmem = get_system_memory();\n> @@ -270,10 +264,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n> MemoryRegion *lowram = g_new(MemoryRegion, 1);\n> ram_addr_t low_ram_size;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a9\";\n> - }\n> -\n> if (ram_size > 0x40000000) {\n> /* 1GB is the maximum the address space permits */\n> fprintf(stderr, \"vexpress-a9: cannot model more than 1GB RAM\\n\");\n> @@ -295,7 +285,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n> memory_region_add_subregion(sysmem, 0x60000000, ram);\n> \n> /* 0x1e000000 A9MPCore (SCU) private memory region */\n> - init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);\n> + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);\n> \n> /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */\n> \n> @@ -351,17 +341,13 @@ static VEDBoardInfo a9_daughterboard = {\n> \n> static void a15_daughterboard_init(const VexpressMachineState *vms,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic)\n> {\n> MemoryRegion *sysmem = get_system_memory();\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *sram = g_new(MemoryRegion, 1);\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a15\";\n> - }\n> -\n> {\n> /* We have to use a separate 64 bit variable here to avoid the gcc\n> * \"comparison is always false due to limited range of data type\"\n> @@ -380,7 +366,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,\n> memory_region_add_subregion(sysmem, 0x80000000, ram);\n> \n> /* 0x2c000000 A15MPCore private memory region (GIC) */\n> - init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);\n> + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);\n> \n> /* A15 daughterboard peripherals: */\n> \n> @@ -560,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)\n> const hwaddr *map = daughterboard->motherboard_map;\n> int i;\n> \n> - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);\n> + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);\n> \n> /*\n> * If a bios file was provided, attempt to map it into memory\n> @@ -761,6 +747,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)\n> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);\n> \n> mc->desc = \"ARM Versatile Express for Cortex-A9\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> \n> vmc->daughterboard = &a9_daughterboard;\n> }\n> @@ -771,6 +758,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)\n> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);\n> \n> mc->desc = \"ARM Versatile Express for Cortex-A15\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> \n> vmc->daughterboard = &a15_daughterboard;\n> }\n> diff --git a/hw/arm/virt.c b/hw/arm/virt.c\n> index fe96557..fe26e99 100644\n> --- a/hw/arm/virt.c\n> +++ b/hw/arm/virt.c\n> @@ -163,13 +163,13 @@ static const int a15irqmap[] = {\n> };\n> \n> static const char *valid_cpus[] = {\n> - \"cortex-a15\",\n> - \"cortex-a53\",\n> - \"cortex-a57\",\n> - \"host\",\n> + ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n> + ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n> + ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n> + ARM_CPU_TYPE_NAME(\"host\"),\n> };\n> \n> -static bool cpuname_valid(const char *cpu)\n> +static bool cpu_type_valid(const char *cpu)\n> {\n> int i;\n\nI'd just change this by:\n\nstatic bool cpuname_valid(const char *cpu)\n{\n static const char *valid_cpus[] = {\n ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n };\n int i;\n\n for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {\n if (strcmp(cpu, valid_cpus[i]) == 0) {\n return true;\n }\n }\n return kvm_enabled() && !strcmp(cpu, ARM_CPU_TYPE_NAME(\"host\");\n}\n\nAnyway this can be a later patch.\n\nReviewed-by: Philippe Mathieu-Daudé \n\n> \n> @@ -1258,18 +1258,8 @@ static void machvirt_init(MachineState *machine)\n> MemoryRegion *secure_sysmem = NULL;\n> int n, virt_max_cpus;\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> - char **cpustr;\n> - ObjectClass *oc;\n> - const char *typename;\n> - CPUClass *cc;\n> - Error *err = NULL;\n> bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a15\";\n> - }\n> -\n> /* We can probe only here because during property set\n> * KVM is not available yet\n> */\n> @@ -1286,11 +1276,8 @@ static void machvirt_init(MachineState *machine)\n> }\n> }\n> \n> - /* Separate the actual CPU model name from any appended features */\n> - cpustr = g_strsplit(cpu_model, \",\", 2);\n> -\n> - if (!cpuname_valid(cpustr[0])) {\n> - error_report(\"mach-virt: CPU %s not supported\", cpustr[0]);\n> + if (!cpu_type_valid(machine->cpu_type)) {\n> + error_report(\"mach-virt: CPU type %s not supported\", machine->cpu_type);\n> exit(1);\n> }\n> \n> @@ -1360,22 +1347,6 @@ static void machvirt_init(MachineState *machine)\n> \n> create_fdt(vms);\n> \n> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!oc) {\n> - error_report(\"Unable to find CPU definition\");\n> - exit(1);\n> - }\n> - typename = object_class_get_name(oc);\n> -\n> - /* convert -smp CPU options specified by the user into global props */\n> - cc = CPU_CLASS(oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_report_err(err);\n> - exit(1);\n> - }\n> -\n> possible_cpus = mc->possible_cpu_arch_ids(machine);\n> for (n = 0; n < possible_cpus->len; n++) {\n> Object *cpuobj;\n> @@ -1385,7 +1356,7 @@ static void machvirt_init(MachineState *machine)\n> break;\n> }\n> \n> - cpuobj = object_new(typename);\n> + cpuobj = object_new(machine->cpu_type);\n> object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,\n> \"mp-affinity\", NULL);\n> \n> @@ -1630,6 +1601,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)\n> mc->minimum_page_bits = 12;\n> mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;\n> mc->cpu_index_to_instance_props = virt_cpu_index_to_props;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> }\n> \n> static const TypeInfo virt_machine_info = {\n> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c\n> index 3759cf8..1836a4e 100644\n> --- a/hw/arm/xilinx_zynq.c\n> +++ b/hw/arm/xilinx_zynq.c\n> @@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,\n> static void zynq_init(MachineState *machine)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> - ObjectClass *cpu_oc;\n> ARMCPU *cpu;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *ext_ram = g_new(MemoryRegion, 1);\n> @@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine)\n> qemu_irq pic[64];\n> int n;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a9\";\n> - }\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> -\n> - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));\n> + cpu = ARM_CPU(object_new(machine->cpu_type));\n> \n> /* By default A9 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc)\n> mc->max_cpus = 1;\n> mc->no_sdcard = 1;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> }\n> \n> DEFINE_MACHINE(\"xilinx-zynq-a9\", zynq_machine_init)\n> diff --git a/hw/arm/z2.c b/hw/arm/z2.c\n> index 417bc1a..60561c7 100644\n> --- a/hw/arm/z2.c\n> +++ b/hw/arm/z2.c\n> @@ -26,6 +26,7 @@\n> #include \"audio/audio.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n> \n> #ifdef DEBUG_Z2\n> #define DPRINTF(fmt, ...) \\\n> @@ -296,7 +297,6 @@ static const TypeInfo aer915_info = {\n> \n> static void z2_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -309,12 +309,8 @@ static void z2_init(MachineState *machine)\n> I2CBus *bus;\n> DeviceState *wm;\n> \n> - if (!cpu_model) {\n> - cpu_model = \"pxa270-c5\";\n> - }\n> -\n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);\n> \n> #ifdef TARGET_WORDS_BIGENDIAN\n> be = 1;\n> @@ -371,6 +367,7 @@ static void z2_machine_init(MachineClass *mc)\n> mc->desc = \"Zipit Z2 (PXA27x)\";\n> mc->init = z2_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n> \n> DEFINE_MACHINE(\"z2\", z2_machine_init)\n> diff --git a/target/arm/cpu.c b/target/arm/cpu.c\n> index a1acce3..ff7ff28 100644\n> --- a/target/arm/cpu.c\n> +++ b/target/arm/cpu.c\n> @@ -905,7 +905,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)\n> }\n> \n> cpuname = g_strsplit(cpu_model, \",\", 1);\n> - typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, cpuname[0]);\n> + typename = g_strdup_printf(ARM_CPU_TYPE_NAME(\"%s\"), cpuname[0]);\n> oc = object_class_by_name(typename);\n> g_strfreev(cpuname);\n> g_free(typename);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"nEwBvcoE\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org 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qemu-arm@nongnu.org","References":"<1505318697-77161-1-git-send-email-imammedo@redhat.com>\n\t<1505318697-77161-6-git-send-email-imammedo@redhat.com>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"","Date":"Thu, 14 Sep 2017 00:47:20 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1505318697-77161-6-git-send-email-imammedo@redhat.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::243","Subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1768386,"web_url":"http://patchwork.ozlabs.org/comment/1768386/","msgid":"<20170914095011.2fba8aab@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-14T07:50:11","subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Thu, 14 Sep 2017 00:47:20 -0300\nPhilippe Mathieu-Daudé wrote:\n\n> Hi Igor,\n> \n> awesome clean refactor!\nThanks,\n\nthere is more patches on this topic for other targets to post\nbut it's waiting on 1-3/5 to land in master so it would be\neasier for maintainers to verify/test them without fishing out\ndependencies from mail list.\n\nhopefully everything will land in 2.11 so we won't have to deal\nwith cpu_model anywhere except of one place vl.c.\n\n> just 1 comment inlined.\n> \n> On 09/13/2017 01:04 PM, Igor Mammedov wrote:\n> > there are 2 use cases to deal with:\n> > 1: fixed CPU models per board/soc\n> > 2: boards with user configurable cpu_model and fallback to\n> > default cpu_model if user hasn't specified one explicitly\n> > \n> > For the 1st\n> > drop intermediate cpu_model parsing and use const cpu type\n> > directly, which replaces:\n> > typename = object_class_get_name(\n> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > object_new(typename)\n> > with\n> > object_new(FOO_CPU_TYPE_NAME)\n> > or\n> > cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> > with\n> > cpu_create(FOO_CPU_TYPE_NAME)\n> > \n> > as result 1st use case doesn't have to invoke not necessary\n> > translation and not needed code is removed.\n> > \n> > For the 2nd\n> > 1: set default cpu type with MachineClass::default_cpu_type and\n> > 2: use generic cpu_model parsing that done before machine_init()\n> > is run and:\n> > 2.1: drop custom cpu_model parsing where pattern is:\n> > typename = object_class_get_name(\n> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> > [parse_features(typename, cpu_model, &err) ]\n> > \n> > 2.2: or replace cpu_generic_init() which does what\n> > 2.1 does + create_cpu(typename) with just\n> > create_cpu(machine->cpu_type)\n> > as result cpu_name -> cpu_type translation is done using\n> > generic machine code one including parsing optional features\n> > if supported/present (removes a bunch of duplicated cpu_model\n> > parsing code) and default cpu type is defined in an uniform way\n> > within machine_class_init callbacks instead of adhoc places\n> > in boadr's machine_init code.\n> > \n> > Signed-off-by: Igor Mammedov \n> > Reviewed-by: Eduardo Habkost \n> > ---\n> > v2:\n> > - fix merge conflicts with ignore_memory_transaction_failures\n> > - fix couple merge conflicts where SoC type string where replaced by type macro\n> > - keep plain prefix string in: strncmp(cpu_type, \"pxa27\", 5)\n> > - s/\"%s\" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME(\"%s\")/\n> > ---\n[...]\n\n> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c\n> > index fe96557..fe26e99 100644\n> > --- a/hw/arm/virt.c\n> > +++ b/hw/arm/virt.c\n> > @@ -163,13 +163,13 @@ static const int a15irqmap[] = {\n> > };\n> > \n> > static const char *valid_cpus[] = {\n> > - \"cortex-a15\",\n> > - \"cortex-a53\",\n> > - \"cortex-a57\",\n> > - \"host\",\n> > + ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n> > + ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n> > + ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n> > + ARM_CPU_TYPE_NAME(\"host\"),\n> > };\n> > \n> > -static bool cpuname_valid(const char *cpu)\n> > +static bool cpu_type_valid(const char *cpu)\n> > {\n> > int i; \n> \n> I'd just change this by:\n> \n> static bool cpuname_valid(const char *cpu)\n> {\n> static const char *valid_cpus[] = {\n> ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n> ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n> ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n> };\n> int i;\n> \n> for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {\n> if (strcmp(cpu, valid_cpus[i]) == 0) {\n> return true;\n> }\n> }\n\n> return kvm_enabled() && !strcmp(cpu, ARM_CPU_TYPE_NAME(\"host\");\nhere is one more case to consider for valid_cpus refactoring,\nCCing Alistair.\n\n> }\n> \n> Anyway this can be a later patch.\nthis check might be removed or superseded by generic valid_cpus work\nthat Alistair is working on, anyways it should be part of that work\nas change is not directly related to this series.\n\n\n[...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dsOui-0005tV-0t\n\tfor qemu-devel@nongnu.org; Thu, 14 Sep 2017 03:50:21 -0400","from mx1.redhat.com ([209.132.183.28]:58230)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dsOuc-0005in-Sj; Thu, 14 Sep 2017 03:50:15 -0400","from smtp.corp.redhat.com\n\t(int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id D1C5037E65;\n\tThu, 14 Sep 2017 07:50:13 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id D412F756BF;\n\tThu, 14 Sep 2017 07:50:12 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com D1C5037E65","Date":"Thu, 14 Sep 2017 09:50:11 +0200","From":"Igor Mammedov ","To":"Philippe =?utf-8?q?Mathieu-Daud=C3=A9?= ","Message-ID":"<20170914095011.2fba8aab@nial.brq.redhat.com>","In-Reply-To":"","References":"<1505318697-77161-1-git-send-email-imammedo@redhat.com>\n\t<1505318697-77161-6-git-send-email-imammedo@redhat.com>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"quoted-printable","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.12","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.29]);\n\tThu, 14 Sep 2017 07:50:14 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis , qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1768763,"web_url":"http://patchwork.ozlabs.org/comment/1768763/","msgid":"","list_archive_url":null,"date":"2017-09-14T17:57:20","subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Wed, Sep 13, 2017 at 9:04 AM, Igor Mammedov wrote:\n> there are 2 use cases to deal with:\n> 1: fixed CPU models per board/soc\n> 2: boards with user configurable cpu_model and fallback to\n> default cpu_model if user hasn't specified one explicitly\n>\n> For the 1st\n> drop intermediate cpu_model parsing and use const cpu type\n> directly, which replaces:\n> typename = object_class_get_name(\n> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> object_new(typename)\n> with\n> object_new(FOO_CPU_TYPE_NAME)\n> or\n> cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n> with\n> cpu_create(FOO_CPU_TYPE_NAME)\n>\n> as result 1st use case doesn't have to invoke not necessary\n> translation and not needed code is removed.\n>\n> For the 2nd\n> 1: set default cpu type with MachineClass::default_cpu_type and\n> 2: use generic cpu_model parsing that done before machine_init()\n> is run and:\n> 2.1: drop custom cpu_model parsing where pattern is:\n> typename = object_class_get_name(\n> cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n> [parse_features(typename, cpu_model, &err) ]\n>\n> 2.2: or replace cpu_generic_init() which does what\n> 2.1 does + create_cpu(typename) with just\n> create_cpu(machine->cpu_type)\n> as result cpu_name -> cpu_type translation is done using\n> generic machine code one including parsing optional features\n> if supported/present (removes a bunch of duplicated cpu_model\n> parsing code) and default cpu type is defined in an uniform way\n> within machine_class_init callbacks instead of adhoc places\n> in boadr's machine_init code.\n>\n> Signed-off-by: Igor Mammedov \n> Reviewed-by: Eduardo Habkost \n\nFox the Xilinx and Netduino stuff:\n\nReviewed-by: Alistair Francis \n\nThanks,\nAlistair\n\n> ---\n> v2:\n> - fix merge conflicts with ignore_memory_transaction_failures\n> - fix couple merge conflicts where SoC type string where replaced by type macro\n> - keep plain prefix string in: strncmp(cpu_type, \"pxa27\", 5)\n> - s/\"%s\" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME(\"%s\")/\n> ---\n> include/hw/arm/armv7m.h | 2 +-\n> include/hw/arm/aspeed_soc.h | 2 +-\n> include/hw/arm/stm32f205_soc.h | 2 +-\n> target/arm/cpu.h | 3 +++\n> hw/arm/armv7m.c | 40 +++++-------------------------------\n> hw/arm/aspeed_soc.c | 13 +++++-------\n> hw/arm/collie.c | 10 +++------\n> hw/arm/exynos4210.c | 6 +-----\n> hw/arm/gumstix.c | 5 +++--\n> hw/arm/highbank.c | 10 ++++-----\n> hw/arm/integratorcp.c | 30 ++-------------------------\n> hw/arm/mainstone.c | 9 ++++-----\n> hw/arm/mps2.c | 17 +++++++---------\n> hw/arm/musicpal.c | 7 ++-----\n> hw/arm/netduino2.c | 2 +-\n> hw/arm/nseries.c | 4 +++-\n> hw/arm/omap1.c | 7 ++-----\n> hw/arm/omap2.c | 4 ++--\n> hw/arm/omap_sx1.c | 5 ++++-\n> hw/arm/palm.c | 5 +++--\n> hw/arm/pxa2xx.c | 10 ++++-----\n> hw/arm/realview.c | 25 +++++------------------\n> hw/arm/spitz.c | 12 ++++++-----\n> hw/arm/stellaris.c | 16 +++++++--------\n> hw/arm/stm32f205_soc.c | 4 ++--\n> hw/arm/strongarm.c | 10 +++------\n> hw/arm/tosa.c | 4 ----\n> hw/arm/versatilepb.c | 15 +++-----------\n> hw/arm/vexpress.c | 32 +++++++++--------------------\n> hw/arm/virt.c | 46 +++++++++---------------------------------\n> hw/arm/xilinx_zynq.c | 10 ++-------\n> hw/arm/z2.c | 9 +++------\n> target/arm/cpu.c | 2 +-\n> 33 files changed, 114 insertions(+), 264 deletions(-)\n>\n> diff --git a/include/hw/arm/armv7m.h b/include/hw/arm/armv7m.h\n> index 10eb058..68cb30d 100644\n> --- a/include/hw/arm/armv7m.h\n> +++ b/include/hw/arm/armv7m.h\n> @@ -55,7 +55,7 @@ typedef struct ARMv7MState {\n> MemoryRegion container;\n>\n> /* Properties */\n> - char *cpu_model;\n> + char *cpu_type;\n> /* MemoryRegion the board provides to us (with its devices, RAM, etc) */\n> MemoryRegion *board_memory;\n> } ARMv7MState;\n> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h\n> index 0b88baa..f26914a 100644\n> --- a/include/hw/arm/aspeed_soc.h\n> +++ b/include/hw/arm/aspeed_soc.h\n> @@ -49,7 +49,7 @@ typedef struct AspeedSoCState {\n>\n> typedef struct AspeedSoCInfo {\n> const char *name;\n> - const char *cpu_model;\n> + const char *cpu_type;\n> uint32_t silicon_rev;\n> hwaddr sdram_base;\n> uint64_t sram_size;\n> diff --git a/include/hw/arm/stm32f205_soc.h b/include/hw/arm/stm32f205_soc.h\n> index e2dce11..922a733 100644\n> --- a/include/hw/arm/stm32f205_soc.h\n> +++ b/include/hw/arm/stm32f205_soc.h\n> @@ -52,7 +52,7 @@ typedef struct STM32F205State {\n> SysBusDevice parent_obj;\n> /*< public >*/\n>\n> - char *cpu_model;\n> + char *cpu_type;\n>\n> ARMv7MState armv7m;\n>\n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 98b9b26..1bfdd8d 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -2088,6 +2088,9 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,\n>\n> #define cpu_init(cpu_model) cpu_generic_init(TYPE_ARM_CPU, cpu_model)\n>\n> +#define ARM_CPU_TYPE_SUFFIX \"-\" TYPE_ARM_CPU\n> +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)\n> +\n> #define cpu_signal_handler cpu_arm_signal_handler\n> #define cpu_list arm_cpu_list\n>\n> diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c\n> index b64a409..57a6806 100644\n> --- a/hw/arm/armv7m.c\n> +++ b/hw/arm/armv7m.c\n> @@ -151,10 +151,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> SysBusDevice *sbd;\n> Error *err = NULL;\n> int i;\n> - char **cpustr;\n> - ObjectClass *oc;\n> - const char *typename;\n> - CPUClass *cc;\n>\n> if (!s->board_memory) {\n> error_setg(errp, \"memory property was not set\");\n> @@ -163,29 +159,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n>\n> memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);\n>\n> - cpustr = g_strsplit(s->cpu_model, \",\", 2);\n> -\n> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!oc) {\n> - error_setg(errp, \"Unknown CPU model %s\", cpustr[0]);\n> - g_strfreev(cpustr);\n> - return;\n> - }\n> -\n> - cc = CPU_CLASS(oc);\n> - typename = object_class_get_name(oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_propagate(errp, err);\n> - return;\n> - }\n> -\n> - s->cpu = ARM_CPU(object_new(typename));\n> - if (!s->cpu) {\n> - error_setg(errp, \"Unknown CPU model %s\", s->cpu_model);\n> - return;\n> - }\n> + s->cpu = ARM_CPU(object_new(s->cpu_type));\n>\n> object_property_set_link(OBJECT(s->cpu), OBJECT(&s->container), \"memory\",\n> &error_abort);\n> @@ -241,7 +215,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp)\n> }\n>\n> static Property armv7m_properties[] = {\n> - DEFINE_PROP_STRING(\"cpu-model\", ARMv7MState, cpu_model),\n> + DEFINE_PROP_STRING(\"cpu-type\", ARMv7MState, cpu_type),\n> DEFINE_PROP_LINK(\"memory\", ARMv7MState, board_memory, TYPE_MEMORY_REGION,\n> MemoryRegion *),\n> DEFINE_PROP_END_OF_LIST(),\n> @@ -275,20 +249,16 @@ static void armv7m_reset(void *opaque)\n> Returns the ARMv7M device. */\n>\n> DeviceState *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq,\n> - const char *kernel_filename, const char *cpu_model)\n> + const char *kernel_filename, const char *cpu_type)\n> {\n> DeviceState *armv7m;\n>\n> - if (cpu_model == NULL) {\n> - cpu_model = \"cortex-m3\";\n> - }\n> -\n> armv7m = qdev_create(NULL, TYPE_ARMV7M);\n> qdev_prop_set_uint32(armv7m, \"num-irq\", num_irq);\n> - qdev_prop_set_string(armv7m, \"cpu-model\", cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", cpu_type);\n> object_property_set_link(OBJECT(armv7m), OBJECT(get_system_memory()),\n> \"memory\", &error_abort);\n> - /* This will exit with an error if the user passed us a bad cpu_model */\n> + /* This will exit with an error if the user passed us a bad cpu_type */\n> qdev_init_nofail(armv7m);\n>\n> armv7m_load_kernel(ARM_CPU(first_cpu), kernel_filename, mem_size);\n> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c\n> index 13c6393..5aa3d2d 100644\n> --- a/hw/arm/aspeed_soc.c\n> +++ b/hw/arm/aspeed_soc.c\n> @@ -54,7 +54,7 @@ static const char *aspeed_soc_ast2500_typenames[] = {\n> static const AspeedSoCInfo aspeed_socs[] = {\n> {\n> .name = \"ast2400-a0\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A0_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -65,7 +65,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2400-a1\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A1_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -76,7 +76,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2400\",\n> - .cpu_model = \"arm926\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm926\"),\n> .silicon_rev = AST2400_A0_SILICON_REV,\n> .sdram_base = AST2400_SDRAM_BASE,\n> .sram_size = 0x8000,\n> @@ -87,7 +87,7 @@ static const AspeedSoCInfo aspeed_socs[] = {\n> .wdts_num = 2,\n> }, {\n> .name = \"ast2500-a1\",\n> - .cpu_model = \"arm1176\",\n> + .cpu_type = ARM_CPU_TYPE_NAME(\"arm1176\"),\n> .silicon_rev = AST2500_A1_SILICON_REV,\n> .sdram_base = AST2500_SDRAM_BASE,\n> .sram_size = 0x9000,\n> @@ -128,13 +128,10 @@ static void aspeed_soc_init(Object *obj)\n> {\n> AspeedSoCState *s = ASPEED_SOC(obj);\n> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);\n> - char *cpu_typename;\n> int i;\n>\n> - cpu_typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, sc->info->cpu_model);\n> - object_initialize(&s->cpu, sizeof(s->cpu), cpu_typename);\n> + object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type);\n> object_property_add_child(obj, \"cpu\", OBJECT(&s->cpu), NULL);\n> - g_free(cpu_typename);\n>\n> object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC);\n> object_property_add_child(obj, \"vic\", OBJECT(&s->vic), NULL);\n> diff --git a/hw/arm/collie.c b/hw/arm/collie.c\n> index 8830192..f8c566e 100644\n> --- a/hw/arm/collie.c\n> +++ b/hw/arm/collie.c\n> @@ -18,7 +18,7 @@\n> #include \"hw/block/flash.h\"\n> #include \"sysemu/block-backend.h\"\n> #include \"exec/address-spaces.h\"\n> -#include \"qom/cpu.h\"\n> +#include \"cpu.h\"\n>\n> static struct arm_boot_info collie_binfo = {\n> .loader_start = SA_SDCS0,\n> @@ -27,7 +27,6 @@ static struct arm_boot_info collie_binfo = {\n>\n> static void collie_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -35,11 +34,7 @@ static void collie_init(MachineState *machine)\n> DriveInfo *dinfo;\n> MemoryRegion *sysmem = get_system_memory();\n>\n> - if (!cpu_model) {\n> - cpu_model = \"sa1110\";\n> - }\n> -\n> - s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model);\n> + s = sa1110_init(sysmem, collie_binfo.ram_size, machine->cpu_type);\n>\n> dinfo = drive_get(IF_PFLASH, 0, 0);\n> pflash_cfi01_register(SA_CS0, NULL, \"collie.fl1\", 0x02000000,\n> @@ -65,6 +60,7 @@ static void collie_machine_init(MachineClass *mc)\n> mc->desc = \"Sharp SL-5500 (Collie) PDA (SA-1110)\";\n> mc->init = collie_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"sa1110\");\n> }\n>\n> DEFINE_MACHINE(\"collie\", collie_machine_init)\n> diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c\n> index ee1438a..e8e1d81 100644\n> --- a/hw/arm/exynos4210.c\n> +++ b/hw/arm/exynos4210.c\n> @@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)\n> Exynos4210State *s = g_new(Exynos4210State, 1);\n> qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];\n> SysBusDevice *busdev;\n> - ObjectClass *cpu_oc;\n> DeviceState *dev;\n> int i, n;\n>\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, \"cortex-a9\");\n> - assert(cpu_oc);\n> -\n> for (n = 0; n < EXYNOS4210_NCPUS; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(ARM_CPU_TYPE_NAME(\"cortex-a9\"));\n>\n> /* By default A9 CPUs have EL3 enabled. This board does not currently\n> * support EL3 so the CPU EL3 property is disabled before realization.\n> diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c\n> index 092ce36..bba9e9f 100644\n> --- a/hw/arm/gumstix.c\n> +++ b/hw/arm/gumstix.c\n> @@ -44,6 +44,7 @@\n> #include \"sysemu/block-backend.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n>\n> static const int sector_len = 128 * 1024;\n>\n> @@ -86,7 +87,6 @@ static void connex_init(MachineState *machine)\n>\n> static void verdex_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> PXA2xxState *cpu;\n> DriveInfo *dinfo;\n> int be;\n> @@ -95,7 +95,7 @@ static void verdex_init(MachineState *machine)\n> uint32_t verdex_rom = 0x02000000;\n> uint32_t verdex_ram = 0x10000000;\n>\n> - cpu = pxa270_init(address_space_mem, verdex_ram, cpu_model ?: \"pxa270-c0\");\n> + cpu = pxa270_init(address_space_mem, verdex_ram, machine->cpu_type);\n>\n> dinfo = drive_get(IF_PFLASH, 0, 0);\n> if (!dinfo && !qtest_enabled()) {\n> @@ -144,6 +144,7 @@ static void verdex_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Gumstix Verdex (PXA270)\";\n> mc->init = verdex_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n>\n> static const TypeInfo verdex_type = {\n> diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c\n> index ba27789..354c6b2 100644\n> --- a/hw/arm/highbank.c\n> +++ b/hw/arm/highbank.c\n> @@ -222,7 +222,6 @@ enum cxmachines {\n> static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -239,19 +238,20 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)\n>\n> switch (machine_id) {\n> case CALXEDA_HIGHBANK:\n> - cpu_model = \"cortex-a9\";\n> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> break;\n> case CALXEDA_MIDWAY:\n> - cpu_model = \"cortex-a15\";\n> + machine->cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> break;\n> + default:\n> + assert(0);\n> }\n>\n> for (n = 0; n < smp_cpus; n++) {\n> - ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> Object *cpuobj;\n> ARMCPU *cpu;\n>\n> - cpuobj = object_new(object_class_get_name(oc));\n> + cpuobj = object_new(machine->cpu_type);\n> cpu = ARM_CPU(cpuobj);\n>\n> object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,\n> diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c\n> index d603af9..e8303b8 100644\n> --- a/hw/arm/integratorcp.c\n> +++ b/hw/arm/integratorcp.c\n> @@ -572,46 +572,19 @@ static struct arm_boot_info integrator_binfo = {\n> static void integratorcp_init(MachineState *machine)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> - char **cpustr;\n> - ObjectClass *cpu_oc;\n> - CPUClass *cc;\n> Object *cpuobj;\n> ARMCPU *cpu;\n> - const char *typename;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *ram_alias = g_new(MemoryRegion, 1);\n> qemu_irq pic[32];\n> DeviceState *dev, *sic, *icp;\n> int i;\n> - Error *err = NULL;\n>\n> - if (!cpu_model) {\n> - cpu_model = \"arm926\";\n> - }\n> -\n> - cpustr = g_strsplit(cpu_model, \",\", 2);\n> -\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> - typename = object_class_get_name(cpu_oc);\n> -\n> - cc = CPU_CLASS(cpu_oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_report_err(err);\n> - exit(1);\n> - }\n> -\n> - cpuobj = object_new(typename);\n> + cpuobj = object_new(machine->cpu_type);\n>\n> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -682,6 +655,7 @@ static void integratorcp_machine_init(MachineClass *mc)\n> mc->desc = \"ARM Integrator/CP (ARM926EJ-S)\";\n> mc->init = integratorcp_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n>\n> DEFINE_MACHINE(\"integratorcp\", integratorcp_machine_init)\n> diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c\n> index 637f52c..d07972a 100644\n> --- a/hw/arm/mainstone.c\n> +++ b/hw/arm/mainstone.c\n> @@ -24,6 +24,7 @@\n> #include \"hw/sysbus.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n>\n> /* Device addresses */\n> #define MST_FPGA_PHYS 0x08000000\n> @@ -121,13 +122,10 @@ static void mainstone_common_init(MemoryRegion *address_space_mem,\n> int i;\n> int be;\n> MemoryRegion *rom = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> -\n> - if (!cpu_model)\n> - cpu_model = \"pxa270-c5\";\n>\n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size,\n> + machine->cpu_type);\n> memory_region_init_ram(rom, NULL, \"mainstone.rom\", MAINSTONE_ROM,\n> &error_fatal);\n> memory_region_set_readonly(rom, true);\n> @@ -197,6 +195,7 @@ static void mainstone2_machine_init(MachineClass *mc)\n> mc->desc = \"Mainstone II (PXA27x)\";\n> mc->init = mainstone_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n>\n> DEFINE_MACHINE(\"mainstone\", mainstone2_machine_init)\n> diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c\n> index abb0ab6..aeaad80 100644\n> --- a/hw/arm/mps2.c\n> +++ b/hw/arm/mps2.c\n> @@ -46,7 +46,6 @@ typedef enum MPS2FPGAType {\n> typedef struct {\n> MachineClass parent;\n> MPS2FPGAType fpga_type;\n> - const char *cpu_model;\n> uint32_t scc_id;\n> } MPS2MachineClass;\n>\n> @@ -107,14 +106,12 @@ static void mps2_common_init(MachineState *machine)\n> MPS2MachineState *mms = MPS2_MACHINE(machine);\n> MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine);\n> MemoryRegion *system_memory = get_system_memory();\n> + MachineClass *mc = MACHINE_GET_CLASS(machine);\n> DeviceState *armv7m, *sccdev;\n>\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = mmc->cpu_model;\n> - }\n> -\n> - if (strcmp(machine->cpu_model, mmc->cpu_model) != 0) {\n> - error_report(\"This board can only be used with CPU %s\", mmc->cpu_model);\n> + if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {\n> + error_report(\"This board can only be used with CPU %s\",\n> + mc->default_cpu_type);\n> exit(1);\n> }\n>\n> @@ -188,7 +185,7 @@ static void mps2_common_init(MachineState *machine)\n> default:\n> g_assert_not_reached();\n> }\n> - qdev_prop_set_string(armv7m, \"cpu-model\", machine->cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", machine->cpu_type);\n> object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory),\n> \"memory\", &error_abort);\n> object_property_set_bool(OBJECT(&mms->armv7m), true, \"realized\",\n> @@ -339,7 +336,7 @@ static void mps2_an385_class_init(ObjectClass *oc, void *data)\n>\n> mc->desc = \"ARM MPS2 with AN385 FPGA image for Cortex-M3\";\n> mmc->fpga_type = FPGA_AN385;\n> - mmc->cpu_model = \"cortex-m3\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> mmc->scc_id = 0x41040000 | (385 << 4);\n> }\n>\n> @@ -350,7 +347,7 @@ static void mps2_an511_class_init(ObjectClass *oc, void *data)\n>\n> mc->desc = \"ARM MPS2 with AN511 DesignStart FPGA image for Cortex-M3\";\n> mmc->fpga_type = FPGA_AN511;\n> - mmc->cpu_model = \"cortex-m3\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> mmc->scc_id = 0x4104000 | (511 << 4);\n> }\n>\n> diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c\n> index 7a6c0a6..b648770 100644\n> --- a/hw/arm/musicpal.c\n> +++ b/hw/arm/musicpal.c\n> @@ -1570,7 +1570,6 @@ static struct arm_boot_info musicpal_binfo = {\n>\n> static void musicpal_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -1590,10 +1589,7 @@ static void musicpal_init(MachineState *machine)\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *sram = g_new(MemoryRegion, 1);\n>\n> - if (!cpu_model) {\n> - cpu_model = \"arm926\";\n> - }\n> - cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));\n> + cpu = ARM_CPU(cpu_create(machine->cpu_type));\n>\n> /* For now we use a fixed - the original - RAM size */\n> memory_region_allocate_system_memory(ram, NULL, \"musicpal.ram\",\n> @@ -1715,6 +1711,7 @@ static void musicpal_machine_init(MachineClass *mc)\n> mc->desc = \"Marvell 88w8618 / MusicPal (ARM926EJ-S)\";\n> mc->init = musicpal_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n>\n> DEFINE_MACHINE(\"musicpal\", musicpal_machine_init)\n> diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c\n> index 9d34d4c..f936017 100644\n> --- a/hw/arm/netduino2.c\n> +++ b/hw/arm/netduino2.c\n> @@ -34,7 +34,7 @@ static void netduino2_init(MachineState *machine)\n> DeviceState *dev;\n>\n> dev = qdev_create(NULL, TYPE_STM32F205_SOC);\n> - qdev_prop_set_string(dev, \"cpu-model\", \"cortex-m3\");\n> + qdev_prop_set_string(dev, \"cpu-type\", ARM_CPU_TYPE_NAME(\"cortex-m3\"));\n> object_property_set_bool(OBJECT(dev), true, \"realized\", &error_fatal);\n>\n> armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename,\n> diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c\n> index a32ac82..58005b6 100644\n> --- a/hw/arm/nseries.c\n> +++ b/hw/arm/nseries.c\n> @@ -1310,7 +1310,7 @@ static void n8x0_init(MachineState *machine,\n> struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s));\n> int sdram_size = binfo->ram_size;\n>\n> - s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_model);\n> + s->mpu = omap2420_mpu_init(sysmem, sdram_size, machine->cpu_type);\n>\n> /* Setup peripherals\n> *\n> @@ -1426,6 +1426,7 @@ static void n800_class_init(ObjectClass *oc, void *data)\n> mc->init = n800_init;\n> mc->default_boot_order = \"\";\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n> }\n>\n> static const TypeInfo n800_type = {\n> @@ -1442,6 +1443,7 @@ static void n810_class_init(ObjectClass *oc, void *data)\n> mc->init = n810_init;\n> mc->default_boot_order = \"\";\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm1136-r2\");\n> }\n>\n> static const TypeInfo n810_type = {\n> diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c\n> index 04e65ce..b3e7625 100644\n> --- a/hw/arm/omap1.c\n> +++ b/hw/arm/omap1.c\n> @@ -3850,7 +3850,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,\n>\n> struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n> unsigned long sdram_size,\n> - const char *core)\n> + const char *cpu_type)\n> {\n> int i;\n> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n> @@ -3858,12 +3858,9 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,\n> DriveInfo *dinfo;\n> SysBusDevice *busdev;\n>\n> - if (!core)\n> - core = \"ti925t\";\n> -\n> /* Core */\n> s->mpu_model = omap310;\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->sdram_size = sdram_size;\n> s->sram_size = OMAP15XX_SRAM_SIZE;\n>\n> diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c\n> index 5821477..3f6076e 100644\n> --- a/hw/arm/omap2.c\n> +++ b/hw/arm/omap2.c\n> @@ -2250,7 +2250,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {\n>\n> struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n> unsigned long sdram_size,\n> - const char *core)\n> + const char *cpu_type)\n> {\n> struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);\n> qemu_irq dma_irqs[4];\n> @@ -2261,7 +2261,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,\n>\n> /* Core */\n> s->mpu_model = omap2420;\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, core ?: \"arm1136-r2\"));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->sdram_size = sdram_size;\n> s->sram_size = OMAP242X_SRAM_SIZE;\n>\n> diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c\n> index 4535617..9a14270 100644\n> --- a/hw/arm/omap_sx1.c\n> +++ b/hw/arm/omap_sx1.c\n> @@ -36,6 +36,7 @@\n> #include \"sysemu/block-backend.h\"\n> #include \"sysemu/qtest.h\"\n> #include \"exec/address-spaces.h\"\n> +#include \"cpu.h\"\n>\n> /*****************************************************************************/\n> /* Siemens SX1 Cellphone V1 */\n> @@ -120,7 +121,7 @@ static void sx1_init(MachineState *machine, const int version)\n> }\n>\n> mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,\n> - machine->cpu_model);\n> + machine->cpu_type);\n>\n> /* External Flash (EMIFS) */\n> memory_region_init_ram(flash, NULL, \"omap_sx1.flash0-0\", flash_size,\n> @@ -224,6 +225,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Siemens SX1 (OMAP310) V2\";\n> mc->init = sx1_init_v2;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n>\n> static const TypeInfo sx1_machine_v2_type = {\n> @@ -239,6 +241,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Siemens SX1 (OMAP310) V1\";\n> mc->init = sx1_init_v1;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n>\n> static const TypeInfo sx1_machine_v1_type = {\n> diff --git a/hw/arm/palm.c b/hw/arm/palm.c\n> index bf070a2..b8753e2 100644\n> --- a/hw/arm/palm.c\n> +++ b/hw/arm/palm.c\n> @@ -29,6 +29,7 @@\n> #include \"hw/devices.h\"\n> #include \"hw/loader.h\"\n> #include \"exec/address-spaces.h\"\n> +#include \"cpu.h\"\n>\n> static uint32_t static_readb(void *opaque, hwaddr offset)\n> {\n> @@ -195,7 +196,6 @@ static struct arm_boot_info palmte_binfo = {\n>\n> static void palmte_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -211,7 +211,7 @@ static void palmte_init(MachineState *machine)\n> MemoryRegion *flash = g_new(MemoryRegion, 1);\n> MemoryRegion *cs = g_new(MemoryRegion, 4);\n>\n> - mpu = omap310_mpu_init(address_space_mem, sdram_size, cpu_model);\n> + mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);\n>\n> /* External Flash (EMIFS) */\n> memory_region_init_ram(flash, NULL, \"palmte.flash\", flash_size,\n> @@ -275,6 +275,7 @@ static void palmte_machine_init(MachineClass *mc)\n> mc->desc = \"Palm Tungsten|E aka. Cheetah PDA (OMAP310)\";\n> mc->init = palmte_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"ti925t\");\n> }\n>\n> DEFINE_MACHINE(\"cheetah\", palmte_machine_init)\n> diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c\n> index c16657d..cf07234 100644\n> --- a/hw/arm/pxa2xx.c\n> +++ b/hw/arm/pxa2xx.c\n> @@ -2052,21 +2052,19 @@ static void pxa2xx_reset(void *opaque, int line, int level)\n>\n> /* Initialise a PXA270 integrated chip (ARM based core). */\n> PXA2xxState *pxa270_init(MemoryRegion *address_space,\n> - unsigned int sdram_size, const char *revision)\n> + unsigned int sdram_size, const char *cpu_type)\n> {\n> PXA2xxState *s;\n> int i;\n> DriveInfo *dinfo;\n> s = g_new0(PXA2xxState, 1);\n>\n> - if (revision && strncmp(revision, \"pxa27\", 5)) {\n> + if (strncmp(cpu_type, \"pxa27\", 5)) {\n> fprintf(stderr, \"Machine requires a PXA27x processor.\\n\");\n> exit(1);\n> }\n> - if (!revision)\n> - revision = \"pxa270\";\n>\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, revision));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n>\n> /* SDRAM & Internal Memory Storage */\n> @@ -2192,7 +2190,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)\n>\n> s = g_new0(PXA2xxState, 1);\n>\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, \"pxa255\"));\n> + s->cpu = ARM_CPU(cpu_create(ARM_CPU_TYPE_NAME(\"pxa255\")));\n> s->reset = qemu_allocate_irq(pxa2xx_reset, s, 0);\n>\n> /* SDRAM & Internal Memory Storage */\n> diff --git a/hw/arm/realview.c b/hw/arm/realview.c\n> index f3a49b6..87cd1e5 100644\n> --- a/hw/arm/realview.c\n> +++ b/hw/arm/realview.c\n> @@ -57,7 +57,6 @@ static void realview_init(MachineState *machine,\n> {\n> ARMCPU *cpu = NULL;\n> CPUARMState *env;\n> - ObjectClass *cpu_oc;\n> MemoryRegion *sysmem = get_system_memory();\n> MemoryRegion *ram_lo;\n> MemoryRegion *ram_hi = g_new(MemoryRegion, 1);\n> @@ -98,14 +97,8 @@ static void realview_init(MachineState *machine,\n> break;\n> }\n>\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> for (n = 0; n < smp_cpus; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(machine->cpu_type);\n>\n> /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board\n> * does not currently support EL3 so the CPU EL3 property is disabled\n> @@ -361,33 +354,21 @@ static void realview_init(MachineState *machine,\n>\n> static void realview_eb_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm926\";\n> - }\n> realview_init(machine, BOARD_EB);\n> }\n>\n> static void realview_eb_mpcore_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm11mpcore\";\n> - }\n> realview_init(machine, BOARD_EB_MPCORE);\n> }\n>\n> static void realview_pb_a8_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"cortex-a8\";\n> - }\n> realview_init(machine, BOARD_PB_A8);\n> }\n>\n> static void realview_pbx_a9_init(MachineState *machine)\n> {\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"cortex-a9\";\n> - }\n> realview_init(machine, BOARD_PBX_A9);\n> }\n>\n> @@ -399,6 +380,7 @@ static void realview_eb_class_init(ObjectClass *oc, void *data)\n> mc->init = realview_eb_init;\n> mc->block_default_type = IF_SCSI;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n>\n> static const TypeInfo realview_eb_type = {\n> @@ -416,6 +398,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data)\n> mc->block_default_type = IF_SCSI;\n> mc->max_cpus = 4;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm11mpcore\");\n> }\n>\n> static const TypeInfo realview_eb_mpcore_type = {\n> @@ -431,6 +414,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"ARM RealView Platform Baseboard for Cortex-A8\";\n> mc->init = realview_pb_a8_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a8\");\n> }\n>\n> static const TypeInfo realview_pb_a8_type = {\n> @@ -447,6 +431,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc, void *data)\n> mc->init = realview_pbx_a9_init;\n> mc->max_cpus = 4;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> }\n>\n> static const TypeInfo realview_pbx_a9_type = {\n> diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c\n> index 6406421..feccdb0 100644\n> --- a/hw/arm/spitz.c\n> +++ b/hw/arm/spitz.c\n> @@ -30,6 +30,7 @@\n> #include \"hw/sysbus.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/sysemu.h\"\n> +#include \"cpu.h\"\n>\n> #undef REG_FMT\n> #define REG_FMT \"0x%02lx\"\n> @@ -909,13 +910,10 @@ static void spitz_common_init(MachineState *machine,\n> DeviceState *scp0, *scp1 = NULL;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *rom = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> -\n> - if (!cpu_model)\n> - cpu_model = (model == terrier) ? \"pxa270-c5\" : \"pxa270-c0\";\n>\n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,\n> + machine->cpu_type);\n>\n> sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);\n>\n> @@ -984,6 +982,7 @@ static void akitapda_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Sharp SL-C1000 (Akita) PDA (PXA270)\";\n> mc->init = akita_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n>\n> static const TypeInfo akitapda_type = {\n> @@ -1000,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *data)\n> mc->init = spitz_init;\n> mc->block_default_type = IF_IDE;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n>\n> static const TypeInfo spitzpda_type = {\n> @@ -1016,6 +1016,7 @@ static void borzoipda_class_init(ObjectClass *oc, void *data)\n> mc->init = borzoi_init;\n> mc->block_default_type = IF_IDE;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c0\");\n> }\n>\n> static const TypeInfo borzoipda_type = {\n> @@ -1032,6 +1033,7 @@ static void terrierpda_class_init(ObjectClass *oc, void *data)\n> mc->init = terrier_init;\n> mc->block_default_type = IF_IDE;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n>\n> static const TypeInfo terrierpda_type = {\n> diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c\n> index b3aad23..de7c0fc 100644\n> --- a/hw/arm/stellaris.c\n> +++ b/hw/arm/stellaris.c\n> @@ -22,6 +22,7 @@\n> #include \"sysemu/sysemu.h\"\n> #include \"hw/char/pl011.h\"\n> #include \"hw/misc/unimp.h\"\n> +#include \"cpu.h\"\n>\n> #define GPIO_A 0\n> #define GPIO_B 1\n> @@ -1225,8 +1226,7 @@ static stellaris_board_info stellaris_boards[] = {\n> }\n> };\n>\n> -static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> - stellaris_board_info *board)\n> +static void stellaris_init(MachineState *ms, stellaris_board_info *board)\n> {\n> static const int uart_irq[] = {5, 6, 33, 34};\n> static const int timer_irq[] = {19, 21, 23, 35};\n> @@ -1298,7 +1298,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> memory_region_add_subregion(system_memory, 0x20000000, sram);\n>\n> nvic = armv7m_init(system_memory, flash_size, NUM_IRQ_LINES,\n> - kernel_filename, cpu_model);\n> + ms->kernel_filename, ms->cpu_type);\n>\n> qdev_connect_gpio_out_named(nvic, \"SYSRESETREQ\", 0,\n> qemu_allocate_irq(&do_sys_reset, NULL, 0));\n> @@ -1435,16 +1435,12 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,\n> /* FIXME: Figure out how to generate these from stellaris_boards. */\n> static void lm3s811evb_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> - const char *kernel_filename = machine->kernel_filename;\n> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);\n> + stellaris_init(machine, &stellaris_boards[0]);\n> }\n>\n> static void lm3s6965evb_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> - const char *kernel_filename = machine->kernel_filename;\n> - stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);\n> + stellaris_init(machine, &stellaris_boards[1]);\n> }\n>\n> static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n> @@ -1454,6 +1450,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Stellaris LM3S811EVB\";\n> mc->init = lm3s811evb_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> }\n>\n> static const TypeInfo lm3s811evb_type = {\n> @@ -1469,6 +1466,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, void *data)\n> mc->desc = \"Stellaris LM3S6965EVB\";\n> mc->init = lm3s6965evb_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-m3\");\n> }\n>\n> static const TypeInfo lm3s6965evb_type = {\n> diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c\n> index f61e735..1cd6374 100644\n> --- a/hw/arm/stm32f205_soc.c\n> +++ b/hw/arm/stm32f205_soc.c\n> @@ -112,7 +112,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n>\n> armv7m = DEVICE(&s->armv7m);\n> qdev_prop_set_uint32(armv7m, \"num-irq\", 96);\n> - qdev_prop_set_string(armv7m, \"cpu-model\", s->cpu_model);\n> + qdev_prop_set_string(armv7m, \"cpu-type\", s->cpu_type);\n> object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),\n> \"memory\", &error_abort);\n> object_property_set_bool(OBJECT(&s->armv7m), true, \"realized\", &err);\n> @@ -200,7 +200,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)\n> }\n>\n> static Property stm32f205_soc_properties[] = {\n> - DEFINE_PROP_STRING(\"cpu-model\", STM32F205State, cpu_model),\n> + DEFINE_PROP_STRING(\"cpu-type\", STM32F205State, cpu_type),\n> DEFINE_PROP_END_OF_LIST(),\n> };\n>\n> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c\n> index c1145dd..3d1a231 100644\n> --- a/hw/arm/strongarm.c\n> +++ b/hw/arm/strongarm.c\n> @@ -1581,23 +1581,19 @@ static const TypeInfo strongarm_ssp_info = {\n>\n> /* Main CPU functions */\n> StrongARMState *sa1110_init(MemoryRegion *sysmem,\n> - unsigned int sdram_size, const char *rev)\n> + unsigned int sdram_size, const char *cpu_type)\n> {\n> StrongARMState *s;\n> int i;\n>\n> s = g_new0(StrongARMState, 1);\n>\n> - if (!rev) {\n> - rev = \"sa1110-b5\";\n> - }\n> -\n> - if (strncmp(rev, \"sa1110\", 6)) {\n> + if (strncmp(cpu_type, \"sa1110\", 6)) {\n> error_report(\"Machine requires a SA1110 processor.\");\n> exit(1);\n> }\n>\n> - s->cpu = ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, rev));\n> + s->cpu = ARM_CPU(cpu_create(cpu_type));\n>\n> memory_region_allocate_system_memory(&s->sdram, NULL, \"strongarm.sdram\",\n> sdram_size);\n> diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c\n> index 1134cf7..0447963 100644\n> --- a/hw/arm/tosa.c\n> +++ b/hw/arm/tosa.c\n> @@ -219,7 +219,6 @@ static struct arm_boot_info tosa_binfo = {\n>\n> static void tosa_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -229,9 +228,6 @@ static void tosa_init(MachineState *machine)\n> TC6393xbState *tmio;\n> DeviceState *scp0, *scp1;\n>\n> - if (!cpu_model)\n> - cpu_model = \"pxa255\";\n> -\n> mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size);\n>\n> memory_region_init_ram(rom, NULL, \"tosa.rom\", TOSA_ROM, &error_fatal);\n> diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c\n> index 76664e4..418792c 100644\n> --- a/hw/arm/versatilepb.c\n> +++ b/hw/arm/versatilepb.c\n> @@ -181,7 +181,6 @@ static struct arm_boot_info versatile_binfo;\n>\n> static void versatile_init(MachineState *machine, int board_id)\n> {\n> - ObjectClass *cpu_oc;\n> Object *cpuobj;\n> ARMCPU *cpu;\n> MemoryRegion *sysmem = get_system_memory();\n> @@ -207,17 +206,7 @@ static void versatile_init(MachineState *machine, int board_id)\n> exit(1);\n> }\n>\n> - if (!machine->cpu_model) {\n> - machine->cpu_model = \"arm926\";\n> - }\n> -\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> - cpuobj = object_new(object_class_get_name(cpu_oc));\n> + cpuobj = object_new(machine->cpu_type);\n>\n> /* By default ARM1176 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -404,6 +393,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data)\n> mc->init = vpb_init;\n> mc->block_default_type = IF_SCSI;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n>\n> static const TypeInfo versatilepb_type = {\n> @@ -420,6 +410,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data)\n> mc->init = vab_init;\n> mc->block_default_type = IF_SCSI;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"arm926\");\n> }\n>\n> static const TypeInfo versatileab_type = {\n> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c\n> index e3acab6..2e5f670 100644\n> --- a/hw/arm/vexpress.c\n> +++ b/hw/arm/vexpress.c\n> @@ -186,7 +186,7 @@ typedef struct {\n>\n> typedef void DBoardInitFn(const VexpressMachineState *machine,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic);\n>\n> struct VEDBoardInfo {\n> @@ -202,22 +202,16 @@ struct VEDBoardInfo {\n> DBoardInitFn *init;\n> };\n>\n> -static void init_cpus(const char *cpu_model, const char *privdev,\n> +static void init_cpus(const char *cpu_type, const char *privdev,\n> hwaddr periphbase, qemu_irq *pic, bool secure)\n> {\n> - ObjectClass *cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> DeviceState *dev;\n> SysBusDevice *busdev;\n> int n;\n>\n> - if (!cpu_oc) {\n> - fprintf(stderr, \"Unable to find CPU definition\\n\");\n> - exit(1);\n> - }\n> -\n> /* Create the actual CPUs */\n> for (n = 0; n < smp_cpus; n++) {\n> - Object *cpuobj = object_new(object_class_get_name(cpu_oc));\n> + Object *cpuobj = object_new(cpu_type);\n>\n> if (!secure) {\n> object_property_set_bool(cpuobj, false, \"has_el3\", NULL);\n> @@ -262,7 +256,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,\n>\n> static void a9_daughterboard_init(const VexpressMachineState *vms,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic)\n> {\n> MemoryRegion *sysmem = get_system_memory();\n> @@ -270,10 +264,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n> MemoryRegion *lowram = g_new(MemoryRegion, 1);\n> ram_addr_t low_ram_size;\n>\n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a9\";\n> - }\n> -\n> if (ram_size > 0x40000000) {\n> /* 1GB is the maximum the address space permits */\n> fprintf(stderr, \"vexpress-a9: cannot model more than 1GB RAM\\n\");\n> @@ -295,7 +285,7 @@ static void a9_daughterboard_init(const VexpressMachineState *vms,\n> memory_region_add_subregion(sysmem, 0x60000000, ram);\n>\n> /* 0x1e000000 A9MPCore (SCU) private memory region */\n> - init_cpus(cpu_model, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);\n> + init_cpus(cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, vms->secure);\n>\n> /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */\n>\n> @@ -351,17 +341,13 @@ static VEDBoardInfo a9_daughterboard = {\n>\n> static void a15_daughterboard_init(const VexpressMachineState *vms,\n> ram_addr_t ram_size,\n> - const char *cpu_model,\n> + const char *cpu_type,\n> qemu_irq *pic)\n> {\n> MemoryRegion *sysmem = get_system_memory();\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> MemoryRegion *sram = g_new(MemoryRegion, 1);\n>\n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a15\";\n> - }\n> -\n> {\n> /* We have to use a separate 64 bit variable here to avoid the gcc\n> * \"comparison is always false due to limited range of data type\"\n> @@ -380,7 +366,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms,\n> memory_region_add_subregion(sysmem, 0x80000000, ram);\n>\n> /* 0x2c000000 A15MPCore private memory region (GIC) */\n> - init_cpus(cpu_model, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);\n> + init_cpus(cpu_type, TYPE_A15MPCORE_PRIV, 0x2c000000, pic, vms->secure);\n>\n> /* A15 daughterboard peripherals: */\n>\n> @@ -560,7 +546,7 @@ static void vexpress_common_init(MachineState *machine)\n> const hwaddr *map = daughterboard->motherboard_map;\n> int i;\n>\n> - daughterboard->init(vms, machine->ram_size, machine->cpu_model, pic);\n> + daughterboard->init(vms, machine->ram_size, machine->cpu_type, pic);\n>\n> /*\n> * If a bios file was provided, attempt to map it into memory\n> @@ -761,6 +747,7 @@ static void vexpress_a9_class_init(ObjectClass *oc, void *data)\n> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);\n>\n> mc->desc = \"ARM Versatile Express for Cortex-A9\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n>\n> vmc->daughterboard = &a9_daughterboard;\n> }\n> @@ -771,6 +758,7 @@ static void vexpress_a15_class_init(ObjectClass *oc, void *data)\n> VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);\n>\n> mc->desc = \"ARM Versatile Express for Cortex-A15\";\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n>\n> vmc->daughterboard = &a15_daughterboard;\n> }\n> diff --git a/hw/arm/virt.c b/hw/arm/virt.c\n> index fe96557..fe26e99 100644\n> --- a/hw/arm/virt.c\n> +++ b/hw/arm/virt.c\n> @@ -163,13 +163,13 @@ static const int a15irqmap[] = {\n> };\n>\n> static const char *valid_cpus[] = {\n> - \"cortex-a15\",\n> - \"cortex-a53\",\n> - \"cortex-a57\",\n> - \"host\",\n> + ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n> + ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n> + ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n> + ARM_CPU_TYPE_NAME(\"host\"),\n> };\n>\n> -static bool cpuname_valid(const char *cpu)\n> +static bool cpu_type_valid(const char *cpu)\n> {\n> int i;\n>\n> @@ -1258,18 +1258,8 @@ static void machvirt_init(MachineState *machine)\n> MemoryRegion *secure_sysmem = NULL;\n> int n, virt_max_cpus;\n> MemoryRegion *ram = g_new(MemoryRegion, 1);\n> - const char *cpu_model = machine->cpu_model;\n> - char **cpustr;\n> - ObjectClass *oc;\n> - const char *typename;\n> - CPUClass *cc;\n> - Error *err = NULL;\n> bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);\n>\n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a15\";\n> - }\n> -\n> /* We can probe only here because during property set\n> * KVM is not available yet\n> */\n> @@ -1286,11 +1276,8 @@ static void machvirt_init(MachineState *machine)\n> }\n> }\n>\n> - /* Separate the actual CPU model name from any appended features */\n> - cpustr = g_strsplit(cpu_model, \",\", 2);\n> -\n> - if (!cpuname_valid(cpustr[0])) {\n> - error_report(\"mach-virt: CPU %s not supported\", cpustr[0]);\n> + if (!cpu_type_valid(machine->cpu_type)) {\n> + error_report(\"mach-virt: CPU type %s not supported\", machine->cpu_type);\n> exit(1);\n> }\n>\n> @@ -1360,22 +1347,6 @@ static void machvirt_init(MachineState *machine)\n>\n> create_fdt(vms);\n>\n> - oc = cpu_class_by_name(TYPE_ARM_CPU, cpustr[0]);\n> - if (!oc) {\n> - error_report(\"Unable to find CPU definition\");\n> - exit(1);\n> - }\n> - typename = object_class_get_name(oc);\n> -\n> - /* convert -smp CPU options specified by the user into global props */\n> - cc = CPU_CLASS(oc);\n> - cc->parse_features(typename, cpustr[1], &err);\n> - g_strfreev(cpustr);\n> - if (err) {\n> - error_report_err(err);\n> - exit(1);\n> - }\n> -\n> possible_cpus = mc->possible_cpu_arch_ids(machine);\n> for (n = 0; n < possible_cpus->len; n++) {\n> Object *cpuobj;\n> @@ -1385,7 +1356,7 @@ static void machvirt_init(MachineState *machine)\n> break;\n> }\n>\n> - cpuobj = object_new(typename);\n> + cpuobj = object_new(machine->cpu_type);\n> object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,\n> \"mp-affinity\", NULL);\n>\n> @@ -1630,6 +1601,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data)\n> mc->minimum_page_bits = 12;\n> mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;\n> mc->cpu_index_to_instance_props = virt_cpu_index_to_props;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a15\");\n> }\n>\n> static const TypeInfo virt_machine_info = {\n> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c\n> index 3759cf8..1836a4e 100644\n> --- a/hw/arm/xilinx_zynq.c\n> +++ b/hw/arm/xilinx_zynq.c\n> @@ -158,11 +158,9 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,\n> static void zynq_init(MachineState *machine)\n> {\n> ram_addr_t ram_size = machine->ram_size;\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> - ObjectClass *cpu_oc;\n> ARMCPU *cpu;\n> MemoryRegion *address_space_mem = get_system_memory();\n> MemoryRegion *ext_ram = g_new(MemoryRegion, 1);\n> @@ -174,12 +172,7 @@ static void zynq_init(MachineState *machine)\n> qemu_irq pic[64];\n> int n;\n>\n> - if (!cpu_model) {\n> - cpu_model = \"cortex-a9\";\n> - }\n> - cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);\n> -\n> - cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));\n> + cpu = ARM_CPU(object_new(machine->cpu_type));\n>\n> /* By default A9 CPUs have EL3 enabled. This board does not\n> * currently support EL3 so the CPU EL3 property is disabled before\n> @@ -327,6 +320,7 @@ static void zynq_machine_init(MachineClass *mc)\n> mc->max_cpus = 1;\n> mc->no_sdcard = 1;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"cortex-a9\");\n> }\n>\n> DEFINE_MACHINE(\"xilinx-zynq-a9\", zynq_machine_init)\n> diff --git a/hw/arm/z2.c b/hw/arm/z2.c\n> index 417bc1a..60561c7 100644\n> --- a/hw/arm/z2.c\n> +++ b/hw/arm/z2.c\n> @@ -26,6 +26,7 @@\n> #include \"audio/audio.h\"\n> #include \"exec/address-spaces.h\"\n> #include \"sysemu/qtest.h\"\n> +#include \"cpu.h\"\n>\n> #ifdef DEBUG_Z2\n> #define DPRINTF(fmt, ...) \\\n> @@ -296,7 +297,6 @@ static const TypeInfo aer915_info = {\n>\n> static void z2_init(MachineState *machine)\n> {\n> - const char *cpu_model = machine->cpu_model;\n> const char *kernel_filename = machine->kernel_filename;\n> const char *kernel_cmdline = machine->kernel_cmdline;\n> const char *initrd_filename = machine->initrd_filename;\n> @@ -309,12 +309,8 @@ static void z2_init(MachineState *machine)\n> I2CBus *bus;\n> DeviceState *wm;\n>\n> - if (!cpu_model) {\n> - cpu_model = \"pxa270-c5\";\n> - }\n> -\n> /* Setup CPU & memory */\n> - mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, cpu_model);\n> + mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type);\n>\n> #ifdef TARGET_WORDS_BIGENDIAN\n> be = 1;\n> @@ -371,6 +367,7 @@ static void z2_machine_init(MachineClass *mc)\n> mc->desc = \"Zipit Z2 (PXA27x)\";\n> mc->init = z2_init;\n> mc->ignore_memory_transaction_failures = true;\n> + mc->default_cpu_type = ARM_CPU_TYPE_NAME(\"pxa270-c5\");\n> }\n>\n> DEFINE_MACHINE(\"z2\", z2_machine_init)\n> diff --git a/target/arm/cpu.c b/target/arm/cpu.c\n> index a1acce3..ff7ff28 100644\n> --- a/target/arm/cpu.c\n> +++ b/target/arm/cpu.c\n> @@ -905,7 +905,7 @@ static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)\n> }\n>\n> cpuname = g_strsplit(cpu_model, \",\", 1);\n> - typename = g_strdup_printf(\"%s-\" TYPE_ARM_CPU, cpuname[0]);\n> + typename = g_strdup_printf(ARM_CPU_TYPE_NAME(\"%s\"), cpuname[0]);\n> oc = object_class_by_name(typename);\n> g_strfreev(cpuname);\n> g_free(typename);\n> --\n> 2.7.4\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::244","Subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"qemu-devel@nongnu.org Developers\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1768855,"web_url":"http://patchwork.ozlabs.org/comment/1768855/","msgid":"","list_archive_url":null,"date":"2017-09-14T22:09:37","subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Sep 14, 2017 at 12:50 AM, Igor Mammedov wrote:\n> On Thu, 14 Sep 2017 00:47:20 -0300\n> Philippe Mathieu-Daudé wrote:\n>\n>> Hi Igor,\n>>\n>> awesome clean refactor!\n> Thanks,\n>\n> there is more patches on this topic for other targets to post\n> but it's waiting on 1-3/5 to land in master so it would be\n> easier for maintainers to verify/test them without fishing out\n> dependencies from mail list.\n>\n> hopefully everything will land in 2.11 so we won't have to deal\n> with cpu_model anywhere except of one place vl.c.\n>\n>> just 1 comment inlined.\n>>\n>> On 09/13/2017 01:04 PM, Igor Mammedov wrote:\n>> > there are 2 use cases to deal with:\n>> > 1: fixed CPU models per board/soc\n>> > 2: boards with user configurable cpu_model and fallback to\n>> > default cpu_model if user hasn't specified one explicitly\n>> >\n>> > For the 1st\n>> > drop intermediate cpu_model parsing and use const cpu type\n>> > directly, which replaces:\n>> > typename = object_class_get_name(\n>> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n>> > object_new(typename)\n>> > with\n>> > object_new(FOO_CPU_TYPE_NAME)\n>> > or\n>> > cpu_generic_init(BASE_CPU_TYPE, \"my cpu model\")\n>> > with\n>> > cpu_create(FOO_CPU_TYPE_NAME)\n>> >\n>> > as result 1st use case doesn't have to invoke not necessary\n>> > translation and not needed code is removed.\n>> >\n>> > For the 2nd\n>> > 1: set default cpu type with MachineClass::default_cpu_type and\n>> > 2: use generic cpu_model parsing that done before machine_init()\n>> > is run and:\n>> > 2.1: drop custom cpu_model parsing where pattern is:\n>> > typename = object_class_get_name(\n>> > cpu_class_by_name(TYPE_ARM_CPU, cpu_model))\n>> > [parse_features(typename, cpu_model, &err) ]\n>> >\n>> > 2.2: or replace cpu_generic_init() which does what\n>> > 2.1 does + create_cpu(typename) with just\n>> > create_cpu(machine->cpu_type)\n>> > as result cpu_name -> cpu_type translation is done using\n>> > generic machine code one including parsing optional features\n>> > if supported/present (removes a bunch of duplicated cpu_model\n>> > parsing code) and default cpu type is defined in an uniform way\n>> > within machine_class_init callbacks instead of adhoc places\n>> > in boadr's machine_init code.\n>> >\n>> > Signed-off-by: Igor Mammedov \n>> > Reviewed-by: Eduardo Habkost \n>> > ---\n>> > v2:\n>> > - fix merge conflicts with ignore_memory_transaction_failures\n>> > - fix couple merge conflicts where SoC type string where replaced by type macro\n>> > - keep plain prefix string in: strncmp(cpu_type, \"pxa27\", 5)\n>> > - s/\"%s\" ARM_CPU_TYPE_SUFFIX/ARM_CPU_TYPE_NAME(\"%s\")/\n>> > ---\n> [...]\n>\n>> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c\n>> > index fe96557..fe26e99 100644\n>> > --- a/hw/arm/virt.c\n>> > +++ b/hw/arm/virt.c\n>> > @@ -163,13 +163,13 @@ static const int a15irqmap[] = {\n>> > };\n>> >\n>> > static const char *valid_cpus[] = {\n>> > - \"cortex-a15\",\n>> > - \"cortex-a53\",\n>> > - \"cortex-a57\",\n>> > - \"host\",\n>> > + ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n>> > + ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n>> > + ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n>> > + ARM_CPU_TYPE_NAME(\"host\"),\n>> > };\n>> >\n>> > -static bool cpuname_valid(const char *cpu)\n>> > +static bool cpu_type_valid(const char *cpu)\n>> > {\n>> > int i;\n>>\n>> I'd just change this by:\n>>\n>> static bool cpuname_valid(const char *cpu)\n>> {\n>> static const char *valid_cpus[] = {\n>> ARM_CPU_TYPE_NAME(\"cortex-a15\"),\n>> ARM_CPU_TYPE_NAME(\"cortex-a53\"),\n>> ARM_CPU_TYPE_NAME(\"cortex-a57\"),\n>> };\n>> int i;\n>>\n>> for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {\n>> if (strcmp(cpu, valid_cpus[i]) == 0) {\n>> return true;\n>> }\n>> }\n>\n>> return kvm_enabled() && !strcmp(cpu, ARM_CPU_TYPE_NAME(\"host\");\n> here is one more case to consider for valid_cpus refactoring,\n> CCing Alistair.\n\nThanks, I have a few comments I need to look at for this. I'm going to\nhold off until this series lands though.\n\nThanks,\nAlistair\n\n>\n>> }\n>>\n>> Anyway this can be a later patch.\n> this check might be removed or superseded by generic valid_cpus work\n> that Alistair is working on, anyways it should be part of that work\n> as change is not directly related to this series.\n>\n>\n> [...]","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"V7gG3rsN\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtXm24cMqz9s3T\n\tfor ;\n\tFri, 15 Sep 2017 08:10:39 +1000 (AEST)","from localhost ([::1]:50207 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dscLE-0003sI-Vx\n\tfor incoming@patchwork.ozlabs.org; Thu, 14 Sep 2017 18:10:37 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:46124)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dscKr-0003oX-HC\n\tfor qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:10:14 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dscKq-0003jM-8b\n\tfor qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:10:13 -0400","from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:35706)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dscKn-0003fD-E2; Thu, 14 Sep 2017 18:10:09 -0400","by mail-wr0-x241.google.com with SMTP id n64so333204wrb.2;\n\tThu, 14 Sep 2017 15:10:09 -0700 (PDT)","by 10.28.191.130 with HTTP; Thu, 14 Sep 2017 15:09:37 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=I/4hKiIBHvIEdYybD6jEAJYcaX6mhyxBLkLPImoclzA=;\n\tb=V7gG3rsNSOqIY2xFgGHN5GuL2Hhjwg2Fenvf+IQYKoWQ5sdKFjJgH4t0L2kOfwfDii\n\t8WoSQZxOQn8rhmn6X5z9+EgyQUE54oM0W0bAfYdaXnuTzL0gUzNFFyuP6Ki5DoZjibQK\n\t3wIxUlmlQRdXCFvf65C9iZHeHmQaEHZWT2ReMWroHZuz6CD7cAWFm2n434Ecn4eGobIT\n\tB/5LJTi9aRQ10YSKUQMgR6ijfO0wju9XbTD7XKz4iJRlqCbJU0/ot8g2G399L/2AUoKh\n\tWM5PTF8wWFcdcEiWYeOD18NOY7P7FUUE44Trl5d5xl+fxUwWzwIIRUCvx0RUiyBgr8UL\n\tDyYA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=I/4hKiIBHvIEdYybD6jEAJYcaX6mhyxBLkLPImoclzA=;\n\tb=VQG6z75xfJNf1S6zhLjcDI/1m4ZV0xCEmS4///Cdm9aK6rfmuiAYpBMk0xgbj5KvWB\n\t//psqqjfWrKwNltmwcDaws+Vf1NjipFb/T66IoMgRPI8fxrMKjJl6Swe0oCoLqO1H0As\n\tyJz6ZOSJbxO+K2iuxv6WX28ab7jTj7fQROU7lrpNsKJctrev7RVt57b9+QVNR14E+Xlh\n\tA/KcBLaKsRCh5UC2GPipydw3Ri2iZ5Wf5IljQTLprRncxToWCGPgahgZx0v+RwMIie0G\n\tj2/zT2vcPMVwFKmjsiwNZJwTIsJvJt5oHLUY/T4m2lD0zuogY7e++i5g0S56+2faOQNO\n\tuE5Q==","X-Gm-Message-State":"AHPjjUhOXTuzZNGENjtaW4pQ6W4JYAaLxRaZBvf+hqapOIejnEyZ1ZRZ\n\tO+5FRdgkkUpSypObuHprCRMV+CYimRdUUGnEksU=","X-Google-Smtp-Source":"ADKCNb659NuhMQhpJ5fl5jkZmo7REbfrqjEcSnfsJOgyqUZyD5bNj/4amB+eoK3Ot0TvRET5OkoNzcIE14sbfxsIfe0=","X-Received":"by 10.223.187.74 with SMTP id x10mr18649074wrg.66.1505427008359; \n\tThu, 14 Sep 2017 15:10:08 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170914095011.2fba8aab@nial.brq.redhat.com>","References":"<1505318697-77161-1-git-send-email-imammedo@redhat.com>\n\t<1505318697-77161-6-git-send-email-imammedo@redhat.com>\n\t\n\t<20170914095011.2fba8aab@nial.brq.redhat.com>","From":"Alistair Francis ","Date":"Thu, 14 Sep 2017 15:09:37 -0700","Message-ID":"","To":"Igor Mammedov ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::241","Subject":"Re: [Qemu-devel] [PATCH v2 5/5] arm: drop intermediate cpu_model ->\n\tcpu type parsing and use cpu type directly","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"qemu-arm , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t, \"qemu-devel@nongnu.org Developers\"\n\t","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]