[{"id":1769763,"web_url":"http://patchwork.ozlabs.org/comment/1769763/","msgid":"","list_archive_url":null,"date":"2017-09-17T17:53:12","subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"On 13 September 2017 at 10:00, wrote:\n> From: Patrice Chotard \n>\n> This driver implements basic clock setup, only clock gating\n> is implemented.\n>\n> This driver doesn't implement .of_match as it's binded\n> by MFD RCC driver.\n>\n> Files include/dt-bindings/clock/stm32h7-clks.h and\n> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> will be available soon in a kernel tag, as all the\n> bindings have been acked by Rob Herring [1].\n>\n> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n>\n> Signed-off-by: Patrice Chotard \n> ---\n> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt | 152 ++++\n> drivers/clk/Makefile | 1 +\n> drivers/clk/clk_stm32h7.c | 802 ++++++++++++++++++++++\n> include/dt-bindings/clock/stm32h7-clks.h | 167 +++++\n> 4 files changed, 1122 insertions(+)\n> create mode 100644 doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> create mode 100644 drivers/clk/clk_stm32h7.c\n> create mode 100644 include/dt-bindings/clock/stm32h7-clks.h\n\nReviewed-by: Simon Glass ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=google.com header.i=@google.com\n\theader.b=\"KQG6lokk\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=chromium.org 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<1505318412-27121-4-git-send-email-patrice.chotard@st.com>","References":"<1505318412-27121-1-git-send-email-patrice.chotard@st.com>\n\t<1505318412-27121-4-git-send-email-patrice.chotard@st.com>","From":"Simon Glass ","Date":"Sun, 17 Sep 2017 11:53:12 -0600","X-Google-Sender-Auth":"N7_IZ8h0wT11L-cXRsRtn9HYhNU","Message-ID":"","To":"Patrice Chotard ","Cc":"U-Boot Mailing List ,\n\tAlbert ARIBAUD ","Subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1771503,"web_url":"http://patchwork.ozlabs.org/comment/1771503/","msgid":"","list_archive_url":null,"date":"2017-09-20T01:39:12","subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","submitter":{"id":64678,"url":"http://patchwork.ozlabs.org/api/people/64678/","name":"Vikas MANOCHA","email":"vikas.manocha@st.com"},"content":"Hi Patrice,\n\nOn 09/13/2017 09:00 AM, patrice.chotard@st.com wrote:\n> From: Patrice Chotard \n> \n> This driver implements basic clock setup, only clock gating\n> is implemented.\n> \n> This driver doesn't implement .of_match as it's binded\n> by MFD RCC driver.\n> \n> Files include/dt-bindings/clock/stm32h7-clks.h and\n> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> will be available soon in a kernel tag, as all the\n> bindings have been acked by Rob Herring [1].\n> \n> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n> \n> Signed-off-by: Patrice Chotard \n> ---\n> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt | 152 ++++\n> drivers/clk/Makefile | 1 +\n> drivers/clk/clk_stm32h7.c | 802 ++++++++++++++++++++++\n> include/dt-bindings/clock/stm32h7-clks.h | 167 +++++\n> 4 files changed, 1122 insertions(+)\n> create mode 100644 doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> create mode 100644 drivers/clk/clk_stm32h7.c\n> create mode 100644 include/dt-bindings/clock/stm32h7-clks.h\n> \n> diff --git a/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> new file mode 100644\n> index 0000000..9d4b587\n> --- /dev/null\n> +++ b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> @@ -0,0 +1,152 @@\n> +STMicroelectronics STM32H7 Reset and Clock Controller\n> +=====================================================\n> +\n> +The RCC IP is both a reset and a clock controller.\n> +\n> +Please refer to clock-bindings.txt for common clock controller binding usage.\n> +Please also refer to reset.txt for common reset controller binding usage.\n> +\n> +Required properties:\n> +- compatible: Should be:\n> + \"st,stm32h743-rcc\"\n> +\n> +- reg: should be register base and length as documented in the\n> + datasheet\n> +\n> +- #reset-cells: 1, see below\n> +\n> +- #clock-cells : from common clock binding; shall be set to 1\n> +\n> +- clocks: External oscillator clock phandle\n> + - high speed external clock signal (HSE)\n> + - low speed external clock signal (LSE)\n> + - external I2S clock (I2S_CKIN)\n> +\n> +- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain\n> + write protection (RTC clock).\n\nst,syscfg is confusing if we are using it for PWR or SYSCFG peripheral of the device.\nAlso why company name to reference the phandle, it can just be syscfg or better something like pwr_xxx as we it pointing to pwrcfg phandle.\n\n> +\n> +- pll x node: Allow to register a pll with specific parameters.\n> + Please see PLL section below.\n> +\n> +Example:\n> +\n> +\trcc: rcc@58024400 {\n> +\t\t#reset-cells = <1>;\n> +\t\t#clock-cells = <2>\n> +\t\tcompatible = \"st,stm32h743-rcc\", \"st,stm32-rcc\";\n> +\t\treg = <0x58024400 0x400>;\n> +\t\tclocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;\n> +\n> +\t\tst,syscfg = <&pwrcfg>;\n\nsee above.\n\n> +\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tvco1@58024430 {\n> +\t\t\t#clock-cells = <0>;\n> +\t\t\tcompatible = \"stm32,pll\";\n> +\t\t\treg = <0>;\n> +\t\t};\n> +\n> +\t\tvco2@58024438 {\n> +\t\t\t#clock-cells = <0>;\n> +\t\t\tcompatible = \"stm32,pll\";\n> +\t\t\treg = <1>;\n> +\t\t\tst,clock-div = <2>;\n> +\t\t\tst,clock-mult = <40>;\n> +\t\t\tst,frac-status = <0>;\n> +\t\t\tst,frac = <0>;\n> +\t\t\tst,vcosel = <1>;\n> +\t\t\tst,pllrge = <2>;\n> +\t\t};\n> +\t};\n> +\n> +\n> +STM32H7 PLL\n> +-----------\n> +\n> +The VCO of STM32 PLL could be reprensented like this:\n> +\n> + Vref --------- --------\n> + ---->| / DIVM |---->| x DIVN | ------> VCO\n> + --------- --------\n> +\t\t ^\n> +\t\t\t |\n> +\t -------\n> +\t\t | FRACN |\n> +\t\t -------\n> +\n> +When the PLL is configured in integer mode:\n> +- VCO = ( Vref / DIVM ) * DIVN\n> +\n> +When the PLL is configured in fractional mode:\n> +- VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)\n> +\n> +\n> +Required properties for pll node:\n> +- compatible: Should be:\n> + \"stm32,pll\"\n> +\n> +- #clock-cells: from common clock binding; shall be set to 0\n> +- reg: Should be the pll number.\n> +\n> +Optional properties:\n> +- st,clock-div: DIVM division factor : <1..63>\n> +- st,clock-mult: DIVN multiplication factor : <4..512>\n> +\n> +- st,frac-status:\n> + - 0 Pll is configured in integer mode\n> + - 1 Pll is configure in fractional mode\n> +\n> +- st,frac: Fractional part of the multiplication factor : <0..8191>\n> +\n> +- st,vcosel: VCO selection\n> + - 0: Wide VCO range:192 to 836 MHz\n> + - 1: Medium VCO range:150 to 420 MHz\n> +\n> +- st,pllrge: PLL input frequency range\n> + - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz\n> + - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz\n> + - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz\n> + - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz\n> +\n> +\n> +The peripheral clock consumer should specify the desired clock by\n> +having the clock ID in its \"clocks\" phandle cell.\n> +\n> +All available clocks are defined as preprocessor macros in\n> +dt-bindings/clock/stm32h7-clks.h header and can be used in device\n> +tree sources.\n> +\n> +Example:\n> +\n> +\t\ttimer5: timer@40000c00 {\n> +\t\t\tcompatible = \"st,stm32-timer\";\n> +\t\t\treg = <0x40000c00 0x400>;\n> +\t\t\tinterrupts = <50>;\n> +\t\t\tclocks = <&rcc TIM5_CK>;\n> +\n> +\t\t};\n> +\n> +Specifying softreset control of devices\n> +=======================================\n> +\n> +Device nodes should specify the reset channel required in their \"resets\"\n> +property, containing a phandle to the reset device node and an index specifying\n> +which channel to use.\n> +The index is the bit number within the RCC registers bank, starting from RCC\n> +base address.\n> +It is calculated as: index = register_offset / 4 * 32 + bit_offset.\n> +Where bit_offset is the bit offset within the register.\n> +\n> +For example, for CRC reset:\n> + crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107\n> +\n> +All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h\n> +header and can be used in device tree sources.\n> +\n> +example:\n> +\n> +\ttimer2 {\n> +\t\tresets\t= <&rcc STM32H7_APB1L_RESET(TIM2)>;\n> +\t};\n> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n> index b773593..83fe88c 100644\n> --- a/drivers/clk/Makefile\n> +++ b/drivers/clk/Makefile\n> @@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o\n> obj-$(CONFIG_CLK_BOSTON) += clk_boston.o\n> obj-$(CONFIG_ARCH_ASPEED) += aspeed/\n> obj-$(CONFIG_STM32F7) += clk_stm32f7.o\n> +obj-$(CONFIG_STM32H7) += clk_stm32h7.o\n> diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c\n> new file mode 100644\n> index 0000000..fd0e3ab\n> --- /dev/null\n> +++ b/drivers/clk/clk_stm32h7.c\n> @@ -0,0 +1,802 @@\n> +/*\n> + * Copyright (C) STMicroelectronics SA 2017\n> + * Author(s): Patrice CHOTARD, for STMicroelectronics.\n> + *\n> + * SPDX-License-Identifier:\tGPL-2.0+\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +\n> +DECLARE_GLOBAL_DATA_PTR;\n> +\n> +/* RCC CR specific definitions */\n> +#define RCC_CR_HSION\t\t\tBIT(0)\n> +#define RCC_CR_HSIRDY\t\t\tBIT(2)\n> +\n> +#define RCC_CR_HSEON\t\t\tBIT(16)\n> +#define RCC_CR_HSERDY\t\t\tBIT(17)\n> +#define RCC_CR_HSEBYP\t\t\tBIT(18)\n> +#define RCC_CR_PLL1ON\t\t\tBIT(24)\n> +#define RCC_CR_PLL1RDY\t\t\tBIT(25)\n> +\n> +#define RCC_CR_HSIDIV_MASK\t\tGENMASK(4, 3)\n> +#define RCC_CR_HSIDIV_SHIFT\t\t3\n> +\n> +#define RCC_CFGR_SW_MASK\t\tGENMASK(2, 0)\n> +#define RCC_CFGR_SW_HSI\t\t\t0\n> +#define RCC_CFGR_SW_CSI\t\t\t1\n> +#define RCC_CFGR_SW_HSE\t\t\t2\n> +#define RCC_CFGR_SW_PLL1\t\t3\n> +\n> +#define RCC_PLLCKSELR_PLLSRC_HSI\t0\n> +#define RCC_PLLCKSELR_PLLSRC_CSI\t1\n> +#define RCC_PLLCKSELR_PLLSRC_HSE\t2\n> +#define RCC_PLLCKSELR_PLLSRC_NO_CLK\t3\n> +\n> +#define RCC_PLLCKSELR_PLLSRC_MASK\tGENMASK(1, 0)\n> +\n> +#define RCC_PLLCKSELR_DIVM1_SHIFT\t4\n> +#define RCC_PLLCKSELR_DIVM1_MASK\tGENMASK(9, 4)\n> +\n> +#define RCC_PLL1DIVR_DIVN1_MASK\t\tGENMASK(8, 0)\n> +\n> +#define RCC_PLL1DIVR_DIVP1_SHIFT\t9\n> +#define RCC_PLL1DIVR_DIVP1_MASK\t\tGENMASK(15, 9)\n> +\n> +#define RCC_PLL1DIVR_DIVQ1_SHIFT\t16\n> +#define RCC_PLL1DIVR_DIVQ1_MASK\t\tGENMASK(22, 16)\n> +\n> +#define RCC_PLL1DIVR_DIVR1_SHIFT\t24\n> +#define RCC_PLL1DIVR_DIVR1_MASK\t\tGENMASK(30, 24)\n> +\n> +#define RCC_PLL1FRACR_FRACN1_SHIFT\t3\n> +#define RCC_PLL1FRACR_FRACN1_MASK\tGENMASK(15, 3)\n> +\n> +#define RCC_PLLCFGR_PLL1RGE_SHIFT\t2\n> +#define\t\tPLL1RGE_1_2_MHZ\t\t0\n> +#define\t\tPLL1RGE_2_4_MHZ\t\t1\n> +#define\t\tPLL1RGE_4_8_MHZ\t\t2\n> +#define\t\tPLL1RGE_8_16_MHZ\t3\n> +#define RCC_PLLCFGR_DIVP1EN\t\tBIT(16)\n> +#define RCC_PLLCFGR_DIVQ1EN\t\tBIT(17)\n> +#define RCC_PLLCFGR_DIVR1EN\t\tBIT(18)\n> +\n> +#define RCC_D1CFGR_HPRE_MASK\t\tGENMASK(3, 0)\n> +#define RCC_D1CFGR_HPRE_DIVIDED\t\tBIT(3)\n> +#define RCC_D1CFGR_HPRE_DIVIDER\t\tGENMASK(2, 0)\n> +\n> +#define RCC_D1CFGR_HPRE_DIV2\t\t8\n> +\n> +#define RCC_D1CFGR_D1PPRE_SHIFT\t\t4\n> +#define RCC_D1CFGR_D1PPRE_DIVIDED\tBIT(6)\n> +#define RCC_D1CFGR_D1PPRE_DIVIDER\tGENMASK(5, 4)\n> +\n> +#define RCC_D1CFGR_D1CPRE_SHIFT\t\t8\n> +#define RCC_D1CFGR_D1CPRE_DIVIDER\tGENMASK(10, 8)\n> +#define RCC_D1CFGR_D1CPRE_DIVIDED\tBIT(11)\n> +\n> +#define RCC_D2CFGR_D2PPRE1_SHIFT\t4\n> +#define RCC_D2CFGR_D2PPRE1_DIVIDED\tBIT(6)\n> +#define RCC_D2CFGR_D2PPRE1_DIVIDER\tGENMASK(5, 4)\n> +\n> +#define RCC_D2CFGR_D2PPRE2_SHIFT\t8\n> +#define RCC_D2CFGR_D2PPRE2_DIVIDED\tBIT(10)\n> +#define RCC_D2CFGR_D2PPRE2_DIVIDER\tGENMASK(9, 8)\n> +\n> +#define RCC_D3CFGR_D3PPRE_SHIFT\t\t4\n> +#define RCC_D3CFGR_D3PPRE_DIVIDED\tBIT(6)\n> +#define RCC_D3CFGR_D3PPRE_DIVIDER\tGENMASK(5, 4)\n> +\n> +#define RCC_D1CCIPR_FMCSRC_MASK\t\tGENMASK(1, 0)\n> +#define\t\tFMCSRC_HCLKD1\t\t0\n> +#define\t\tFMCSRC_PLL1_Q_CK\t1\n> +#define\t\tFMCSRC_PLL2_R_CK\t2\n> +#define\t\tFMCSRC_PER_CK\t\t3\n> +\n> +#define RCC_D1CCIPR_QSPISRC_MASK\tGENMASK(5, 4)\n> +#define RCC_D1CCIPR_QSPISRC_SHIFT\t4\n> +#define\t\tQSPISRC_HCLKD1\t\t0\n> +#define\t\tQSPISRC_PLL1_Q_CK\t1\n> +#define\t\tQSPISRC_PLL2_R_CK\t2\n> +#define\t\tQSPISRC_PER_CK\t\t3\n> +\n> +#define PWR_CR3\t\t\t\t0x0c\n> +#define PWR_CR3_SDEN\t\t\tBIT(2)\n\nCan we use SCUEN suffix to match the Ref Manual.\n\n> +#define PWR_D3CR\t\t\t0x18\n> +#define PWR_D3CR_VOS_MASK\t\tGENMASK(15, 14)\n> +#define PWR_D3CR_VOS_SHIFT\t\t14\n> +#define\t\tVOS_SCALE_3\t\t1\n> +#define\t\tVOS_SCALE_2\t\t2\n> +#define\t\tVOS_SCALE_1\t\t3\n> +#define PWR_D3CR_VOSREADY\t\tBIT(13)\n> +\n> +struct stm32_rcc_regs {\n> +\tu32 cr;\t\t/* 0x00 Source Control Register */\n> +\tu32 icscr;\t/* 0x04 Internal Clock Source Calibration Register */\n> +\tu32 crrcr;\t/* 0x08 Clock Recovery RC Register */\n> +\tu32 reserved1;\t/* 0x0c reserved */\n> +\tu32 cfgr;\t/* 0x10 Clock Configuration Register */\n> +\tu32 reserved2;\t/* 0x14 reserved */\n> +\tu32 d1cfgr;\t/* 0x18 Domain 1 Clock Configuration Register */\n> +\tu32 d2cfgr;\t/* 0x1c Domain 2 Clock Configuration Register */\n> +\tu32 d3cfgr;\t/* 0x20 Domain 3 Clock Configuration Register */\n> +\tu32 reserved3;\t/* 0x24 reserved */\n> +\tu32 pllckselr;\t/* 0x28 PLLs Clock Source Selection Register */\n> +\tu32 pllcfgr;\t/* 0x2c PLLs Configuration Register */\n> +\tu32 pll1divr;\t/* 0x30 PLL1 Dividers Configuration Register */\n> +\tu32 pll1fracr;\t/* 0x34 PLL1 Fractional Divider Register */\n> +\tu32 pll2divr;\t/* 0x38 PLL2 Dividers Configuration Register */\n> +\tu32 pll2fracr;\t/* 0x3c PLL2 Fractional Divider Register */\n> +\tu32 pll3divr;\t/* 0x40 PLL3 Dividers Configuration Register */\n> +\tu32 pll3fracr;\t/* 0x44 PLL3 Fractional Divider Register */\n> +\tu32 reserved4;\t/* 0x48 reserved */\n> +\tu32 d1ccipr;\t/* 0x4c Domain 1 Kernel Clock Configuration Register */\n> +\tu32 d2ccip1r;\t/* 0x50 Domain 2 Kernel Clock Configuration Register */\n> +\tu32 d2ccip2r;\t/* 0x54 Domain 2 Kernel Clock Configuration Register */\n> +\tu32 d3ccipr;\t/* 0x58 Domain 3 Kernel Clock Configuration Register */\n> +\tu32 reserved5;\t/* 0x5c reserved */\n> +\tu32 cier;\t/* 0x60 Clock Source Interrupt Enable Register */\n> +\tu32 cifr;\t/* 0x64 Clock Source Interrupt Flag Register */\n> +\tu32 cicr;\t/* 0x68 Clock Source Interrupt Clear Register */\n> +\tu32 reserved6;\t/* 0x6c reserved */\n> +\tu32 bdcr;\t/* 0x70 Backup Domain Control Register */\n> +\tu32 csr;\t/* 0x74 Clock Control and Status Register */\n> +\tu32 reserved7;\t/* 0x78 reserved */\n> +\n> +\tu32 ahb3rstr;\t/* 0x7c AHB3 Peripheral Reset Register */\n> +\tu32 ahb1rstr;\t/* 0x80 AHB1 Peripheral Reset Register */\n> +\tu32 ahb2rstr;\t/* 0x84 AHB2 Peripheral Reset Register */\n> +\tu32 ahb4rstr;\t/* 0x88 AHB4 Peripheral Reset Register */\n> +\n> +\tu32 apb3rstr;\t/* 0x8c APB3 Peripheral Reset Register */\n> +\tu32 apb1lrstr;\t/* 0x90 APB1 low Peripheral Reset Register */\n> +\tu32 apb1hrstr;\t/* 0x94 APB1 high Peripheral Reset Register */\n> +\tu32 apb2rstr;\t/* 0x98 APB2 Clock Register */\n> +\tu32 apb4rstr;\t/* 0x9c APB4 Clock Register */\n> +\n> +\tu32 gcr;\t/* 0xa0 Global Control Register */\n> +\tu32 reserved8;\t/* 0xa4 reserved */\n> +\tu32 d3amr;\t/* 0xa8 D3 Autonomous mode Register */\n> +\tu32 reserved9[9];/* 0xac to 0xcc reserved */\n> +\tu32 rsr;\t/* 0xd0 Reset Status Register */\n> +\tu32 ahb3enr;\t/* 0xd4 AHB3 Clock Register */\n> +\tu32 ahb1enr;\t/* 0xd8 AHB1 Clock Register */\n> +\tu32 ahb2enr;\t/* 0xdc AHB2 Clock Register */\n> +\tu32 ahb4enr;\t/* 0xe0 AHB4 Clock Register */\n> +\n> +\tu32 apb3enr;\t/* 0xe4 APB3 Clock Register */\n> +\tu32 apb1lenr;\t/* 0xe8 APB1 low Clock Register */\n> +\tu32 apb1henr;\t/* 0xec APB1 high Clock Register */\n> +\tu32 apb2enr;\t/* 0xf0 APB2 Clock Register */\n> +\tu32 apb4enr;\t/* 0xf4 APB4 Clock Register */\n> +};\n> +\n> +#define RCC_AHB3ENR\toffsetof(struct stm32_rcc_regs, ahb3enr)\n> +#define RCC_AHB1ENR\toffsetof(struct stm32_rcc_regs, ahb1enr)\n> +#define RCC_AHB2ENR\toffsetof(struct stm32_rcc_regs, ahb2enr)\n> +#define RCC_AHB4ENR\toffsetof(struct stm32_rcc_regs, ahb4enr)\n> +#define RCC_APB3ENR\toffsetof(struct stm32_rcc_regs, apb3enr)\n> +#define RCC_APB1LENR\toffsetof(struct stm32_rcc_regs, apb1lenr)\n> +#define RCC_APB1HENR\toffsetof(struct stm32_rcc_regs, apb1henr)\n> +#define RCC_APB2ENR\toffsetof(struct stm32_rcc_regs, apb2enr)\n> +#define RCC_APB4ENR\toffsetof(struct stm32_rcc_regs, apb4enr)\n> +\n> +struct clk_cfg {\n> +\tu32 gate_offset;\n> +\tu8 gate_bit_idx;\n> +\tconst char *name;\n> +};\n> +\n> +#define CLK(_gate_offset, _bit_idx, _name) \\\n> +{ \\\n> +\t.gate_offset = _gate_offset,\\\n> +\t.gate_bit_idx = _bit_idx,\\\n> +\t.name = _name,\\\n> +}\n> +\n> +/*\n> + * the way all these entries are sorted in this array could seem\n> + * unlogical, but we are dependant of kernel DT_bindings,\n> + * where clocks are separate in 2 banks, peripheral clocks and\n> + * kernel clocks.\n> + */\n\nit destroys the purpose of device tree if we are embedding all the info in the structure array.\nIn addition expensive in terms of memory usage.\n\n> +\n> +static const struct clk_cfg clk_map[] = {\n> +\tCLK(RCC_AHB3ENR, 31, \"d1sram1\"),\t/* peripheral clocks */\n\nDo we need CLK Macro, {RCC_AHB3ENR, 31, \"d1sram1\"} should work fine.\n\n> +\tCLK(RCC_AHB3ENR, 30, \"itcm\"),\n> +\tCLK(RCC_AHB3ENR, 29, \"dtcm2\"),\n> +\tCLK(RCC_AHB3ENR, 28, \"dtcm1\"),\n> +\tCLK(RCC_AHB3ENR, 8, \"flitf\"),\n> +\tCLK(RCC_AHB3ENR, 5, \"jpgdec\"),\n> +\tCLK(RCC_AHB3ENR, 4, \"dma2d\"),\n> +\tCLK(RCC_AHB3ENR, 0, \"mdma\"),\n> +\tCLK(RCC_AHB1ENR, 28, \"usb2ulpi\"),\n> +\tCLK(RCC_AHB1ENR, 17, \"eth1rx\"),\n> +\tCLK(RCC_AHB1ENR, 16, \"eth1tx\"),\n> +\tCLK(RCC_AHB1ENR, 15, \"eth1mac\"),\n> +\tCLK(RCC_AHB1ENR, 14, \"art\"),\n> +\tCLK(RCC_AHB1ENR, 26, \"usb1ulpi\"),\n> +\tCLK(RCC_AHB1ENR, 1, \"dma2\"),\n> +\tCLK(RCC_AHB1ENR, 0, \"dma1\"),\n> +\tCLK(RCC_AHB2ENR, 31, \"d2sram3\"),\n> +\tCLK(RCC_AHB2ENR, 30, \"d2sram2\"),\n> +\tCLK(RCC_AHB2ENR, 29, \"d2sram1\"),\n> +\tCLK(RCC_AHB2ENR, 5, \"hash\"),\n> +\tCLK(RCC_AHB2ENR, 4, \"crypt\"),\n> +\tCLK(RCC_AHB2ENR, 0, \"camitf\"),\n> +\tCLK(RCC_AHB4ENR, 28, \"bkpram\"),\n> +\tCLK(RCC_AHB4ENR, 25, \"hsem\"),\n> +\tCLK(RCC_AHB4ENR, 21, \"bdma\"),\n> +\tCLK(RCC_AHB4ENR, 19, \"crc\"),\n> +\tCLK(RCC_AHB4ENR, 10, \"gpiok\"),\n> +\tCLK(RCC_AHB4ENR, 9, \"gpioj\"),\n> +\tCLK(RCC_AHB4ENR, 8, \"gpioi\"),\n> +\tCLK(RCC_AHB4ENR, 7, \"gpioh\"),\n> +\tCLK(RCC_AHB4ENR, 6, \"gpiog\"),\n> +\tCLK(RCC_AHB4ENR, 5, \"gpiof\"),\n> +\tCLK(RCC_AHB4ENR, 4, \"gpioe\"),\n> +\tCLK(RCC_AHB4ENR, 3, \"gpiod\"),\n> +\tCLK(RCC_AHB4ENR, 2, \"gpioc\"),\n> +\tCLK(RCC_AHB4ENR, 1, \"gpiob\"),\n> +\tCLK(RCC_AHB4ENR, 0, \"gpioa\"),\n> +\tCLK(RCC_APB3ENR, 6, \"wwdg1\"),\n> +\tCLK(RCC_APB1LENR, 29, \"dac12\"),\n> +\tCLK(RCC_APB1LENR, 11, \"wwdg2\"),\n> +\tCLK(RCC_APB1LENR, 8, \"tim14\"),\n> +\tCLK(RCC_APB1LENR, 7, \"tim13\"),\n> +\tCLK(RCC_APB1LENR, 6, \"tim12\"),\n> +\tCLK(RCC_APB1LENR, 5, \"tim7\"),\n> +\tCLK(RCC_APB1LENR, 4, \"tim6\"),\n> +\tCLK(RCC_APB1LENR, 3, \"tim5\"),\n> +\tCLK(RCC_APB1LENR, 2, \"tim4\"),\n> +\tCLK(RCC_APB1LENR, 1, \"tim3\"),\n> +\tCLK(RCC_APB1LENR, 0, \"tim2\"),\n> +\tCLK(RCC_APB1HENR, 5, \"mdios\"),\n> +\tCLK(RCC_APB1HENR, 4, \"opamp\"),\n> +\tCLK(RCC_APB1HENR, 1, \"crs\"),\n> +\tCLK(RCC_APB2ENR, 18, \"tim17\"),\n> +\tCLK(RCC_APB2ENR, 17, \"tim16\"),\n> +\tCLK(RCC_APB2ENR, 16, \"tim15\"),\n> +\tCLK(RCC_APB2ENR, 1, \"tim8\"),\n> +\tCLK(RCC_APB2ENR, 0, \"tim1\"),\n> +\tCLK(RCC_APB4ENR, 26, \"tmpsens\"),\n> +\tCLK(RCC_APB4ENR, 16, \"rtcapb\"),\n> +\tCLK(RCC_APB4ENR, 15, \"vref\"),\n> +\tCLK(RCC_APB4ENR, 14, \"comp12\"),\n> +\tCLK(RCC_APB4ENR, 1, \"syscfg\"),\n> +\tCLK(RCC_AHB3ENR, 16, \"sdmmc1\"),\t/* kernel clocks */\n> +\tCLK(RCC_AHB3ENR, 14, \"quadspi\"),\n> +\tCLK(RCC_AHB3ENR, 12, \"fmc\"),\n> +\tCLK(RCC_AHB1ENR, 27, \"usb2otg\"),\n> +\tCLK(RCC_AHB1ENR, 25, \"usb1otg\"),\n> +\tCLK(RCC_AHB1ENR, 5, \"adc12\"),\n> +\tCLK(RCC_AHB2ENR, 9, \"sdmmc2\"),\n> +\tCLK(RCC_AHB2ENR, 6, \"rng\"),\n> +\tCLK(RCC_AHB4ENR, 24, \"adc3\"),\n> +\tCLK(RCC_APB3ENR, 4, \"dsi\"),\n> +\tCLK(RCC_APB3ENR, 3, \"ltdc\"),\n> +\tCLK(RCC_APB1LENR, 31, \"usart8\"),\n> +\tCLK(RCC_APB1LENR, 30, \"usart7\"),\n> +\tCLK(RCC_APB1LENR, 27, \"hdmicec\"),\n> +\tCLK(RCC_APB1LENR, 23, \"i2c3\"),\n> +\tCLK(RCC_APB1LENR, 22, \"i2c2\"),\n> +\tCLK(RCC_APB1LENR, 21, \"i2c1\"),\n> +\tCLK(RCC_APB1LENR, 20, \"uart5\"),\n> +\tCLK(RCC_APB1LENR, 19, \"uart4\"),\n> +\tCLK(RCC_APB1LENR, 18, \"usart3\"),\n> +\tCLK(RCC_APB1LENR, 17, \"usart2\"),\n> +\tCLK(RCC_APB1LENR, 16, \"spdifrx\"),\n> +\tCLK(RCC_APB1LENR, 15, \"spi3\"),\n> +\tCLK(RCC_APB1LENR, 14, \"spi2\"),\n> +\tCLK(RCC_APB1LENR, 9, \"lptim1\"),\n> +\tCLK(RCC_APB1HENR, 8, \"fdcan\"),\n> +\tCLK(RCC_APB1HENR, 2, \"swp\"),\n> +\tCLK(RCC_APB2ENR, 29, \"hrtim\"),\n> +\tCLK(RCC_APB2ENR, 28, \"dfsdm1\"),\n> +\tCLK(RCC_APB2ENR, 24, \"sai3\"),\n> +\tCLK(RCC_APB2ENR, 23, \"sai2\"),\n> +\tCLK(RCC_APB2ENR, 22, \"sai1\"),\n> +\tCLK(RCC_APB2ENR, 20, \"spi5\"),\n> +\tCLK(RCC_APB2ENR, 13, \"spi4\"),\n> +\tCLK(RCC_APB2ENR, 12, \"spi1\"),\n> +\tCLK(RCC_APB2ENR, 5, \"usart6\"),\n> +\tCLK(RCC_APB2ENR, 4, \"usart1\"),\n> +\tCLK(RCC_APB4ENR, 21, \"sai4a\"),\n> +\tCLK(RCC_APB4ENR, 21, \"sai4b\"),\n> +\tCLK(RCC_APB4ENR, 12, \"lptim5\"),\n> +\tCLK(RCC_APB4ENR, 11, \"lptim4\"),\n> +\tCLK(RCC_APB4ENR, 10, \"lptim3\"),\n> +\tCLK(RCC_APB4ENR, 9, \"lptim2\"),\n> +\tCLK(RCC_APB4ENR, 7, \"i2c4\"),\n> +\tCLK(RCC_APB4ENR, 5, \"spi6\"),\n> +\tCLK(RCC_APB4ENR, 3, \"lpuart1\"),\n> +};\n> +\n> +struct stm32_clk {\n> +\tstruct stm32_rcc_regs *rcc_base;\n> +\tstruct regmap *pwr_regmap;\n> +};\n> +\n> +struct pll_psc {\n> +\tu8\tdivm;\n> +\tu16\tdivn;\n> +\tu8\tdivp;\n> +\tu8\tdivq;\n> +\tu8\tdivr;\n> +};\n> +\n> +/*\n> + * OSC_HSE = 25 MHz\n> + * VCO = 500MHz\n> + * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz\n> + */\n> +struct pll_psc sys_pll_psc = {\n> +\t.divm = 4,\n> +\t.divn = 80,\n> +\t.divp = 2,\n> +\t.divq = 2,\n> +\t.divr = 2,\n> +};\n> +\n> +int configure_clocks(struct udevice *dev)\n> +{\n> +\tstruct stm32_clk *priv = dev_get_priv(dev);\n> +\tstruct stm32_rcc_regs *regs = priv->rcc_base;\n> +\tuint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);\n> +\tuint32_t pllckselr = 0;\n> +\tuint32_t pll1divr = 0;\n> +\tuint32_t pllcfgr = 0;\n> +\n> +\t/* Switch on HSI */\n> +\tsetbits_le32(®s->cr, RCC_CR_HSION);\n> +\twhile (!(readl(®s->cr) & RCC_CR_HSIRDY))\n> +\t\t;\n> +\n> +\t/* Reset CFGR, now HSI is the default system clock */\n> +\twritel(0, ®s->cfgr);\n> +\n> +\t/* Set all kernel domain clock registers to reset value*/\n> +\twritel(0x0, ®s->d1ccipr);\n> +\twritel(0x0, ®s->d2ccip1r);\n> +\twritel(0x0, ®s->d2ccip2r);\n> +\n> +\t/* Set voltage scaling at scale 1 */\n\npls add info what is scale1\n\n> +\tclrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,\n> +\t\t\tVOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);\n> +\t/* disable step down converter */\n\nis this comment correct ?\n\n> +\tclrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);\n> +\twhile (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))\n> +\t\t;\n> +\n> +\t/* disable HSE to configure it */\n> +\tclrbits_le32(®s->cr, RCC_CR_HSEON);\n> +\twhile ((readl(®s->cr) & RCC_CR_HSERDY))\n> +\t\t;\n> +\n> +\t/* clear HSE bypass and set it ON */\n> +\tclrbits_le32(®s->cr, RCC_CR_HSEBYP);\n> +\t/* Switch on HSE */\n> +\tsetbits_le32(®s->cr, RCC_CR_HSEON);\n> +\twhile (!(readl(®s->cr) & RCC_CR_HSERDY))\n> +\t\t;\n> +\n> +\t/* pll setup, disable it */\n> +\tclrbits_le32(®s->cr, RCC_CR_PLL1ON);\n> +\twhile ((readl(®s->cr) & RCC_CR_PLL1RDY))\n> +\t\t;\n> +\n> +\t/* Select HSE as PLL clock source */\n> +\tpllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;\n> +\tpllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;\n> +\twritel(pllckselr, ®s->pllckselr);\n> +\n> +\tpll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;\n> +\tpll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;\n> +\tpll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;\n> +\tpll1divr |= (sys_pll_psc.divn - 1);\n> +\twritel(pll1divr, ®s->pll1divr);\n> +\n> +\tpllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;\n> +\tpllcfgr |= RCC_PLLCFGR_DIVP1EN;\n> +\tpllcfgr |= RCC_PLLCFGR_DIVQ1EN;\n> +\tpllcfgr |= RCC_PLLCFGR_DIVR1EN;\n> +\twritel(pllcfgr, ®s->pllcfgr);\n> +\n> +\t/* pll setup, enable it */\n> +\tsetbits_le32(®s->cr, RCC_CR_PLL1ON);\n> +\n> +\t/* set HPRE (/2) DI clk --> 125MHz */\n> +\tclrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK,\n> +\t\t\tRCC_D1CFGR_HPRE_DIV2);\n> +\n> +\t/* select PLL1 as system clock source (sys_ck)*/\n> +\tclrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);\n> +\twhile ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)\n> +\t\t;\n> +\n> +\t/* sdram: use pll1_q as fmc_k clk */\n> +\tclrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,\n> +\t\t\tFMCSRC_PLL1_Q_CK);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)\n> +{\n> +\tu32 divider;\n> +\n> +\t/* get HSI divider value */\n> +\tdivider = readl(®s->cr) & RCC_CR_HSIDIV_MASK;\n> +\tdivider = divider >> RCC_CR_HSIDIV_SHIFT;\n> +\n> +\treturn divider;\n> +};\n> +\n> +enum pllsrc {\n> +\tHSE,\n> +\tLSE,\n> +\tHSI,\n> +\tCSI,\n> +\tI2S,\n> +\tTIMER,\n> +\tPLLSRC_NB,\n> +};\n> +\n> +static const char * const pllsrc_name[PLLSRC_NB] = {\n> +\t[HSE] = \"clk-hse\",\n> +\t[LSE] = \"clk-lse\",\n> +\t[HSI] = \"clk-hsi\",\n> +\t[CSI] = \"clk-csi\",\n> +\t[I2S] = \"clk-i2s\",\n> +\t[TIMER] = \"timer-clk\"\n> +};\n> +\n> +static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)\n> +{\n> +\tstruct clk clk;\n> +\tstruct udevice *fixed_clock_dev = NULL;\n> +\tu32 divider;\n> +\tint ret;\n> +\tconst char *name = pllsrc_name[pllsrc];\n> +\n> +\tdebug(\"%s name %s\\n\", __func__, name);\n> +\n> +\tclk.id = 0;\n> +\tret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);\n> +\tif (ret) {\n> +\t\terror(\"Can't find clk %s (%d)\", name, ret);\n> +\t\treturn 0;\n> +\t}\n> +\n> +\tret = clk_request(fixed_clock_dev, &clk);\n> +\tif (ret) {\n> +\t\terror(\"Can't request %s clk (%d)\", name, ret);\n> +\t\treturn 0;\n> +\t}\n> +\n> +\tdivider = 0;\n> +\tif (pllsrc == HSI)\n> +\t\tdivider = stm32_get_HSI_divider(regs);\n> +\n> +\tdebug(\"%s divider %d rate %ld\\n\", __func__,\n> +\t divider, clk_get_rate(&clk));\n> +\n> +\treturn clk_get_rate(&clk) >> divider;\n> +};\n> +\n> +enum pll1_output {\n> +\tPLL1_P_CK,\n> +\tPLL1_Q_CK,\n> +\tPLL1_R_CK,\n> +};\n> +\n> +static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,\n> +\t\t\t enum pll1_output output)\n> +{\n> +\tulong pllsrc = 0;\n> +\tu32 divm1, divn1, divp1, divq1, divr1, fracn1;\n> +\tulong vco, rate;\n> +\n> +\t/* get the PLLSRC */\n> +\tswitch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {\n> +\tcase RCC_PLLCKSELR_PLLSRC_HSI:\n> +\t\tpllsrc = stm32_get_rate(regs, HSI);\n> +\t\tbreak;\n> +\tcase RCC_PLLCKSELR_PLLSRC_CSI:\n> +\t\tpllsrc = stm32_get_rate(regs, CSI);\n> +\t\tbreak;\n> +\tcase RCC_PLLCKSELR_PLLSRC_HSE:\n> +\t\tpllsrc = stm32_get_rate(regs, HSE);\n> +\t\tbreak;\n> +\tcase RCC_PLLCKSELR_PLLSRC_NO_CLK:\n> +\t\t/* shouldn't happen */\n> +\t\terror(\"wrong value for RCC_PLLCKSELR register\\n\");\n> +\t\tpllsrc = 0;\n> +\t\tbreak;\n> +\t}\n> +\n> +\t/* pllsrc = 0 ? no need to go ahead */\n> +\tif (!pllsrc)\n> +\t\treturn pllsrc;\n> +\n> +\t/* get divm1, divp1, divn1 and divr1 */\n> +\tdivm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;\n> +\tdivm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;\n> +\n> +\tdivn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;\n> +\n> +\tdivp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;\n> +\tdivp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;\n> +\n> +\tdivq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;\n> +\tdivq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;\n> +\n> +\tdivr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;\n> +\tdivr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;\n> +\n> +\tfracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;\n> +\tfracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;\n> +\n> +\tvco = (pllsrc / divm1) * divn1;\n> +\trate = (pllsrc * fracn1) / (divm1 * 8192);\n> +\n> +\tdebug(\"%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\\n\",\n> +\t __func__, divm1, divn1, divp1, divq1, divr1);\n> +\tdebug(\"%s fracn1 = %d vco = %ld rate = %ld\\n\",\n> +\t __func__, fracn1, vco, rate);\n> +\n> +\tswitch (output) {\n> +\tcase PLL1_P_CK:\n> +\t\treturn (vco + rate) / divp1;\n> +\t\tbreak;\n> +\tcase PLL1_Q_CK:\n> +\t\treturn (vco + rate) / divq1;\n> +\t\tbreak;\n> +\n> +\tcase PLL1_R_CK:\n> +\t\treturn (vco + rate) / divr1;\n> +\t\tbreak;\n> +\t}\n> +\n> +\treturn -EINVAL;\n> +}\n> +\n> +static ulong stm32_clk_get_rate(struct clk *clk)\n> +{\n> +\tstruct stm32_clk *priv = dev_get_priv(clk->dev);\n> +\tstruct stm32_rcc_regs *regs = priv->rcc_base;\n> +\tulong sysclk = 0;\n> +\tu32 gate_offset;\n> +\tu32 d1cfgr;\n> +\t/* prescaler table lookups for clock computation */\n> +\tu16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};\n> +\tu8 source, idx;\n> +\n> +\t/*\n> +\t * get system clock (sys_ck) source\n> +\t * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck\n> +\t */\n> +\tsource = readl(®s->cfgr) & RCC_CFGR_SW_MASK;\n> +\tswitch (source) {\n> +\tcase RCC_CFGR_SW_PLL1:\n> +\t\tsysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);\n> +\t\tbreak;\n> +\tcase RCC_CFGR_SW_HSE:\n> +\t\tsysclk = stm32_get_rate(regs, HSE);\n> +\t\tbreak;\n> +\n> +\tcase RCC_CFGR_SW_CSI:\n> +\t\tsysclk = stm32_get_rate(regs, CSI);\n> +\t\tbreak;\n> +\n> +\tcase RCC_CFGR_SW_HSI:\n> +\t\tsysclk = stm32_get_rate(regs, HSI);\n> +\t\tbreak;\n> +\t}\n> +\n> +\t/* sysclk = 0 ? no need to go ahead */\n> +\tif (!sysclk)\n> +\t\treturn sysclk;\n> +\n> +\tdebug(\"%s system clock: source = %d freq = %ld\\n\",\n> +\t __func__, source, sysclk);\n> +\n> +\td1cfgr = readl(®s->d1cfgr);\n> +\n> +\tif (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {\n> +\t\t/* get D1 domain Core prescaler */\n> +\t\tidx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>\n> +\t\t RCC_D1CFGR_D1CPRE_SHIFT;\n> +\t\tsysclk = sysclk / prescaler_table[idx];\n> +\t}\n> +\n> +\tif (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {\n> +\t\t/* get D1 domain AHB prescaler */\n> +\t\tidx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;\n> +\t\tsysclk = sysclk / prescaler_table[idx];\n> +\t}\n> +\n> +\tgate_offset = clk_map[clk->id].gate_offset;\n> +\n> +\tdebug(\"%s clk->id=%ld gate_offset=0x%x sysclk=%ld\\n\",\n> +\t __func__, clk->id, gate_offset, sysclk);\n> +\n> +\tswitch (gate_offset) {\n> +\tcase RCC_AHB3ENR:\n> +\tcase RCC_AHB1ENR:\n> +\tcase RCC_AHB2ENR:\n> +\tcase RCC_AHB4ENR:\n> +\t\treturn sysclk;\n> +\t\tbreak;\n> +\n> +\tcase RCC_APB3ENR:\n> +\t\tif (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {\n> +\t\t\t/* get D1 domain APB3 prescaler */\n> +\t\t\tidx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>\n> +\t\t\t RCC_D1CFGR_D1PPRE_SHIFT;\n> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n> +\t\t}\n> +\n> +\t\tdebug(\"%s system clock: freq after APB3 prescaler = %ld\\n\",\n> +\t\t __func__, sysclk);\n> +\n> +\t\treturn sysclk;\n> +\t\tbreak;\n> +\n> +\tcase RCC_APB4ENR:\n> +\t\tif (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {\n> +\t\t\t/* get D3 domain APB4 prescaler */\n> +\t\t\tidx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>\n> +\t\t\t RCC_D3CFGR_D3PPRE_SHIFT;\n> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n> +\t\t}\n> +\n> +\t\tdebug(\"%s system clock: freq after APB4 prescaler = %ld\\n\",\n> +\t\t __func__, sysclk);\n> +\n> +\t\treturn sysclk;\n> +\t\tbreak;\n> +\n> +\tcase RCC_APB1LENR:\n> +\tcase RCC_APB1HENR:\n> +\t\tif (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) {\n> +\t\t\t/* get D2 domain APB1 prescaler */\n> +\t\t\tidx = (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) >>\n> +\t\t\t RCC_D2CFGR_D2PPRE1_SHIFT;\n> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n> +\t\t}\n> +\n> +\t\tdebug(\"%s system clock: freq after APB1 prescaler = %ld\\n\",\n> +\t\t __func__, sysclk);\n> +\n> +\t\treturn sysclk;\n> +\t\tbreak;\n> +\n> +\tcase RCC_APB2ENR:\n> +\t\tif (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) {\n> +\t\t\t/* get D2 domain APB1 prescaler */\n> +\t\t\tidx = (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) >>\n> +\t\t\t RCC_D2CFGR_D2PPRE2_SHIFT;\n> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n> +\t\t}\n> +\n> +\t\tdebug(\"%s system clock: freq after APB2 prescaler = %ld\\n\",\n> +\t\t __func__, sysclk);\n> +\n> +\t\treturn sysclk;\n> +\t\tbreak;\n> +\n> +\tdefault:\n> +\t\terror(\"unexpected gate_offset value (0x%x)\\n\", gate_offset);\n> +\t\treturn -EINVAL;\n> +\t\tbreak;\n> +\t}\n> +}\n> +\n> +static int stm32_clk_enable(struct clk *clk)\n> +{\n> +\tstruct stm32_clk *priv = dev_get_priv(clk->dev);\n> +\tstruct stm32_rcc_regs *regs = priv->rcc_base;\n> +\tu32 gate_offset;\n> +\tu32 gate_bit_index;\n> +\tunsigned long clk_id = clk->id;\n> +\n> +\tgate_offset = clk_map[clk_id].gate_offset;\n> +\tgate_bit_index = clk_map[clk_id].gate_bit_idx;\n> +\n> +\tdebug(\"%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\\n\",\n> +\t __func__, clk->id, gate_offset, gate_bit_index,\n> +\t clk_map[clk_id].name);\n> +\n> +\tsetbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index));\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int stm32_clk_probe(struct udevice *dev)\n> +{\n> +\tstruct stm32_clk *priv = dev_get_priv(dev);\n> +\tstruct udevice *syscon;\n> +\tfdt_addr_t addr;\n> +\tint err;\n> +\n> +\taddr = dev_read_addr(dev);\n> +\tif (addr == FDT_ADDR_T_NONE)\n> +\t\treturn -EINVAL;\n> +\n> +\tpriv->rcc_base = (struct stm32_rcc_regs *)addr;\n> +\n> +\t/* get corresponding syscon phandle */\n> +\terr = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,\n> +\t\t\t\t\t \"st,syscfg\", &syscon);\n> +\n> +\tif (err) {\n> +\t\terror(\"unable to find syscon device\\n\");\n> +\t\treturn err;\n> +\t}\n> +\n> +\tpriv->pwr_regmap = syscon_get_regmap(syscon);\n\nwhy SYSCON_UCLASS...It is used just to get the base address of power control block ?\nIt can be done directly from the phandle also, e.g. fdt_node_offset_by_phandle() or similar.\n\n\nCheers,\nVikas\n\n> +\tif (!priv->pwr_regmap) {\n> +\t\terror(\"unable to find regmap\\n\");\n> +\t\treturn -ENODEV;\n> +\t}\n> +\n> +\tconfigure_clocks(dev);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int stm32_clk_of_xlate(struct clk *clk,\n> +\t\t\tstruct ofnode_phandle_args *args)\n> +{\n> +\tif (args->args_count != 1) {\n> +\t\tdebug(\"Invaild args_count: %d\\n\", args->args_count);\n> +\t\treturn -EINVAL;\n> +\t}\n> +\n> +\tif (args->args_count) {\n> +\t\tclk->id = args->args[0];\n> +\t\t/*\n> +\t\t * this computation convert DT clock index which is used to\n> +\t\t * point into 2 separate clock arrays (peripheral and kernel\n> +\t\t * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)\n> +\t\t * into index to point into only one array where peripheral\n> +\t\t * and kernel clocks are consecutive\n> +\t\t */\n> +\t\tif (clk->id >= KERN_BANK) {\n> +\t\t\tclk->id -= KERN_BANK;\n> +\t\t\tclk->id += LAST_PERIF_BANK - PERIF_BANK + 1;\n> +\t\t} else {\n> +\t\t\tclk->id -= PERIF_BANK;\n> +\t\t}\n> +\t} else {\n> +\t\tclk->id = 0;\n> +\t}\n> +\n> +\tdebug(\"%s clk->id %ld\\n\", __func__, clk->id);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct clk_ops stm32_clk_ops = {\n> +\t.of_xlate\t= stm32_clk_of_xlate,\n> +\t.enable\t\t= stm32_clk_enable,\n> +\t.get_rate\t= stm32_clk_get_rate,\n> +};\n> +\n> +U_BOOT_DRIVER(stm32h7_clk) = {\n> +\t.name\t\t\t= \"stm32h7_rcc_clock\",\n> +\t.id\t\t\t= UCLASS_CLK,\n> +\t.ops\t\t\t= &stm32_clk_ops,\n> +\t.probe\t\t\t= stm32_clk_probe,\n> +\t.priv_auto_alloc_size\t= sizeof(struct stm32_clk),\n> +\t.flags\t\t\t= DM_FLAG_PRE_RELOC,\n> +};\n> diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h\n> new file mode 100644\n> index 0000000..4d87e7e\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/stm32h7-clks.h\n> @@ -0,0 +1,167 @@\n> +/* SYS, CORE AND BUS CLOCKS */\n> +#define SYS_D1CPRE 0\n> +#define HCLK 1\n> +#define PCLK1 2\n> +#define PCLK2 3\n> +#define PCLK3 4\n> +#define PCLK4 5\n> +#define HSI_DIV 6\n> +#define HSE_1M 7\n> +#define I2S_CKIN 8\n> +#define CK_DSI_PHY 9\n> +#define HSE_CK 10\n> +#define LSE_CK 11\n> +#define CSI_KER_DIV122 12\n> +#define RTC_CK 13\n> +#define CPU_SYSTICK 14\n> +\n> +/* OSCILLATOR BANK */\n> +#define OSC_BANK 18\n> +#define HSI_CK 18\n> +#define HSI_KER_CK 19\n> +#define CSI_CK 20\n> +#define CSI_KER_CK 21\n> +#define RC48_CK 22\n> +#define LSI_CK 23\n> +\n> +/* MCLOCK BANK */\n> +#define MCLK_BANK 28\n> +#define PER_CK 28\n> +#define PLLSRC 29\n> +#define SYS_CK 30\n> +#define TRACEIN_CK 31\n> +\n> +/* ODF BANK */\n> +#define ODF_BANK 32\n> +#define PLL1_P 32\n> +#define PLL1_Q 33\n> +#define PLL1_R 34\n> +#define PLL2_P 35\n> +#define PLL2_Q 36\n> +#define PLL2_R 37\n> +#define PLL3_P 38\n> +#define PLL3_Q 39\n> +#define PLL3_R 40\n> +\n> +/* MCO BANK */\n> +#define MCO_BANK 41\n> +#define MCO1 41\n> +#define MCO2 42\n> +\n> +/* PERIF BANK */\n> +#define PERIF_BANK 50\n> +#define D1SRAM1_CK 50\n> +#define ITCM_CK 51\n> +#define DTCM2_CK 52\n> +#define DTCM1_CK 53\n> +#define FLITF_CK 54\n> +#define JPGDEC_CK 55\n> +#define DMA2D_CK 56\n> +#define MDMA_CK 57\n> +#define USB2ULPI_CK 58\n> +#define USB1ULPI_CK 59\n> +#define ETH1RX_CK 60\n> +#define ETH1TX_CK 61\n> +#define ETH1MAC_CK 62\n> +#define ART_CK 63\n> +#define DMA2_CK 64\n> +#define DMA1_CK 65\n> +#define D2SRAM3_CK 66\n> +#define D2SRAM2_CK 67\n> +#define D2SRAM1_CK 68\n> +#define HASH_CK 69\n> +#define CRYPT_CK 70\n> +#define CAMITF_CK 71\n> +#define BKPRAM_CK 72\n> +#define HSEM_CK 73\n> +#define BDMA_CK 74\n> +#define CRC_CK 75\n> +#define GPIOK_CK 76\n> +#define GPIOJ_CK 77\n> +#define GPIOI_CK 78\n> +#define GPIOH_CK 79\n> +#define GPIOG_CK 80\n> +#define GPIOF_CK 81\n> +#define GPIOE_CK 82\n> +#define GPIOD_CK 83\n> +#define GPIOC_CK 84\n> +#define GPIOB_CK 85\n> +#define GPIOA_CK 86\n> +#define WWDG1_CK 87\n> +#define DAC12_CK 88\n> +#define WWDG2_CK 89\n> +#define TIM14_CK 90\n> +#define TIM13_CK 91\n> +#define TIM12_CK 92\n> +#define TIM7_CK 93\n> +#define TIM6_CK 94\n> +#define TIM5_CK 95\n> +#define TIM4_CK 96\n> +#define TIM3_CK 97\n> +#define TIM2_CK 98\n> +#define MDIOS_CK 99\n> +#define OPAMP_CK 100\n> +#define CRS_CK 101\n> +#define TIM17_CK 102\n> +#define TIM16_CK 103\n> +#define TIM15_CK 104\n> +#define TIM8_CK 105\n> +#define TIM1_CK 106\n> +#define TMPSENS_CK 107\n> +#define RTCAPB_CK 108\n> +#define VREF_CK 109\n> +#define COMP12_CK 110\n> +#define SYSCFG_CK 111\n> +/* must be equal to last peripheral clock index */\n> +#define LAST_PERIF_BANK SYSCFG_CK\n> +\n> +/* KERNEL BANK */\n> +#define KERN_BANK 120\n> +#define SDMMC1_CK 120\n> +#define QUADSPI_CK 121\n> +#define FMC_CK 122\n> +#define USB2OTG_CK 123\n> +#define USB1OTG_CK 124\n> +#define ADC12_CK 125\n> +#define SDMMC2_CK 126\n> +#define RNG_CK 127\n> +#define ADC3_CK 128\n> +#define DSI_CK 129\n> +#define LTDC_CK 130\n> +#define USART8_CK 131\n> +#define USART7_CK 132\n> +#define HDMICEC_CK 133\n> +#define I2C3_CK 134\n> +#define I2C2_CK 135\n> +#define I2C1_CK 136\n> +#define UART5_CK 137\n> +#define UART4_CK 138\n> +#define USART3_CK 139\n> +#define USART2_CK 140\n> +#define SPDIFRX_CK 141\n> +#define SPI3_CK 142\n> +#define SPI2_CK 143\n> +#define LPTIM1_CK 144\n> +#define FDCAN_CK 145\n> +#define SWP_CK 146\n> +#define HRTIM_CK 147\n> +#define DFSDM1_CK 148\n> +#define SAI3_CK 149\n> +#define SAI2_CK 150\n> +#define SAI1_CK 151\n> +#define SPI5_CK 152\n> +#define SPI4_CK 153\n> +#define SPI1_CK 154\n> +#define USART6_CK 155\n> +#define USART1_CK 156\n> +#define SAI4B_CK 157\n> +#define SAI4A_CK 158\n> +#define LPTIM5_CK 159\n> +#define LPTIM4_CK 160\n> +#define LPTIM3_CK 161\n> +#define LPTIM2_CK 162\n> +#define I2C4_CK 163\n> +#define SPI6_CK 164\n> +#define LPUART1_CK 165\n> +\n> +#define STM32H7_MAX_CLKS 166\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxjhD5zGjz9sBW\n\tfor ;\n\tWed, 20 Sep 2017 12:03:23 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 1F2BEC21D72; Wed, 20 Sep 2017 02:03:21 +0000 (UTC)","from lists.denx.de (localhost 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Gecko/20100101\n\tThunderbird/45.3.0","MIME-Version":"1.0","In-Reply-To":"<1505318412-27121-4-git-send-email-patrice.chotard@st.com>","X-Originating-IP":"[10.75.127.44]","X-ClientProxiedBy":"SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG7NODE3.st.com\n\t(10.75.127.21)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-19_11:, , signatures=0","Subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1773665,"web_url":"http://patchwork.ozlabs.org/comment/1773665/","msgid":"<20170922141918.GK30205@bill-the-cat>","list_archive_url":null,"date":"2017-09-22T14:19:18","subject":"Re: [U-Boot] [U-Boot, v2,\n\t3/9] dm: clk: add clk driver support for stm32h7 SoCs","submitter":{"id":65875,"url":"http://patchwork.ozlabs.org/api/people/65875/","name":"Tom Rini","email":"trini@konsulko.com"},"content":"On Wed, Sep 13, 2017 at 06:00:06PM +0200, patrice.chotard@st.com wrote:\n\n> From: Patrice Chotard \n> \n> This driver implements basic clock setup, only clock gating\n> is implemented.\n> \n> This driver doesn't implement .of_match as it's binded\n> by MFD RCC driver.\n> \n> Files include/dt-bindings/clock/stm32h7-clks.h and\n> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> will be available soon in a kernel tag, as all the\n> bindings have been acked by Rob Herring [1].\n> \n> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n> \n> Signed-off-by: Patrice Chotard \n> Reviewed-by: Simon Glass \n\nApplied to u-boot/master, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=konsulko.com header.i=@konsulko.com\n\theader.b=\"kdVM0A1A\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xzGG11sQwz9sP1\n\tfor ;\n\tSat, 23 Sep 2017 00:34:33 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 12B82C220DB; Fri, 22 Sep 2017 14:27:07 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 99C0BC220A6;\n\tFri, 22 Sep 2017 14:26:46 +0000 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","To":"patrice.chotard@st.com","Message-ID":"<20170922141918.GK30205@bill-the-cat>","References":"<1505318412-27121-4-git-send-email-patrice.chotard@st.com>","MIME-Version":"1.0","In-Reply-To":"<1505318412-27121-4-git-send-email-patrice.chotard@st.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] [U-Boot, v2,\n\t3/9] dm: clk: add clk driver support for stm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"multipart/mixed;\n\tboundary=\"===============5505505978749899978==\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1774489,"web_url":"http://patchwork.ozlabs.org/comment/1774489/","msgid":"","list_archive_url":null,"date":"2017-09-25T07:51:12","subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","submitter":{"id":63958,"url":"http://patchwork.ozlabs.org/api/people/63958/","name":"Patrice CHOTARD","email":"patrice.chotard@st.com"},"content":"Hi Vikas\n\nOn 09/20/2017 03:39 AM, Vikas Manocha wrote:\n> Hi Patrice,\n> \n> On 09/13/2017 09:00 AM, patrice.chotard@st.com wrote:\n>> From: Patrice Chotard \n>>\n>> This driver implements basic clock setup, only clock gating\n>> is implemented.\n>>\n>> This driver doesn't implement .of_match as it's binded\n>> by MFD RCC driver.\n>>\n>> Files include/dt-bindings/clock/stm32h7-clks.h and\n>> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n>> will be available soon in a kernel tag, as all the\n>> bindings have been acked by Rob Herring [1].\n>>\n>> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n>>\n>> Signed-off-by: Patrice Chotard \n>> ---\n>> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt | 152 ++++\n>> drivers/clk/Makefile | 1 +\n>> drivers/clk/clk_stm32h7.c | 802 ++++++++++++++++++++++\n>> include/dt-bindings/clock/stm32h7-clks.h | 167 +++++\n>> 4 files changed, 1122 insertions(+)\n>> create mode 100644 doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n>> create mode 100644 drivers/clk/clk_stm32h7.c\n>> create mode 100644 include/dt-bindings/clock/stm32h7-clks.h\n>>\n>> diff --git a/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n>> new file mode 100644\n>> index 0000000..9d4b587\n>> --- /dev/null\n>> +++ b/doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n>> @@ -0,0 +1,152 @@\n>> +STMicroelectronics STM32H7 Reset and Clock Controller\n>> +=====================================================\n>> +\n>> +The RCC IP is both a reset and a clock controller.\n>> +\n>> +Please refer to clock-bindings.txt for common clock controller binding usage.\n>> +Please also refer to reset.txt for common reset controller binding usage.\n>> +\n>> +Required properties:\n>> +- compatible: Should be:\n>> + \"st,stm32h743-rcc\"\n>> +\n>> +- reg: should be register base and length as documented in the\n>> + datasheet\n>> +\n>> +- #reset-cells: 1, see below\n>> +\n>> +- #clock-cells : from common clock binding; shall be set to 1\n>> +\n>> +- clocks: External oscillator clock phandle\n>> + - high speed external clock signal (HSE)\n>> + - low speed external clock signal (LSE)\n>> + - external I2S clock (I2S_CKIN)\n>> +\n>> +- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain\n>> + write protection (RTC clock).\n> \n> st,syscfg is confusing if we are using it for PWR or SYSCFG peripheral of the device.\n> Also why company name to reference the phandle, it can just be syscfg or better something like pwr_xxx as we it pointing to pwrcfg phandle.\n\nI didn't get the history of this compatible string, we heritate it from \nkernel.\n\n> \n>> +\n>> +- pll x node: Allow to register a pll with specific parameters.\n>> + Please see PLL section below.\n>> +\n>> +Example:\n>> +\n>> +\trcc: rcc@58024400 {\n>> +\t\t#reset-cells = <1>;\n>> +\t\t#clock-cells = <2>\n>> +\t\tcompatible = \"st,stm32h743-rcc\", \"st,stm32-rcc\";\n>> +\t\treg = <0x58024400 0x400>;\n>> +\t\tclocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;\n>> +\n>> +\t\tst,syscfg = <&pwrcfg>;\n> \n> see above.\n> \n>> +\n>> +\t\t#address-cells = <1>;\n>> +\t\t#size-cells = <0>;\n>> +\n>> +\t\tvco1@58024430 {\n>> +\t\t\t#clock-cells = <0>;\n>> +\t\t\tcompatible = \"stm32,pll\";\n>> +\t\t\treg = <0>;\n>> +\t\t};\n>> +\n>> +\t\tvco2@58024438 {\n>> +\t\t\t#clock-cells = <0>;\n>> +\t\t\tcompatible = \"stm32,pll\";\n>> +\t\t\treg = <1>;\n>> +\t\t\tst,clock-div = <2>;\n>> +\t\t\tst,clock-mult = <40>;\n>> +\t\t\tst,frac-status = <0>;\n>> +\t\t\tst,frac = <0>;\n>> +\t\t\tst,vcosel = <1>;\n>> +\t\t\tst,pllrge = <2>;\n>> +\t\t};\n>> +\t};\n>> +\n>> +\n>> +STM32H7 PLL\n>> +-----------\n>> +\n>> +The VCO of STM32 PLL could be reprensented like this:\n>> +\n>> + Vref --------- --------\n>> + ---->| / DIVM |---->| x DIVN | ------> VCO\n>> + --------- --------\n>> +\t\t ^\n>> +\t\t\t |\n>> +\t -------\n>> +\t\t | FRACN |\n>> +\t\t -------\n>> +\n>> +When the PLL is configured in integer mode:\n>> +- VCO = ( Vref / DIVM ) * DIVN\n>> +\n>> +When the PLL is configured in fractional mode:\n>> +- VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)\n>> +\n>> +\n>> +Required properties for pll node:\n>> +- compatible: Should be:\n>> + \"stm32,pll\"\n>> +\n>> +- #clock-cells: from common clock binding; shall be set to 0\n>> +- reg: Should be the pll number.\n>> +\n>> +Optional properties:\n>> +- st,clock-div: DIVM division factor : <1..63>\n>> +- st,clock-mult: DIVN multiplication factor : <4..512>\n>> +\n>> +- st,frac-status:\n>> + - 0 Pll is configured in integer mode\n>> + - 1 Pll is configure in fractional mode\n>> +\n>> +- st,frac: Fractional part of the multiplication factor : <0..8191>\n>> +\n>> +- st,vcosel: VCO selection\n>> + - 0: Wide VCO range:192 to 836 MHz\n>> + - 1: Medium VCO range:150 to 420 MHz\n>> +\n>> +- st,pllrge: PLL input frequency range\n>> + - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz\n>> + - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz\n>> + - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz\n>> + - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz\n>> +\n>> +\n>> +The peripheral clock consumer should specify the desired clock by\n>> +having the clock ID in its \"clocks\" phandle cell.\n>> +\n>> +All available clocks are defined as preprocessor macros in\n>> +dt-bindings/clock/stm32h7-clks.h header and can be used in device\n>> +tree sources.\n>> +\n>> +Example:\n>> +\n>> +\t\ttimer5: timer@40000c00 {\n>> +\t\t\tcompatible = \"st,stm32-timer\";\n>> +\t\t\treg = <0x40000c00 0x400>;\n>> +\t\t\tinterrupts = <50>;\n>> +\t\t\tclocks = <&rcc TIM5_CK>;\n>> +\n>> +\t\t};\n>> +\n>> +Specifying softreset control of devices\n>> +=======================================\n>> +\n>> +Device nodes should specify the reset channel required in their \"resets\"\n>> +property, containing a phandle to the reset device node and an index specifying\n>> +which channel to use.\n>> +The index is the bit number within the RCC registers bank, starting from RCC\n>> +base address.\n>> +It is calculated as: index = register_offset / 4 * 32 + bit_offset.\n>> +Where bit_offset is the bit offset within the register.\n>> +\n>> +For example, for CRC reset:\n>> + crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107\n>> +\n>> +All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h\n>> +header and can be used in device tree sources.\n>> +\n>> +example:\n>> +\n>> +\ttimer2 {\n>> +\t\tresets\t= <&rcc STM32H7_APB1L_RESET(TIM2)>;\n>> +\t};\n>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n>> index b773593..83fe88c 100644\n>> --- a/drivers/clk/Makefile\n>> +++ b/drivers/clk/Makefile\n>> @@ -22,3 +22,4 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o\n>> obj-$(CONFIG_CLK_BOSTON) += clk_boston.o\n>> obj-$(CONFIG_ARCH_ASPEED) += aspeed/\n>> obj-$(CONFIG_STM32F7) += clk_stm32f7.o\n>> +obj-$(CONFIG_STM32H7) += clk_stm32h7.o\n>> diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c\n>> new file mode 100644\n>> index 0000000..fd0e3ab\n>> --- /dev/null\n>> +++ b/drivers/clk/clk_stm32h7.c\n>> @@ -0,0 +1,802 @@\n>> +/*\n>> + * Copyright (C) STMicroelectronics SA 2017\n>> + * Author(s): Patrice CHOTARD, for STMicroelectronics.\n>> + *\n>> + * SPDX-License-Identifier:\tGPL-2.0+\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#include \n>> +\n>> +DECLARE_GLOBAL_DATA_PTR;\n>> +\n>> +/* RCC CR specific definitions */\n>> +#define RCC_CR_HSION\t\t\tBIT(0)\n>> +#define RCC_CR_HSIRDY\t\t\tBIT(2)\n>> +\n>> +#define RCC_CR_HSEON\t\t\tBIT(16)\n>> +#define RCC_CR_HSERDY\t\t\tBIT(17)\n>> +#define RCC_CR_HSEBYP\t\t\tBIT(18)\n>> +#define RCC_CR_PLL1ON\t\t\tBIT(24)\n>> +#define RCC_CR_PLL1RDY\t\t\tBIT(25)\n>> +\n>> +#define RCC_CR_HSIDIV_MASK\t\tGENMASK(4, 3)\n>> +#define RCC_CR_HSIDIV_SHIFT\t\t3\n>> +\n>> +#define RCC_CFGR_SW_MASK\t\tGENMASK(2, 0)\n>> +#define RCC_CFGR_SW_HSI\t\t\t0\n>> +#define RCC_CFGR_SW_CSI\t\t\t1\n>> +#define RCC_CFGR_SW_HSE\t\t\t2\n>> +#define RCC_CFGR_SW_PLL1\t\t3\n>> +\n>> +#define RCC_PLLCKSELR_PLLSRC_HSI\t0\n>> +#define RCC_PLLCKSELR_PLLSRC_CSI\t1\n>> +#define RCC_PLLCKSELR_PLLSRC_HSE\t2\n>> +#define RCC_PLLCKSELR_PLLSRC_NO_CLK\t3\n>> +\n>> +#define RCC_PLLCKSELR_PLLSRC_MASK\tGENMASK(1, 0)\n>> +\n>> +#define RCC_PLLCKSELR_DIVM1_SHIFT\t4\n>> +#define RCC_PLLCKSELR_DIVM1_MASK\tGENMASK(9, 4)\n>> +\n>> +#define RCC_PLL1DIVR_DIVN1_MASK\t\tGENMASK(8, 0)\n>> +\n>> +#define RCC_PLL1DIVR_DIVP1_SHIFT\t9\n>> +#define RCC_PLL1DIVR_DIVP1_MASK\t\tGENMASK(15, 9)\n>> +\n>> +#define RCC_PLL1DIVR_DIVQ1_SHIFT\t16\n>> +#define RCC_PLL1DIVR_DIVQ1_MASK\t\tGENMASK(22, 16)\n>> +\n>> +#define RCC_PLL1DIVR_DIVR1_SHIFT\t24\n>> +#define RCC_PLL1DIVR_DIVR1_MASK\t\tGENMASK(30, 24)\n>> +\n>> +#define RCC_PLL1FRACR_FRACN1_SHIFT\t3\n>> +#define RCC_PLL1FRACR_FRACN1_MASK\tGENMASK(15, 3)\n>> +\n>> +#define RCC_PLLCFGR_PLL1RGE_SHIFT\t2\n>> +#define\t\tPLL1RGE_1_2_MHZ\t\t0\n>> +#define\t\tPLL1RGE_2_4_MHZ\t\t1\n>> +#define\t\tPLL1RGE_4_8_MHZ\t\t2\n>> +#define\t\tPLL1RGE_8_16_MHZ\t3\n>> +#define RCC_PLLCFGR_DIVP1EN\t\tBIT(16)\n>> +#define RCC_PLLCFGR_DIVQ1EN\t\tBIT(17)\n>> +#define RCC_PLLCFGR_DIVR1EN\t\tBIT(18)\n>> +\n>> +#define RCC_D1CFGR_HPRE_MASK\t\tGENMASK(3, 0)\n>> +#define RCC_D1CFGR_HPRE_DIVIDED\t\tBIT(3)\n>> +#define RCC_D1CFGR_HPRE_DIVIDER\t\tGENMASK(2, 0)\n>> +\n>> +#define RCC_D1CFGR_HPRE_DIV2\t\t8\n>> +\n>> +#define RCC_D1CFGR_D1PPRE_SHIFT\t\t4\n>> +#define RCC_D1CFGR_D1PPRE_DIVIDED\tBIT(6)\n>> +#define RCC_D1CFGR_D1PPRE_DIVIDER\tGENMASK(5, 4)\n>> +\n>> +#define RCC_D1CFGR_D1CPRE_SHIFT\t\t8\n>> +#define RCC_D1CFGR_D1CPRE_DIVIDER\tGENMASK(10, 8)\n>> +#define RCC_D1CFGR_D1CPRE_DIVIDED\tBIT(11)\n>> +\n>> +#define RCC_D2CFGR_D2PPRE1_SHIFT\t4\n>> +#define RCC_D2CFGR_D2PPRE1_DIVIDED\tBIT(6)\n>> +#define RCC_D2CFGR_D2PPRE1_DIVIDER\tGENMASK(5, 4)\n>> +\n>> +#define RCC_D2CFGR_D2PPRE2_SHIFT\t8\n>> +#define RCC_D2CFGR_D2PPRE2_DIVIDED\tBIT(10)\n>> +#define RCC_D2CFGR_D2PPRE2_DIVIDER\tGENMASK(9, 8)\n>> +\n>> +#define RCC_D3CFGR_D3PPRE_SHIFT\t\t4\n>> +#define RCC_D3CFGR_D3PPRE_DIVIDED\tBIT(6)\n>> +#define RCC_D3CFGR_D3PPRE_DIVIDER\tGENMASK(5, 4)\n>> +\n>> +#define RCC_D1CCIPR_FMCSRC_MASK\t\tGENMASK(1, 0)\n>> +#define\t\tFMCSRC_HCLKD1\t\t0\n>> +#define\t\tFMCSRC_PLL1_Q_CK\t1\n>> +#define\t\tFMCSRC_PLL2_R_CK\t2\n>> +#define\t\tFMCSRC_PER_CK\t\t3\n>> +\n>> +#define RCC_D1CCIPR_QSPISRC_MASK\tGENMASK(5, 4)\n>> +#define RCC_D1CCIPR_QSPISRC_SHIFT\t4\n>> +#define\t\tQSPISRC_HCLKD1\t\t0\n>> +#define\t\tQSPISRC_PLL1_Q_CK\t1\n>> +#define\t\tQSPISRC_PLL2_R_CK\t2\n>> +#define\t\tQSPISRC_PER_CK\t\t3\n>> +\n>> +#define PWR_CR3\t\t\t\t0x0c\n>> +#define PWR_CR3_SDEN\t\t\tBIT(2)\n> \n> Can we use SCUEN suffix to match the Ref Manual.\n\nWhich version of reference manual do you use ? in mine its SDEN, but i \npropably use a too old ref manual.\n\n> \n>> +#define PWR_D3CR\t\t\t0x18\n>> +#define PWR_D3CR_VOS_MASK\t\tGENMASK(15, 14)\n>> +#define PWR_D3CR_VOS_SHIFT\t\t14\n>> +#define\t\tVOS_SCALE_3\t\t1\n>> +#define\t\tVOS_SCALE_2\t\t2\n>> +#define\t\tVOS_SCALE_1\t\t3\n>> +#define PWR_D3CR_VOSREADY\t\tBIT(13)\n>> +\n>> +struct stm32_rcc_regs {\n>> +\tu32 cr;\t\t/* 0x00 Source Control Register */\n>> +\tu32 icscr;\t/* 0x04 Internal Clock Source Calibration Register */\n>> +\tu32 crrcr;\t/* 0x08 Clock Recovery RC Register */\n>> +\tu32 reserved1;\t/* 0x0c reserved */\n>> +\tu32 cfgr;\t/* 0x10 Clock Configuration Register */\n>> +\tu32 reserved2;\t/* 0x14 reserved */\n>> +\tu32 d1cfgr;\t/* 0x18 Domain 1 Clock Configuration Register */\n>> +\tu32 d2cfgr;\t/* 0x1c Domain 2 Clock Configuration Register */\n>> +\tu32 d3cfgr;\t/* 0x20 Domain 3 Clock Configuration Register */\n>> +\tu32 reserved3;\t/* 0x24 reserved */\n>> +\tu32 pllckselr;\t/* 0x28 PLLs Clock Source Selection Register */\n>> +\tu32 pllcfgr;\t/* 0x2c PLLs Configuration Register */\n>> +\tu32 pll1divr;\t/* 0x30 PLL1 Dividers Configuration Register */\n>> +\tu32 pll1fracr;\t/* 0x34 PLL1 Fractional Divider Register */\n>> +\tu32 pll2divr;\t/* 0x38 PLL2 Dividers Configuration Register */\n>> +\tu32 pll2fracr;\t/* 0x3c PLL2 Fractional Divider Register */\n>> +\tu32 pll3divr;\t/* 0x40 PLL3 Dividers Configuration Register */\n>> +\tu32 pll3fracr;\t/* 0x44 PLL3 Fractional Divider Register */\n>> +\tu32 reserved4;\t/* 0x48 reserved */\n>> +\tu32 d1ccipr;\t/* 0x4c Domain 1 Kernel Clock Configuration Register */\n>> +\tu32 d2ccip1r;\t/* 0x50 Domain 2 Kernel Clock Configuration Register */\n>> +\tu32 d2ccip2r;\t/* 0x54 Domain 2 Kernel Clock Configuration Register */\n>> +\tu32 d3ccipr;\t/* 0x58 Domain 3 Kernel Clock Configuration Register */\n>> +\tu32 reserved5;\t/* 0x5c reserved */\n>> +\tu32 cier;\t/* 0x60 Clock Source Interrupt Enable Register */\n>> +\tu32 cifr;\t/* 0x64 Clock Source Interrupt Flag Register */\n>> +\tu32 cicr;\t/* 0x68 Clock Source Interrupt Clear Register */\n>> +\tu32 reserved6;\t/* 0x6c reserved */\n>> +\tu32 bdcr;\t/* 0x70 Backup Domain Control Register */\n>> +\tu32 csr;\t/* 0x74 Clock Control and Status Register */\n>> +\tu32 reserved7;\t/* 0x78 reserved */\n>> +\n>> +\tu32 ahb3rstr;\t/* 0x7c AHB3 Peripheral Reset Register */\n>> +\tu32 ahb1rstr;\t/* 0x80 AHB1 Peripheral Reset Register */\n>> +\tu32 ahb2rstr;\t/* 0x84 AHB2 Peripheral Reset Register */\n>> +\tu32 ahb4rstr;\t/* 0x88 AHB4 Peripheral Reset Register */\n>> +\n>> +\tu32 apb3rstr;\t/* 0x8c APB3 Peripheral Reset Register */\n>> +\tu32 apb1lrstr;\t/* 0x90 APB1 low Peripheral Reset Register */\n>> +\tu32 apb1hrstr;\t/* 0x94 APB1 high Peripheral Reset Register */\n>> +\tu32 apb2rstr;\t/* 0x98 APB2 Clock Register */\n>> +\tu32 apb4rstr;\t/* 0x9c APB4 Clock Register */\n>> +\n>> +\tu32 gcr;\t/* 0xa0 Global Control Register */\n>> +\tu32 reserved8;\t/* 0xa4 reserved */\n>> +\tu32 d3amr;\t/* 0xa8 D3 Autonomous mode Register */\n>> +\tu32 reserved9[9];/* 0xac to 0xcc reserved */\n>> +\tu32 rsr;\t/* 0xd0 Reset Status Register */\n>> +\tu32 ahb3enr;\t/* 0xd4 AHB3 Clock Register */\n>> +\tu32 ahb1enr;\t/* 0xd8 AHB1 Clock Register */\n>> +\tu32 ahb2enr;\t/* 0xdc AHB2 Clock Register */\n>> +\tu32 ahb4enr;\t/* 0xe0 AHB4 Clock Register */\n>> +\n>> +\tu32 apb3enr;\t/* 0xe4 APB3 Clock Register */\n>> +\tu32 apb1lenr;\t/* 0xe8 APB1 low Clock Register */\n>> +\tu32 apb1henr;\t/* 0xec APB1 high Clock Register */\n>> +\tu32 apb2enr;\t/* 0xf0 APB2 Clock Register */\n>> +\tu32 apb4enr;\t/* 0xf4 APB4 Clock Register */\n>> +};\n>> +\n>> +#define RCC_AHB3ENR\toffsetof(struct stm32_rcc_regs, ahb3enr)\n>> +#define RCC_AHB1ENR\toffsetof(struct stm32_rcc_regs, ahb1enr)\n>> +#define RCC_AHB2ENR\toffsetof(struct stm32_rcc_regs, ahb2enr)\n>> +#define RCC_AHB4ENR\toffsetof(struct stm32_rcc_regs, ahb4enr)\n>> +#define RCC_APB3ENR\toffsetof(struct stm32_rcc_regs, apb3enr)\n>> +#define RCC_APB1LENR\toffsetof(struct stm32_rcc_regs, apb1lenr)\n>> +#define RCC_APB1HENR\toffsetof(struct stm32_rcc_regs, apb1henr)\n>> +#define RCC_APB2ENR\toffsetof(struct stm32_rcc_regs, apb2enr)\n>> +#define RCC_APB4ENR\toffsetof(struct stm32_rcc_regs, apb4enr)\n>> +\n>> +struct clk_cfg {\n>> +\tu32 gate_offset;\n>> +\tu8 gate_bit_idx;\n>> +\tconst char *name;\n>> +};\n>> +\n>> +#define CLK(_gate_offset, _bit_idx, _name) \\\n>> +{ \\\n>> +\t.gate_offset = _gate_offset,\\\n>> +\t.gate_bit_idx = _bit_idx,\\\n>> +\t.name = _name,\\\n>> +}\n>> +\n>> +/*\n>> + * the way all these entries are sorted in this array could seem\n>> + * unlogical, but we are dependant of kernel DT_bindings,\n>> + * where clocks are separate in 2 banks, peripheral clocks and\n>> + * kernel clocks.\n>> + */\n> \n> it destroys the purpose of device tree if we are embedding all the info in the structure array.\n> In addition expensive in terms of memory usage.\n> \n>> +\n>> +static const struct clk_cfg clk_map[] = {\n>> +\tCLK(RCC_AHB3ENR, 31, \"d1sram1\"),\t/* peripheral clocks */\n> \n> Do we need CLK Macro, {RCC_AHB3ENR, 31, \"d1sram1\"} should work fine.\n\nAgree, it's a residue of my rework, i will send a fix for this\n\n> \n>> +\tCLK(RCC_AHB3ENR, 30, \"itcm\"),\n>> +\tCLK(RCC_AHB3ENR, 29, \"dtcm2\"),\n>> +\tCLK(RCC_AHB3ENR, 28, \"dtcm1\"),\n>> +\tCLK(RCC_AHB3ENR, 8, \"flitf\"),\n>> +\tCLK(RCC_AHB3ENR, 5, \"jpgdec\"),\n>> +\tCLK(RCC_AHB3ENR, 4, \"dma2d\"),\n>> +\tCLK(RCC_AHB3ENR, 0, \"mdma\"),\n>> +\tCLK(RCC_AHB1ENR, 28, \"usb2ulpi\"),\n>> +\tCLK(RCC_AHB1ENR, 17, \"eth1rx\"),\n>> +\tCLK(RCC_AHB1ENR, 16, \"eth1tx\"),\n>> +\tCLK(RCC_AHB1ENR, 15, \"eth1mac\"),\n>> +\tCLK(RCC_AHB1ENR, 14, \"art\"),\n>> +\tCLK(RCC_AHB1ENR, 26, \"usb1ulpi\"),\n>> +\tCLK(RCC_AHB1ENR, 1, \"dma2\"),\n>> +\tCLK(RCC_AHB1ENR, 0, \"dma1\"),\n>> +\tCLK(RCC_AHB2ENR, 31, \"d2sram3\"),\n>> +\tCLK(RCC_AHB2ENR, 30, \"d2sram2\"),\n>> +\tCLK(RCC_AHB2ENR, 29, \"d2sram1\"),\n>> +\tCLK(RCC_AHB2ENR, 5, \"hash\"),\n>> +\tCLK(RCC_AHB2ENR, 4, \"crypt\"),\n>> +\tCLK(RCC_AHB2ENR, 0, \"camitf\"),\n>> +\tCLK(RCC_AHB4ENR, 28, \"bkpram\"),\n>> +\tCLK(RCC_AHB4ENR, 25, \"hsem\"),\n>> +\tCLK(RCC_AHB4ENR, 21, \"bdma\"),\n>> +\tCLK(RCC_AHB4ENR, 19, \"crc\"),\n>> +\tCLK(RCC_AHB4ENR, 10, \"gpiok\"),\n>> +\tCLK(RCC_AHB4ENR, 9, \"gpioj\"),\n>> +\tCLK(RCC_AHB4ENR, 8, \"gpioi\"),\n>> +\tCLK(RCC_AHB4ENR, 7, \"gpioh\"),\n>> +\tCLK(RCC_AHB4ENR, 6, \"gpiog\"),\n>> +\tCLK(RCC_AHB4ENR, 5, \"gpiof\"),\n>> +\tCLK(RCC_AHB4ENR, 4, \"gpioe\"),\n>> +\tCLK(RCC_AHB4ENR, 3, \"gpiod\"),\n>> +\tCLK(RCC_AHB4ENR, 2, \"gpioc\"),\n>> +\tCLK(RCC_AHB4ENR, 1, \"gpiob\"),\n>> +\tCLK(RCC_AHB4ENR, 0, \"gpioa\"),\n>> +\tCLK(RCC_APB3ENR, 6, \"wwdg1\"),\n>> +\tCLK(RCC_APB1LENR, 29, \"dac12\"),\n>> +\tCLK(RCC_APB1LENR, 11, \"wwdg2\"),\n>> +\tCLK(RCC_APB1LENR, 8, \"tim14\"),\n>> +\tCLK(RCC_APB1LENR, 7, \"tim13\"),\n>> +\tCLK(RCC_APB1LENR, 6, \"tim12\"),\n>> +\tCLK(RCC_APB1LENR, 5, \"tim7\"),\n>> +\tCLK(RCC_APB1LENR, 4, \"tim6\"),\n>> +\tCLK(RCC_APB1LENR, 3, \"tim5\"),\n>> +\tCLK(RCC_APB1LENR, 2, \"tim4\"),\n>> +\tCLK(RCC_APB1LENR, 1, \"tim3\"),\n>> +\tCLK(RCC_APB1LENR, 0, \"tim2\"),\n>> +\tCLK(RCC_APB1HENR, 5, \"mdios\"),\n>> +\tCLK(RCC_APB1HENR, 4, \"opamp\"),\n>> +\tCLK(RCC_APB1HENR, 1, \"crs\"),\n>> +\tCLK(RCC_APB2ENR, 18, \"tim17\"),\n>> +\tCLK(RCC_APB2ENR, 17, \"tim16\"),\n>> +\tCLK(RCC_APB2ENR, 16, \"tim15\"),\n>> +\tCLK(RCC_APB2ENR, 1, \"tim8\"),\n>> +\tCLK(RCC_APB2ENR, 0, \"tim1\"),\n>> +\tCLK(RCC_APB4ENR, 26, \"tmpsens\"),\n>> +\tCLK(RCC_APB4ENR, 16, \"rtcapb\"),\n>> +\tCLK(RCC_APB4ENR, 15, \"vref\"),\n>> +\tCLK(RCC_APB4ENR, 14, \"comp12\"),\n>> +\tCLK(RCC_APB4ENR, 1, \"syscfg\"),\n>> +\tCLK(RCC_AHB3ENR, 16, \"sdmmc1\"),\t/* kernel clocks */\n>> +\tCLK(RCC_AHB3ENR, 14, \"quadspi\"),\n>> +\tCLK(RCC_AHB3ENR, 12, \"fmc\"),\n>> +\tCLK(RCC_AHB1ENR, 27, \"usb2otg\"),\n>> +\tCLK(RCC_AHB1ENR, 25, \"usb1otg\"),\n>> +\tCLK(RCC_AHB1ENR, 5, \"adc12\"),\n>> +\tCLK(RCC_AHB2ENR, 9, \"sdmmc2\"),\n>> +\tCLK(RCC_AHB2ENR, 6, \"rng\"),\n>> +\tCLK(RCC_AHB4ENR, 24, \"adc3\"),\n>> +\tCLK(RCC_APB3ENR, 4, \"dsi\"),\n>> +\tCLK(RCC_APB3ENR, 3, \"ltdc\"),\n>> +\tCLK(RCC_APB1LENR, 31, \"usart8\"),\n>> +\tCLK(RCC_APB1LENR, 30, \"usart7\"),\n>> +\tCLK(RCC_APB1LENR, 27, \"hdmicec\"),\n>> +\tCLK(RCC_APB1LENR, 23, \"i2c3\"),\n>> +\tCLK(RCC_APB1LENR, 22, \"i2c2\"),\n>> +\tCLK(RCC_APB1LENR, 21, \"i2c1\"),\n>> +\tCLK(RCC_APB1LENR, 20, \"uart5\"),\n>> +\tCLK(RCC_APB1LENR, 19, \"uart4\"),\n>> +\tCLK(RCC_APB1LENR, 18, \"usart3\"),\n>> +\tCLK(RCC_APB1LENR, 17, \"usart2\"),\n>> +\tCLK(RCC_APB1LENR, 16, \"spdifrx\"),\n>> +\tCLK(RCC_APB1LENR, 15, \"spi3\"),\n>> +\tCLK(RCC_APB1LENR, 14, \"spi2\"),\n>> +\tCLK(RCC_APB1LENR, 9, \"lptim1\"),\n>> +\tCLK(RCC_APB1HENR, 8, \"fdcan\"),\n>> +\tCLK(RCC_APB1HENR, 2, \"swp\"),\n>> +\tCLK(RCC_APB2ENR, 29, \"hrtim\"),\n>> +\tCLK(RCC_APB2ENR, 28, \"dfsdm1\"),\n>> +\tCLK(RCC_APB2ENR, 24, \"sai3\"),\n>> +\tCLK(RCC_APB2ENR, 23, \"sai2\"),\n>> +\tCLK(RCC_APB2ENR, 22, \"sai1\"),\n>> +\tCLK(RCC_APB2ENR, 20, \"spi5\"),\n>> +\tCLK(RCC_APB2ENR, 13, \"spi4\"),\n>> +\tCLK(RCC_APB2ENR, 12, \"spi1\"),\n>> +\tCLK(RCC_APB2ENR, 5, \"usart6\"),\n>> +\tCLK(RCC_APB2ENR, 4, \"usart1\"),\n>> +\tCLK(RCC_APB4ENR, 21, \"sai4a\"),\n>> +\tCLK(RCC_APB4ENR, 21, \"sai4b\"),\n>> +\tCLK(RCC_APB4ENR, 12, \"lptim5\"),\n>> +\tCLK(RCC_APB4ENR, 11, \"lptim4\"),\n>> +\tCLK(RCC_APB4ENR, 10, \"lptim3\"),\n>> +\tCLK(RCC_APB4ENR, 9, \"lptim2\"),\n>> +\tCLK(RCC_APB4ENR, 7, \"i2c4\"),\n>> +\tCLK(RCC_APB4ENR, 5, \"spi6\"),\n>> +\tCLK(RCC_APB4ENR, 3, \"lpuart1\"),\n>> +};\n>> +\n>> +struct stm32_clk {\n>> +\tstruct stm32_rcc_regs *rcc_base;\n>> +\tstruct regmap *pwr_regmap;\n>> +};\n>> +\n>> +struct pll_psc {\n>> +\tu8\tdivm;\n>> +\tu16\tdivn;\n>> +\tu8\tdivp;\n>> +\tu8\tdivq;\n>> +\tu8\tdivr;\n>> +};\n>> +\n>> +/*\n>> + * OSC_HSE = 25 MHz\n>> + * VCO = 500MHz\n>> + * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz\n>> + */\n>> +struct pll_psc sys_pll_psc = {\n>> +\t.divm = 4,\n>> +\t.divn = 80,\n>> +\t.divp = 2,\n>> +\t.divq = 2,\n>> +\t.divr = 2,\n>> +};\n>> +\n>> +int configure_clocks(struct udevice *dev)\n>> +{\n>> +\tstruct stm32_clk *priv = dev_get_priv(dev);\n>> +\tstruct stm32_rcc_regs *regs = priv->rcc_base;\n>> +\tuint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);\n>> +\tuint32_t pllckselr = 0;\n>> +\tuint32_t pll1divr = 0;\n>> +\tuint32_t pllcfgr = 0;\n>> +\n>> +\t/* Switch on HSI */\n>> +\tsetbits_le32(®s->cr, RCC_CR_HSION);\n>> +\twhile (!(readl(®s->cr) & RCC_CR_HSIRDY))\n>> +\t\t;\n>> +\n>> +\t/* Reset CFGR, now HSI is the default system clock */\n>> +\twritel(0, ®s->cfgr);\n>> +\n>> +\t/* Set all kernel domain clock registers to reset value*/\n>> +\twritel(0x0, ®s->d1ccipr);\n>> +\twritel(0x0, ®s->d2ccip1r);\n>> +\twritel(0x0, ®s->d2ccip2r);\n>> +\n>> +\t/* Set voltage scaling at scale 1 */\n> \n> pls add info what is scale1\n\nok\n\n> \n>> +\tclrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,\n>> +\t\t\tVOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);\n>> +\t/* disable step down converter */\n> \n> is this comment correct ?\n\nYes, in ref manual, SDEN bit description is for \"Step down converter\"\n> \n>> +\tclrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SDEN);\n>> +\twhile (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))\n>> +\t\t;\n>> +\n>> +\t/* disable HSE to configure it */\n>> +\tclrbits_le32(®s->cr, RCC_CR_HSEON);\n>> +\twhile ((readl(®s->cr) & RCC_CR_HSERDY))\n>> +\t\t;\n>> +\n>> +\t/* clear HSE bypass and set it ON */\n>> +\tclrbits_le32(®s->cr, RCC_CR_HSEBYP);\n>> +\t/* Switch on HSE */\n>> +\tsetbits_le32(®s->cr, RCC_CR_HSEON);\n>> +\twhile (!(readl(®s->cr) & RCC_CR_HSERDY))\n>> +\t\t;\n>> +\n>> +\t/* pll setup, disable it */\n>> +\tclrbits_le32(®s->cr, RCC_CR_PLL1ON);\n>> +\twhile ((readl(®s->cr) & RCC_CR_PLL1RDY))\n>> +\t\t;\n>> +\n>> +\t/* Select HSE as PLL clock source */\n>> +\tpllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;\n>> +\tpllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;\n>> +\twritel(pllckselr, ®s->pllckselr);\n>> +\n>> +\tpll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;\n>> +\tpll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;\n>> +\tpll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;\n>> +\tpll1divr |= (sys_pll_psc.divn - 1);\n>> +\twritel(pll1divr, ®s->pll1divr);\n>> +\n>> +\tpllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;\n>> +\tpllcfgr |= RCC_PLLCFGR_DIVP1EN;\n>> +\tpllcfgr |= RCC_PLLCFGR_DIVQ1EN;\n>> +\tpllcfgr |= RCC_PLLCFGR_DIVR1EN;\n>> +\twritel(pllcfgr, ®s->pllcfgr);\n>> +\n>> +\t/* pll setup, enable it */\n>> +\tsetbits_le32(®s->cr, RCC_CR_PLL1ON);\n>> +\n>> +\t/* set HPRE (/2) DI clk --> 125MHz */\n>> +\tclrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK,\n>> +\t\t\tRCC_D1CFGR_HPRE_DIV2);\n>> +\n>> +\t/* select PLL1 as system clock source (sys_ck)*/\n>> +\tclrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);\n>> +\twhile ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)\n>> +\t\t;\n>> +\n>> +\t/* sdram: use pll1_q as fmc_k clk */\n>> +\tclrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,\n>> +\t\t\tFMCSRC_PLL1_Q_CK);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)\n>> +{\n>> +\tu32 divider;\n>> +\n>> +\t/* get HSI divider value */\n>> +\tdivider = readl(®s->cr) & RCC_CR_HSIDIV_MASK;\n>> +\tdivider = divider >> RCC_CR_HSIDIV_SHIFT;\n>> +\n>> +\treturn divider;\n>> +};\n>> +\n>> +enum pllsrc {\n>> +\tHSE,\n>> +\tLSE,\n>> +\tHSI,\n>> +\tCSI,\n>> +\tI2S,\n>> +\tTIMER,\n>> +\tPLLSRC_NB,\n>> +};\n>> +\n>> +static const char * const pllsrc_name[PLLSRC_NB] = {\n>> +\t[HSE] = \"clk-hse\",\n>> +\t[LSE] = \"clk-lse\",\n>> +\t[HSI] = \"clk-hsi\",\n>> +\t[CSI] = \"clk-csi\",\n>> +\t[I2S] = \"clk-i2s\",\n>> +\t[TIMER] = \"timer-clk\"\n>> +};\n>> +\n>> +static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)\n>> +{\n>> +\tstruct clk clk;\n>> +\tstruct udevice *fixed_clock_dev = NULL;\n>> +\tu32 divider;\n>> +\tint ret;\n>> +\tconst char *name = pllsrc_name[pllsrc];\n>> +\n>> +\tdebug(\"%s name %s\\n\", __func__, name);\n>> +\n>> +\tclk.id = 0;\n>> +\tret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);\n>> +\tif (ret) {\n>> +\t\terror(\"Can't find clk %s (%d)\", name, ret);\n>> +\t\treturn 0;\n>> +\t}\n>> +\n>> +\tret = clk_request(fixed_clock_dev, &clk);\n>> +\tif (ret) {\n>> +\t\terror(\"Can't request %s clk (%d)\", name, ret);\n>> +\t\treturn 0;\n>> +\t}\n>> +\n>> +\tdivider = 0;\n>> +\tif (pllsrc == HSI)\n>> +\t\tdivider = stm32_get_HSI_divider(regs);\n>> +\n>> +\tdebug(\"%s divider %d rate %ld\\n\", __func__,\n>> +\t divider, clk_get_rate(&clk));\n>> +\n>> +\treturn clk_get_rate(&clk) >> divider;\n>> +};\n>> +\n>> +enum pll1_output {\n>> +\tPLL1_P_CK,\n>> +\tPLL1_Q_CK,\n>> +\tPLL1_R_CK,\n>> +};\n>> +\n>> +static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,\n>> +\t\t\t enum pll1_output output)\n>> +{\n>> +\tulong pllsrc = 0;\n>> +\tu32 divm1, divn1, divp1, divq1, divr1, fracn1;\n>> +\tulong vco, rate;\n>> +\n>> +\t/* get the PLLSRC */\n>> +\tswitch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {\n>> +\tcase RCC_PLLCKSELR_PLLSRC_HSI:\n>> +\t\tpllsrc = stm32_get_rate(regs, HSI);\n>> +\t\tbreak;\n>> +\tcase RCC_PLLCKSELR_PLLSRC_CSI:\n>> +\t\tpllsrc = stm32_get_rate(regs, CSI);\n>> +\t\tbreak;\n>> +\tcase RCC_PLLCKSELR_PLLSRC_HSE:\n>> +\t\tpllsrc = stm32_get_rate(regs, HSE);\n>> +\t\tbreak;\n>> +\tcase RCC_PLLCKSELR_PLLSRC_NO_CLK:\n>> +\t\t/* shouldn't happen */\n>> +\t\terror(\"wrong value for RCC_PLLCKSELR register\\n\");\n>> +\t\tpllsrc = 0;\n>> +\t\tbreak;\n>> +\t}\n>> +\n>> +\t/* pllsrc = 0 ? no need to go ahead */\n>> +\tif (!pllsrc)\n>> +\t\treturn pllsrc;\n>> +\n>> +\t/* get divm1, divp1, divn1 and divr1 */\n>> +\tdivm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;\n>> +\tdivm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;\n>> +\n>> +\tdivn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;\n>> +\n>> +\tdivp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;\n>> +\tdivp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;\n>> +\n>> +\tdivq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;\n>> +\tdivq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;\n>> +\n>> +\tdivr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;\n>> +\tdivr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;\n>> +\n>> +\tfracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;\n>> +\tfracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;\n>> +\n>> +\tvco = (pllsrc / divm1) * divn1;\n>> +\trate = (pllsrc * fracn1) / (divm1 * 8192);\n>> +\n>> +\tdebug(\"%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\\n\",\n>> +\t __func__, divm1, divn1, divp1, divq1, divr1);\n>> +\tdebug(\"%s fracn1 = %d vco = %ld rate = %ld\\n\",\n>> +\t __func__, fracn1, vco, rate);\n>> +\n>> +\tswitch (output) {\n>> +\tcase PLL1_P_CK:\n>> +\t\treturn (vco + rate) / divp1;\n>> +\t\tbreak;\n>> +\tcase PLL1_Q_CK:\n>> +\t\treturn (vco + rate) / divq1;\n>> +\t\tbreak;\n>> +\n>> +\tcase PLL1_R_CK:\n>> +\t\treturn (vco + rate) / divr1;\n>> +\t\tbreak;\n>> +\t}\n>> +\n>> +\treturn -EINVAL;\n>> +}\n>> +\n>> +static ulong stm32_clk_get_rate(struct clk *clk)\n>> +{\n>> +\tstruct stm32_clk *priv = dev_get_priv(clk->dev);\n>> +\tstruct stm32_rcc_regs *regs = priv->rcc_base;\n>> +\tulong sysclk = 0;\n>> +\tu32 gate_offset;\n>> +\tu32 d1cfgr;\n>> +\t/* prescaler table lookups for clock computation */\n>> +\tu16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};\n>> +\tu8 source, idx;\n>> +\n>> +\t/*\n>> +\t * get system clock (sys_ck) source\n>> +\t * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck\n>> +\t */\n>> +\tsource = readl(®s->cfgr) & RCC_CFGR_SW_MASK;\n>> +\tswitch (source) {\n>> +\tcase RCC_CFGR_SW_PLL1:\n>> +\t\tsysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);\n>> +\t\tbreak;\n>> +\tcase RCC_CFGR_SW_HSE:\n>> +\t\tsysclk = stm32_get_rate(regs, HSE);\n>> +\t\tbreak;\n>> +\n>> +\tcase RCC_CFGR_SW_CSI:\n>> +\t\tsysclk = stm32_get_rate(regs, CSI);\n>> +\t\tbreak;\n>> +\n>> +\tcase RCC_CFGR_SW_HSI:\n>> +\t\tsysclk = stm32_get_rate(regs, HSI);\n>> +\t\tbreak;\n>> +\t}\n>> +\n>> +\t/* sysclk = 0 ? no need to go ahead */\n>> +\tif (!sysclk)\n>> +\t\treturn sysclk;\n>> +\n>> +\tdebug(\"%s system clock: source = %d freq = %ld\\n\",\n>> +\t __func__, source, sysclk);\n>> +\n>> +\td1cfgr = readl(®s->d1cfgr);\n>> +\n>> +\tif (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {\n>> +\t\t/* get D1 domain Core prescaler */\n>> +\t\tidx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>\n>> +\t\t RCC_D1CFGR_D1CPRE_SHIFT;\n>> +\t\tsysclk = sysclk / prescaler_table[idx];\n>> +\t}\n>> +\n>> +\tif (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {\n>> +\t\t/* get D1 domain AHB prescaler */\n>> +\t\tidx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;\n>> +\t\tsysclk = sysclk / prescaler_table[idx];\n>> +\t}\n>> +\n>> +\tgate_offset = clk_map[clk->id].gate_offset;\n>> +\n>> +\tdebug(\"%s clk->id=%ld gate_offset=0x%x sysclk=%ld\\n\",\n>> +\t __func__, clk->id, gate_offset, sysclk);\n>> +\n>> +\tswitch (gate_offset) {\n>> +\tcase RCC_AHB3ENR:\n>> +\tcase RCC_AHB1ENR:\n>> +\tcase RCC_AHB2ENR:\n>> +\tcase RCC_AHB4ENR:\n>> +\t\treturn sysclk;\n>> +\t\tbreak;\n>> +\n>> +\tcase RCC_APB3ENR:\n>> +\t\tif (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {\n>> +\t\t\t/* get D1 domain APB3 prescaler */\n>> +\t\t\tidx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>\n>> +\t\t\t RCC_D1CFGR_D1PPRE_SHIFT;\n>> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n>> +\t\t}\n>> +\n>> +\t\tdebug(\"%s system clock: freq after APB3 prescaler = %ld\\n\",\n>> +\t\t __func__, sysclk);\n>> +\n>> +\t\treturn sysclk;\n>> +\t\tbreak;\n>> +\n>> +\tcase RCC_APB4ENR:\n>> +\t\tif (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {\n>> +\t\t\t/* get D3 domain APB4 prescaler */\n>> +\t\t\tidx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>\n>> +\t\t\t RCC_D3CFGR_D3PPRE_SHIFT;\n>> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n>> +\t\t}\n>> +\n>> +\t\tdebug(\"%s system clock: freq after APB4 prescaler = %ld\\n\",\n>> +\t\t __func__, sysclk);\n>> +\n>> +\t\treturn sysclk;\n>> +\t\tbreak;\n>> +\n>> +\tcase RCC_APB1LENR:\n>> +\tcase RCC_APB1HENR:\n>> +\t\tif (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) {\n>> +\t\t\t/* get D2 domain APB1 prescaler */\n>> +\t\t\tidx = (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) >>\n>> +\t\t\t RCC_D2CFGR_D2PPRE1_SHIFT;\n>> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n>> +\t\t}\n>> +\n>> +\t\tdebug(\"%s system clock: freq after APB1 prescaler = %ld\\n\",\n>> +\t\t __func__, sysclk);\n>> +\n>> +\t\treturn sysclk;\n>> +\t\tbreak;\n>> +\n>> +\tcase RCC_APB2ENR:\n>> +\t\tif (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) {\n>> +\t\t\t/* get D2 domain APB1 prescaler */\n>> +\t\t\tidx = (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) >>\n>> +\t\t\t RCC_D2CFGR_D2PPRE2_SHIFT;\n>> +\t\t\tsysclk = sysclk / prescaler_table[idx];\n>> +\t\t}\n>> +\n>> +\t\tdebug(\"%s system clock: freq after APB2 prescaler = %ld\\n\",\n>> +\t\t __func__, sysclk);\n>> +\n>> +\t\treturn sysclk;\n>> +\t\tbreak;\n>> +\n>> +\tdefault:\n>> +\t\terror(\"unexpected gate_offset value (0x%x)\\n\", gate_offset);\n>> +\t\treturn -EINVAL;\n>> +\t\tbreak;\n>> +\t}\n>> +}\n>> +\n>> +static int stm32_clk_enable(struct clk *clk)\n>> +{\n>> +\tstruct stm32_clk *priv = dev_get_priv(clk->dev);\n>> +\tstruct stm32_rcc_regs *regs = priv->rcc_base;\n>> +\tu32 gate_offset;\n>> +\tu32 gate_bit_index;\n>> +\tunsigned long clk_id = clk->id;\n>> +\n>> +\tgate_offset = clk_map[clk_id].gate_offset;\n>> +\tgate_bit_index = clk_map[clk_id].gate_bit_idx;\n>> +\n>> +\tdebug(\"%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\\n\",\n>> +\t __func__, clk->id, gate_offset, gate_bit_index,\n>> +\t clk_map[clk_id].name);\n>> +\n>> +\tsetbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index));\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int stm32_clk_probe(struct udevice *dev)\n>> +{\n>> +\tstruct stm32_clk *priv = dev_get_priv(dev);\n>> +\tstruct udevice *syscon;\n>> +\tfdt_addr_t addr;\n>> +\tint err;\n>> +\n>> +\taddr = dev_read_addr(dev);\n>> +\tif (addr == FDT_ADDR_T_NONE)\n>> +\t\treturn -EINVAL;\n>> +\n>> +\tpriv->rcc_base = (struct stm32_rcc_regs *)addr;\n>> +\n>> +\t/* get corresponding syscon phandle */\n>> +\terr = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,\n>> +\t\t\t\t\t \"st,syscfg\", &syscon);\n>> +\n>> +\tif (err) {\n>> +\t\terror(\"unable to find syscon device\\n\");\n>> +\t\treturn err;\n>> +\t}\n>> +\n>> +\tpriv->pwr_regmap = syscon_get_regmap(syscon);\n> \n> why SYSCON_UCLASS...It is used just to get the base address of power control block ?\n> It can be done directly from the phandle also, e.g. fdt_node_offset_by_phandle() or similar.\n\nAgree, i will fix this too\n\n\nThanks\n\nPatrice\n\n> \n> \n> Cheers,\n> Vikas\n> \n>> +\tif (!priv->pwr_regmap) {\n>> +\t\terror(\"unable to find regmap\\n\");\n>> +\t\treturn -ENODEV;\n>> +\t}\n>> +\n>> +\tconfigure_clocks(dev);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int stm32_clk_of_xlate(struct clk *clk,\n>> +\t\t\tstruct ofnode_phandle_args *args)\n>> +{\n>> +\tif (args->args_count != 1) {\n>> +\t\tdebug(\"Invaild args_count: %d\\n\", args->args_count);\n>> +\t\treturn -EINVAL;\n>> +\t}\n>> +\n>> +\tif (args->args_count) {\n>> +\t\tclk->id = args->args[0];\n>> +\t\t/*\n>> +\t\t * this computation convert DT clock index which is used to\n>> +\t\t * point into 2 separate clock arrays (peripheral and kernel\n>> +\t\t * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)\n>> +\t\t * into index to point into only one array where peripheral\n>> +\t\t * and kernel clocks are consecutive\n>> +\t\t */\n>> +\t\tif (clk->id >= KERN_BANK) {\n>> +\t\t\tclk->id -= KERN_BANK;\n>> +\t\t\tclk->id += LAST_PERIF_BANK - PERIF_BANK + 1;\n>> +\t\t} else {\n>> +\t\t\tclk->id -= PERIF_BANK;\n>> +\t\t}\n>> +\t} else {\n>> +\t\tclk->id = 0;\n>> +\t}\n>> +\n>> +\tdebug(\"%s clk->id %ld\\n\", __func__, clk->id);\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static struct clk_ops stm32_clk_ops = {\n>> +\t.of_xlate\t= stm32_clk_of_xlate,\n>> +\t.enable\t\t= stm32_clk_enable,\n>> +\t.get_rate\t= stm32_clk_get_rate,\n>> +};\n>> +\n>> +U_BOOT_DRIVER(stm32h7_clk) = {\n>> +\t.name\t\t\t= \"stm32h7_rcc_clock\",\n>> +\t.id\t\t\t= UCLASS_CLK,\n>> +\t.ops\t\t\t= &stm32_clk_ops,\n>> +\t.probe\t\t\t= stm32_clk_probe,\n>> +\t.priv_auto_alloc_size\t= sizeof(struct stm32_clk),\n>> +\t.flags\t\t\t= DM_FLAG_PRE_RELOC,\n>> +};\n>> diff --git a/include/dt-bindings/clock/stm32h7-clks.h b/include/dt-bindings/clock/stm32h7-clks.h\n>> new file mode 100644\n>> index 0000000..4d87e7e\n>> --- /dev/null\n>> +++ b/include/dt-bindings/clock/stm32h7-clks.h\n>> @@ -0,0 +1,167 @@\n>> +/* SYS, CORE AND BUS CLOCKS */\n>> +#define SYS_D1CPRE 0\n>> +#define HCLK 1\n>> +#define PCLK1 2\n>> +#define PCLK2 3\n>> +#define PCLK3 4\n>> +#define PCLK4 5\n>> +#define HSI_DIV 6\n>> +#define HSE_1M 7\n>> +#define I2S_CKIN 8\n>> +#define CK_DSI_PHY 9\n>> +#define HSE_CK 10\n>> +#define LSE_CK 11\n>> +#define CSI_KER_DIV122 12\n>> +#define RTC_CK 13\n>> +#define CPU_SYSTICK 14\n>> +\n>> +/* OSCILLATOR BANK */\n>> +#define OSC_BANK 18\n>> +#define HSI_CK 18\n>> +#define HSI_KER_CK 19\n>> +#define CSI_CK 20\n>> +#define CSI_KER_CK 21\n>> +#define RC48_CK 22\n>> +#define LSI_CK 23\n>> +\n>> +/* MCLOCK BANK */\n>> +#define MCLK_BANK 28\n>> +#define PER_CK 28\n>> +#define PLLSRC 29\n>> +#define SYS_CK 30\n>> +#define TRACEIN_CK 31\n>> +\n>> +/* ODF BANK */\n>> +#define ODF_BANK 32\n>> +#define PLL1_P 32\n>> +#define PLL1_Q 33\n>> +#define PLL1_R 34\n>> +#define PLL2_P 35\n>> +#define PLL2_Q 36\n>> +#define PLL2_R 37\n>> +#define PLL3_P 38\n>> +#define PLL3_Q 39\n>> +#define PLL3_R 40\n>> +\n>> +/* MCO BANK */\n>> +#define MCO_BANK 41\n>> +#define MCO1 41\n>> +#define MCO2 42\n>> +\n>> +/* PERIF BANK */\n>> +#define PERIF_BANK 50\n>> +#define D1SRAM1_CK 50\n>> +#define ITCM_CK 51\n>> +#define DTCM2_CK 52\n>> +#define DTCM1_CK 53\n>> +#define FLITF_CK 54\n>> +#define JPGDEC_CK 55\n>> +#define DMA2D_CK 56\n>> +#define MDMA_CK 57\n>> +#define USB2ULPI_CK 58\n>> +#define USB1ULPI_CK 59\n>> +#define ETH1RX_CK 60\n>> +#define ETH1TX_CK 61\n>> +#define ETH1MAC_CK 62\n>> +#define ART_CK 63\n>> +#define DMA2_CK 64\n>> +#define DMA1_CK 65\n>> +#define D2SRAM3_CK 66\n>> +#define D2SRAM2_CK 67\n>> +#define D2SRAM1_CK 68\n>> +#define HASH_CK 69\n>> +#define CRYPT_CK 70\n>> +#define CAMITF_CK 71\n>> +#define BKPRAM_CK 72\n>> +#define HSEM_CK 73\n>> +#define BDMA_CK 74\n>> +#define CRC_CK 75\n>> +#define GPIOK_CK 76\n>> +#define GPIOJ_CK 77\n>> +#define GPIOI_CK 78\n>> +#define GPIOH_CK 79\n>> +#define GPIOG_CK 80\n>> +#define GPIOF_CK 81\n>> +#define GPIOE_CK 82\n>> +#define GPIOD_CK 83\n>> +#define GPIOC_CK 84\n>> +#define GPIOB_CK 85\n>> +#define GPIOA_CK 86\n>> +#define WWDG1_CK 87\n>> +#define DAC12_CK 88\n>> +#define WWDG2_CK 89\n>> +#define TIM14_CK 90\n>> +#define TIM13_CK 91\n>> +#define TIM12_CK 92\n>> +#define TIM7_CK 93\n>> +#define TIM6_CK 94\n>> +#define TIM5_CK 95\n>> +#define TIM4_CK 96\n>> +#define TIM3_CK 97\n>> +#define TIM2_CK 98\n>> +#define MDIOS_CK 99\n>> +#define OPAMP_CK 100\n>> +#define CRS_CK 101\n>> +#define TIM17_CK 102\n>> +#define TIM16_CK 103\n>> +#define TIM15_CK 104\n>> +#define TIM8_CK 105\n>> +#define TIM1_CK 106\n>> +#define TMPSENS_CK 107\n>> +#define RTCAPB_CK 108\n>> +#define VREF_CK 109\n>> +#define COMP12_CK 110\n>> +#define SYSCFG_CK 111\n>> +/* must be equal to last peripheral clock index */\n>> +#define LAST_PERIF_BANK SYSCFG_CK\n>> +\n>> +/* KERNEL BANK */\n>> +#define KERN_BANK 120\n>> +#define SDMMC1_CK 120\n>> +#define QUADSPI_CK 121\n>> +#define FMC_CK 122\n>> +#define USB2OTG_CK 123\n>> +#define USB1OTG_CK 124\n>> +#define ADC12_CK 125\n>> +#define SDMMC2_CK 126\n>> +#define RNG_CK 127\n>> +#define ADC3_CK 128\n>> +#define DSI_CK 129\n>> +#define LTDC_CK 130\n>> +#define USART8_CK 131\n>> +#define USART7_CK 132\n>> +#define HDMICEC_CK 133\n>> +#define I2C3_CK 134\n>> +#define I2C2_CK 135\n>> +#define I2C1_CK 136\n>> +#define UART5_CK 137\n>> +#define UART4_CK 138\n>> +#define USART3_CK 139\n>> +#define USART2_CK 140\n>> +#define SPDIFRX_CK 141\n>> +#define SPI3_CK 142\n>> +#define SPI2_CK 143\n>> +#define LPTIM1_CK 144\n>> +#define FDCAN_CK 145\n>> +#define SWP_CK 146\n>> +#define HRTIM_CK 147\n>> +#define DFSDM1_CK 148\n>> +#define SAI3_CK 149\n>> +#define SAI2_CK 150\n>> +#define SAI1_CK 151\n>> +#define SPI5_CK 152\n>> +#define SPI4_CK 153\n>> +#define SPI1_CK 154\n>> +#define USART6_CK 155\n>> +#define USART1_CK 156\n>> +#define SAI4B_CK 157\n>> +#define SAI4A_CK 158\n>> +#define LPTIM5_CK 159\n>> +#define LPTIM4_CK 160\n>> +#define LPTIM3_CK 161\n>> +#define LPTIM2_CK 162\n>> +#define I2C4_CK 163\n>> +#define SPI6_CK 164\n>> +#define LPUART1_CK 165\n>> +\n>> +#define STM32H7_MAX_CLKS 166\n>>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0x9b6xDvz9tXM\n\tfor ;\n\tMon, 25 Sep 2017 17:51:31 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid ABF94C22052; Mon, 25 Sep 2017 07:51:30 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id CAB7EC21C50;\n\tMon, 25 Sep 2017 07:51:18 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D7162C21C50; Mon, 25 Sep 2017 07:51:17 +0000 (UTC)","from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com\n\t[62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 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([fe80::d04:5337:ab17:b6f6]) by\n\tSFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6%20]) with mapi id\n\t15.00.1178.000; Mon, 25 Sep 2017 09:51:12 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Patrice CHOTARD ","To":"Vikas MANOCHA , \"u-boot@lists.denx.de\"\n\t, \"albert.u.boot@aribaud.net\"\n\t, \"sjg@chromium.org\" ","Thread-Topic":"[PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs","Thread-Index":"AQHTLKll1/eQ/h7DZUeJPa3oAw6itKK856sAgAhDloA=","Date":"Mon, 25 Sep 2017 07:51:12 +0000","Message-ID":"","References":"<1505318412-27121-1-git-send-email-patrice.chotard@st.com>\n\t<1505318412-27121-4-git-send-email-patrice.chotard@st.com>\n\t","In-Reply-To":"","Accept-Language":"fr-FR, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","user-agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","x-ms-exchange-messagesentrepresentingtype":"1","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.75.127.48]","Content-ID":"","MIME-Version":"1.0","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-25_03:, , signatures=0","Subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775276,"web_url":"http://patchwork.ozlabs.org/comment/1775276/","msgid":"<30892c26-32a0-1934-b9ab-058b46e07143@st.com>","list_archive_url":null,"date":"2017-09-26T08:51:15","subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","submitter":{"id":63958,"url":"http://patchwork.ozlabs.org/api/people/63958/","name":"Patrice CHOTARD","email":"patrice.chotard@st.com"},"content":"Hi Vikas\n\nOn 09/25/2017 09:51 AM, Patrice CHOTARD wrote:\n> Hi Vikas\n> \n> On 09/20/2017 03:39 AM, Vikas Manocha wrote:\n>> Hi Patrice,\n>>\n>> On 09/13/2017 09:00 AM, patrice.chotard@st.com wrote:\n>>> From: Patrice Chotard \n>>>\n>>> This driver implements basic clock setup, only clock gating\n>>> is implemented.\n>>>\n>>> This driver doesn't implement .of_match as it's binded\n>>> by MFD RCC driver.\n>>>\n>>> Files include/dt-bindings/clock/stm32h7-clks.h and\n>>> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n>>> will be available soon in a kernel tag, as all the\n>>> bindings have been acked by Rob Herring [1].\n>>>\n>>> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n>>>\n>>> Signed-off-by: Patrice Chotard \n>>> ---\n\n[...]\n\n>>> +\n>>> +#define PWR_CR3                0x0c\n>>> +#define PWR_CR3_SDEN            BIT(2)\n>>\n>> Can we use SCUEN suffix to match the Ref Manual.\n> \n> Which version of reference manual do you use ? in mine its SDEN, but i \n> propably use a too old ref manual.\n> \n\nI have found the last version of STM32H7 ref manual, mine was too old,\nok i will update the PWR_CR3_SDEN to PWR_CR3_SCUEN\n\nthanks\n\nPatrice\n\n>>\n>>> +#define PWR_D3CR            0x18\n>>> +#define PWR_D3CR_VOS_MASK        GENMASK(15, 14)\n>>> +#define PWR_D3CR_VOS_SHIFT        14\n>>> +#define        VOS_SCALE_3        1\n>>> +#define        VOS_SCALE_2        2\n>>> +#define        VOS_SCALE_1        3\n>>> +#define PWR_D3CR_VOSREADY        BIT(13)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1ZST3Xgbz9t3B\n\tfor ;\n\tTue, 26 Sep 2017 18:51:36 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid F21ACC21E97; Tue, 26 Sep 2017 08:51:25 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id AF617C21CA5;\n\tTue, 26 Sep 2017 08:51:22 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 74F7AC21CA5; Tue, 26 Sep 2017 08:51:21 +0000 (UTC)","from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 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([fe80::d04:5337:ab17:b6f6]) by\n\tSFHDAG6NODE3.st.com ([fe80::d04:5337:ab17:b6f6%20]) with mapi id\n\t15.00.1178.000; Tue, 26 Sep 2017 10:51:15 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Patrice CHOTARD ","To":"Vikas MANOCHA , \"u-boot@lists.denx.de\"\n\t, \"albert.u.boot@aribaud.net\"\n\t, \"sjg@chromium.org\" ","Thread-Topic":"[PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs","Thread-Index":"AQHTLKll1/eQ/h7DZUeJPa3oAw6itKK856sAgAhDloCAAaMdgA==","Date":"Tue, 26 Sep 2017 08:51:15 +0000","Message-ID":"<30892c26-32a0-1934-b9ab-058b46e07143@st.com>","References":"<1505318412-27121-1-git-send-email-patrice.chotard@st.com>\n\t<1505318412-27121-4-git-send-email-patrice.chotard@st.com>\n\t\n\t","In-Reply-To":"","Accept-Language":"fr-FR, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","user-agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","x-ms-exchange-messagesentrepresentingtype":"1","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.75.127.46]","Content-ID":"","MIME-Version":"1.0","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-26_02:, , signatures=0","Subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775425,"web_url":"http://patchwork.ozlabs.org/comment/1775425/","msgid":"<904b9f52-7abe-2257-5686-f185f5bbc06d@st.com>","list_archive_url":null,"date":"2017-09-26T12:26:56","subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","submitter":{"id":63958,"url":"http://patchwork.ozlabs.org/api/people/63958/","name":"Patrice CHOTARD","email":"patrice.chotard@st.com"},"content":"Hi Vikas\n\nOn 09/26/2017 10:51 AM, Patrice CHOTARD wrote:\n> Hi Vikas\n> \n> On 09/25/2017 09:51 AM, Patrice CHOTARD wrote:\n>> Hi Vikas\n>>\n>> On 09/20/2017 03:39 AM, Vikas Manocha wrote:\n>>> Hi Patrice,\n>>>\n>>> On 09/13/2017 09:00 AM, patrice.chotard@st.com wrote:\n>>>> From: Patrice Chotard \n>>>>\n>>>> This driver implements basic clock setup, only clock gating\n>>>> is implemented.\n>>>>\n>>>> This driver doesn't implement .of_match as it's binded\n>>>> by MFD RCC driver.\n>>>>\n>>>> Files include/dt-bindings/clock/stm32h7-clks.h and\n>>>> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n>>>> will be available soon in a kernel tag, as all the\n>>>> bindings have been acked by Rob Herring [1].\n>>>>\n>>>> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n>>>>\n>>>> Signed-off-by: Patrice Chotard \n>>>> ---\n> \n> [...]\n> \n>>>> +\n>>>> +#define PWR_CR3                0x0c\n>>>> +#define PWR_CR3_SDEN            BIT(2)\n>>>\n>>> Can we use SCUEN suffix to match the Ref Manual.\n>>\n>> Which version of reference manual do you use ? in mine its SDEN, but i \n>> propably use a too old ref manual.\n>>\n> \n> I have found the last version of STM32H7 ref manual, mine was too old,\n> ok i will update the PWR_CR3_SDEN to PWR_CR3_SCUEN\n\nAfter double check, in the STM32H7x3 reference manual available on \nst.com (DocID029587 Rev 2), bit 2 of PWR_CR3 reg is described as following:\n\n\"Bit 2 SCUEN: Supply configuration update enable\nThis bit is read-only:\n0: Supply configuration update locked.\n1: Single write enabled to Supply configuration (LDOEN and BYPASS)\"\n\nWhereas in the one i used, bit 2 of PWR_CR3 is described as:\n\n\"Bit 2 SDEN (1)(2) : SD converter Enable\n0: Step down converter disabled\n1: Step down converter enabled. (Default)\"\n\nIf i follow ref manual DocID029587 Rev 2, this bit is read-only, so the \nwrite access of PWR_CR3 bit(2) in clk_stm32h7.c is useless. But after \nwrite access removal, the both STM32H7 disco and eval board doesn't boot.\n\nThe reference manual is wrong regarding with at least this bit. I will\ncontact PWR architect to solve this point.\n\nPatrice\n\n\n> \n> thanks\n> \n> Patrice\n> \n>>>\n>>>> +#define PWR_D3CR            0x18\n>>>> +#define PWR_D3CR_VOS_MASK        GENMASK(15, 14)\n>>>> +#define PWR_D3CR_VOS_SHIFT        14\n>>>> +#define        VOS_SCALE_3        1\n>>>> +#define        VOS_SCALE_2        2\n>>>> +#define        VOS_SCALE_1        3\n>>>> +#define PWR_D3CR_VOSREADY        BIT(13)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1gFj5FSDz9s76\n\tfor ;\n\tTue, 26 Sep 2017 22:27:37 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 7641DC21F1F; Tue, 26 Sep 2017 12:27:04 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 18792C21E84;\n\tTue, 26 Sep 2017 12:27:02 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 725C2C21E32; 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Tue, 26 Sep 2017 14:26:56 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Patrice CHOTARD ","To":"Vikas MANOCHA , \"u-boot@lists.denx.de\"\n\t, \"albert.u.boot@aribaud.net\"\n\t, \"sjg@chromium.org\" ","Thread-Topic":"[PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs","Thread-Index":"AQHTLKll1/eQ/h7DZUeJPa3oAw6itKK856sAgAhDloCAAaMdgIAAPEKA","Date":"Tue, 26 Sep 2017 12:26:56 +0000","Message-ID":"<904b9f52-7abe-2257-5686-f185f5bbc06d@st.com>","References":"<1505318412-27121-1-git-send-email-patrice.chotard@st.com>\n\t<1505318412-27121-4-git-send-email-patrice.chotard@st.com>\n\t\n\t\n\t<30892c26-32a0-1934-b9ab-058b46e07143@st.com>","In-Reply-To":"<30892c26-32a0-1934-b9ab-058b46e07143@st.com>","Accept-Language":"fr-FR, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","user-agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","x-ms-exchange-messagesentrepresentingtype":"1","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.75.127.51]","Content-ID":"<9BA0F60A4E1D1246AB72B6F15F7DA41F@st.com>","MIME-Version":"1.0","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-26_05:, , signatures=0","Subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775704,"web_url":"http://patchwork.ozlabs.org/comment/1775704/","msgid":"","list_archive_url":null,"date":"2017-09-26T17:10:26","subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","submitter":{"id":64678,"url":"http://patchwork.ozlabs.org/api/people/64678/","name":"Vikas MANOCHA","email":"vikas.manocha@st.com"},"content":"Thanks Patrice,\n\n> -----Original Message-----\n> From: Patrice CHOTARD\n> Sent: Tuesday, September 26, 2017 5:27 AM\n> To: Vikas MANOCHA ; u-boot@lists.denx.de; albert.u.boot@aribaud.net; sjg@chromium.org\n> Cc: Patrick DELAUNAY ; Christophe KERELLO \n> Subject: Re: [PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs\n> \n> Hi Vikas\n> \n> On 09/26/2017 10:51 AM, Patrice CHOTARD wrote:\n> > Hi Vikas\n> >\n> > On 09/25/2017 09:51 AM, Patrice CHOTARD wrote:\n> >> Hi Vikas\n> >>\n> >> On 09/20/2017 03:39 AM, Vikas Manocha wrote:\n> >>> Hi Patrice,\n> >>>\n> >>> On 09/13/2017 09:00 AM, patrice.chotard@st.com wrote:\n> >>>> From: Patrice Chotard \n> >>>>\n> >>>> This driver implements basic clock setup, only clock gating is\n> >>>> implemented.\n> >>>>\n> >>>> This driver doesn't implement .of_match as it's binded by MFD RCC\n> >>>> driver.\n> >>>>\n> >>>> Files include/dt-bindings/clock/stm32h7-clks.h and\n> >>>> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt\n> >>>> will be available soon in a kernel tag, as all the bindings have\n> >>>> been acked by Rob Herring [1].\n> >>>>\n> >>>> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html\n> >>>>\n> >>>> Signed-off-by: Patrice Chotard \n> >>>> ---\n> >\n> > [...]\n> >\n> >>>> +\n> >>>> +#define PWR_CR3                0x0c #define PWR_CR3_SDEN\n> >>>> +BIT(2)\n> >>>\n> >>> Can we use SCUEN suffix to match the Ref Manual.\n> >>\n> >> Which version of reference manual do you use ? in mine its SDEN, but\n> >> i propably use a too old ref manual.\n> >>\n> >\n> > I have found the last version of STM32H7 ref manual, mine was too old,\n> > ok i will update the PWR_CR3_SDEN to PWR_CR3_SCUEN\n> \n> After double check, in the STM32H7x3 reference manual available on st.com (DocID029587 Rev 2), bit 2 of PWR_CR3 reg is described as\n> following:\n> \n> \"Bit 2 SCUEN: Supply configuration update enable This bit is read-only:\n> 0: Supply configuration update locked.\n> 1: Single write enabled to Supply configuration (LDOEN and BYPASS)\"\n> \n> Whereas in the one i used, bit 2 of PWR_CR3 is described as:\n> \n> \"Bit 2 SDEN (1)(2) : SD converter Enable\n> 0: Step down converter disabled\n> 1: Step down converter enabled. (Default)\"\n> \n> If i follow ref manual DocID029587 Rev 2, this bit is read-only, so the write access of PWR_CR3 bit(2) in clk_stm32h7.c is useless. But\n> after write access removal, the both STM32H7 disco and eval board doesn't boot.\n> \n> The reference manual is wrong regarding with at least this bit. I will contact PWR architect to solve this point.\n\nOk, By the Rev3 of the Ref manual is also available online but does not matter for this bit. Even the explanation for this bit does not make sense if system does not boot without it.\n\nCheers,\nVikas\n\n> \n> Patrice\n> \n> \n> >\n> > thanks\n> >\n> > Patrice\n> >\n> >>>\n> >>>> +#define PWR_D3CR            0x18\n> >>>> +#define PWR_D3CR_VOS_MASK        GENMASK(15, 14) #define\n> >>>> +PWR_D3CR_VOS_SHIFT        14 #define        VOS_SCALE_3        1\n> >>>> +#define        VOS_SCALE_2        2 #define        VOS_SCALE_1\n> >>>> +3 #define PWR_D3CR_VOSREADY        BIT(13)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1nXM3gj3z9t3Z\n\tfor ;\n\tWed, 27 Sep 2017 03:10:42 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 35F97C21E08; Tue, 26 Sep 2017 17:10:38 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 69425C21DC4;\n\tTue, 26 Sep 2017 17:10:35 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 9DF46C21C54; Tue, 26 Sep 2017 17:10:34 +0000 (UTC)","from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com\n\t[91.207.212.93])\n\tby lists.denx.de (Postfix) with ESMTPS id 369F1C21C54\n\tfor ; Tue, 26 Sep 2017 17:10:34 +0000 (UTC)","from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8QH8t3I032221; Tue, 26 Sep 2017 19:10:28 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2d7tyag0xn-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tTue, 26 Sep 2017 19:10:28 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0FDBD31;\n\tTue, 26 Sep 2017 17:10:27 +0000 (GMT)","from Webmail-eu.st.com (sfhdag6node2.st.com [10.75.127.17])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A0BEA2C6E;\n\tTue, 26 Sep 2017 17:10:27 +0000 (GMT)","from SFHDAG7NODE3.st.com (10.75.127.21) by SFHDAG6NODE2.st.com\n\t(10.75.127.17) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tTue, 26 Sep 2017 19:10:27 +0200","from SFHDAG7NODE3.st.com ([fe80::e966:8e0e:e19f:969e]) by\n\tSFHDAG7NODE3.st.com ([fe80::e966:8e0e:e19f:969e%20]) with mapi id\n\t15.00.1178.000; Tue, 26 Sep 2017 19:10:26 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","From":"Vikas MANOCHA ","To":"Patrice CHOTARD , \"u-boot@lists.denx.de\"\n\t, \"albert.u.boot@aribaud.net\"\n\t, \"sjg@chromium.org\" ","Thread-Topic":"[PATCH v2 3/9] dm: clk: add clk driver support for stm32h7 SoCs","Thread-Index":"AQHTNdMPuItzad2fMkKRzDt+0nRidKLGvAuAgAA8QwCAAG9kEA==","Date":"Tue, 26 Sep 2017 17:10:26 +0000","Message-ID":"","References":"<1505318412-27121-1-git-send-email-patrice.chotard@st.com>\n\t<1505318412-27121-4-git-send-email-patrice.chotard@st.com>\n\t\n\t\n\t<30892c26-32a0-1934-b9ab-058b46e07143@st.com>\n\t<904b9f52-7abe-2257-5686-f185f5bbc06d@st.com>","In-Reply-To":"<904b9f52-7abe-2257-5686-f185f5bbc06d@st.com>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.75.127.44]","MIME-Version":"1.0","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-26_06:, , signatures=0","Subject":"Re: [U-Boot] [PATCH v2 3/9] dm: clk: add clk driver support for\n\tstm32h7 SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]