[{"id":1767912,"web_url":"http://patchwork.ozlabs.org/comment/1767912/","msgid":"<20170913160657.00b6bbe9@nial.brq.redhat.com>","list_archive_url":null,"date":"2017-09-13T14:06:57","subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","submitter":{"id":11305,"url":"http://patchwork.ozlabs.org/api/people/11305/","name":"Igor Mammedov","email":"imammedo@redhat.com"},"content":"On Wed, 13 Sep 2017 15:24:06 +0200\nDavid Hildenbrand wrote:\n\n> Specifying more than 1 CPU (e.g. -smp 5) leads to SIGP errors (the\n> guest tries to bring these CPUs up but fails), because we don't support\n> multiple CPUs on s390x under TCG.\n> \n> Let's bail out if more than 1 is specified, so we don't raise people's\n> hope.\n> \n> Tested-by: Matthew Rosato \n> Signed-off-by: David Hildenbrand \nReviewed-by: Igor Mammedov \n\n> ---\n> hw/s390x/s390-virtio-ccw.c | 6 ++++++\n> 1 file changed, 6 insertions(+)\n> \n> diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c\n> index f67b4b5d58..417998ec28 100644\n> --- a/hw/s390x/s390-virtio-ccw.c\n> +++ b/hw/s390x/s390-virtio-ccw.c\n> @@ -23,6 +23,7 @@\n> #include \"hw/s390x/css.h\"\n> #include \"virtio-ccw.h\"\n> #include \"qemu/config-file.h\"\n> +#include \"qemu/error-report.h\"\n> #include \"s390-pci-bus.h\"\n> #include \"hw/s390x/storage-keys.h\"\n> #include \"hw/s390x/storage-attributes.h\"\n> @@ -55,6 +56,11 @@ static void s390_init_cpus(MachineState *machine)\n> if (machine->cpu_model == NULL) {\n> machine->cpu_model = s390_default_cpu_model_name();\n> }\n> + if (tcg_enabled() && max_cpus > 1) {\n> + error_report(\"Number of SMP CPUs requested (%d) exceeds max CPUs \"\n> + \"supported by TCG (1) on s390x\", max_cpus);\n> + exit(1);\n> + }\n> \n> cpu_states = g_new0(S390CPU *, max_cpus);\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Wed, 13 Sep 2017 10:07:12 -0400","from mx1.redhat.com ([209.132.183.28]:56518)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1ds8Jm-0003gx-OZ\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 10:07:06 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 941E8C04B924;\n\tWed, 13 Sep 2017 14:07:04 +0000 (UTC)","from nial.brq.redhat.com (unknown [10.43.2.209])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id DB5B251919;\n\tWed, 13 Sep 2017 14:06:58 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 941E8C04B924","Date":"Wed, 13 Sep 2017 16:06:57 +0200","From":"Igor Mammedov ","To":"David Hildenbrand ","Message-ID":"<20170913160657.00b6bbe9@nial.brq.redhat.com>","In-Reply-To":"<20170913132417.24384-12-david@redhat.com>","References":"<20170913132417.24384-1-david@redhat.com>\n\t<20170913132417.24384-12-david@redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.31]);\n\tWed, 13 Sep 2017 14:07:04 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Matthew Rosato , thuth@redhat.com,\n\tEduardo Habkost ,\n\tMarkus Armbruster , cohuck@redhat.com,\n\tRichard Henderson ,\n\tqemu-devel@nongnu.org, Alexander Graf ,\n\tborntraeger@de.ibm.com, Paolo Bonzini ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1768005,"web_url":"http://patchwork.ozlabs.org/comment/1768005/","msgid":"<87lglia85d.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-13T16:13:50","subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"David Hildenbrand writes:\n\n> Specifying more than 1 CPU (e.g. -smp 5) leads to SIGP errors (the\n> guest tries to bring these CPUs up but fails), because we don't support\n> multiple CPUs on s390x under TCG.\n>\n> Let's bail out if more than 1 is specified, so we don't raise people's\n> hope.\n\nWhy does this restriction exist? Without MTTCG enabled -smp > 1 should\nbe safe from any races.\n\n>\n> Tested-by: Matthew Rosato \n> Signed-off-by: David Hildenbrand \n> ---\n> hw/s390x/s390-virtio-ccw.c | 6 ++++++\n> 1 file changed, 6 insertions(+)\n>\n> diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c\n> index f67b4b5d58..417998ec28 100644\n> --- a/hw/s390x/s390-virtio-ccw.c\n> +++ b/hw/s390x/s390-virtio-ccw.c\n> @@ -23,6 +23,7 @@\n> #include \"hw/s390x/css.h\"\n> #include \"virtio-ccw.h\"\n> #include \"qemu/config-file.h\"\n> +#include \"qemu/error-report.h\"\n> #include \"s390-pci-bus.h\"\n> #include \"hw/s390x/storage-keys.h\"\n> #include \"hw/s390x/storage-attributes.h\"\n> @@ -55,6 +56,11 @@ static void s390_init_cpus(MachineState *machine)\n> if (machine->cpu_model == NULL) {\n> machine->cpu_model = s390_default_cpu_model_name();\n> }\n> + if (tcg_enabled() && max_cpus > 1) {\n> + error_report(\"Number of SMP CPUs requested (%d) exceeds max CPUs \"\n> + \"supported by TCG (1) on s390x\", max_cpus);\n> + exit(1);\n> + }\n>\n> cpu_states = g_new0(S390CPU *, max_cpus);\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"David Hildenbrand ","In-reply-to":"<20170913132417.24384-12-david@redhat.com>","Date":"Wed, 13 Sep 2017 17:13:50 +0100","Message-ID":"<87lglia85d.fsf@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22b","Subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Matthew Rosato , thuth@redhat.com,\n\tEduardo Habkost ,\n\tMarkus Armbruster , cohuck@redhat.com,\n\tRichard Henderson ,\n\tqemu-devel@nongnu.org, Alexander Graf ,\n\tborntraeger@de.ibm.com, Paolo Bonzini ,\n\tIgor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1768008,"web_url":"http://patchwork.ozlabs.org/comment/1768008/","msgid":"","list_archive_url":null,"date":"2017-09-13T16:25:10","subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","submitter":{"id":70402,"url":"http://patchwork.ozlabs.org/api/people/70402/","name":"David Hildenbrand","email":"david@redhat.com"},"content":"On 13.09.2017 18:13, Alex Bennée wrote:\n> \n> David Hildenbrand writes:\n> \n>> Specifying more than 1 CPU (e.g. -smp 5) leads to SIGP errors (the\n>> guest tries to bring these CPUs up but fails), because we don't support\n>> multiple CPUs on s390x under TCG.\n>>\n>> Let's bail out if more than 1 is specified, so we don't raise people's\n>> hope.\n> \n> Why does this restriction exist? Without MTTCG enabled -smp > 1 should\n> be safe from any races.\n\nBecause the actual SIGP code (instruction to start/stop ... CPUs) is not\nimplemented yet.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsn924nm9z9s7C\n\tfor ;\n\tThu, 14 Sep 2017 02:26:14 +1000 (AEST)","from localhost ([::1]:43467 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dsAUO-0006yc-H5\n\tfor incoming@patchwork.ozlabs.org; Wed, 13 Sep 2017 12:26:12 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:56337)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dsATZ-0006uc-Jt\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 12:25:25 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dsATU-00080I-LL\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 12:25:21 -0400","from mx1.redhat.com ([209.132.183.28]:34040)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dsATU-0007zV-FY\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 12:25:16 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 5DD1581DF1;\n\tWed, 13 Sep 2017 16:25:15 +0000 (UTC)","from [10.36.116.230] (ovpn-116-230.ams2.redhat.com [10.36.116.230])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 0E4615E1D1;\n\tWed, 13 Sep 2017 16:25:11 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 5DD1581DF1","To":"=?utf-8?q?Alex_Benn=C3=A9e?= ","References":"<20170913132417.24384-1-david@redhat.com>\n\t<20170913132417.24384-12-david@redhat.com>\n\t<87lglia85d.fsf@linaro.org>","From":"David Hildenbrand ","Organization":"Red Hat GmbH","Message-ID":"","Date":"Wed, 13 Sep 2017 18:25:10 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<87lglia85d.fsf@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tWed, 13 Sep 2017 16:25:15 +0000 (UTC)","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Matthew Rosato , thuth@redhat.com,\n\tEduardo Habkost ,\n\tMarkus Armbruster , cohuck@redhat.com,\n\tRichard Henderson ,\n\tqemu-devel@nongnu.org, Alexander Graf ,\n\tborntraeger@de.ibm.com, Paolo Bonzini ,\n\tIgor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1769179,"web_url":"http://patchwork.ozlabs.org/comment/1769179/","msgid":"<87vakk85k8.fsf@linaro.org>","list_archive_url":null,"date":"2017-09-15T13:17:11","subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"David Hildenbrand writes:\n\n> On 13.09.2017 18:13, Alex Bennée wrote:\n>>\n>> David Hildenbrand writes:\n>>\n>>> Specifying more than 1 CPU (e.g. -smp 5) leads to SIGP errors (the\n>>> guest tries to bring these CPUs up but fails), because we don't support\n>>> multiple CPUs on s390x under TCG.\n>>>\n>>> Let's bail out if more than 1 is specified, so we don't raise people's\n>>> hope.\n>>\n>> Why does this restriction exist? Without MTTCG enabled -smp > 1 should\n>> be safe from any races.\n>\n> Because the actual SIGP code (instruction to start/stop ... CPUs) is not\n> implemented yet.\n\nAhh OK, I assume something like ARM's PCSI interface then.\n\nWhen you do get around to implementing just ensure you use the async\nmechanism to initialise the target processor state to avoid races in\nMTTCG. Essentially you queue the work up on the target and then it is\nrun before the powered up vCPU starts running code.\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"aiXrlYVp\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtwzg1jx0z9sRm\n\tfor ;\n\tFri, 15 Sep 2017 23:22:07 +1000 (AEST)","from localhost ([::1]:53383 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dsqZJ-0007eo-CR\n\tfor incoming@patchwork.ozlabs.org; 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emacs 25.2.50.3","From":"Alex =?utf-8?q?Benn=C3=A9e?= ","To":"David Hildenbrand ","In-reply-to":"","Date":"Fri, 15 Sep 2017 14:17:11 +0100","Message-ID":"<87vakk85k8.fsf@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22f","Subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Matthew Rosato , thuth@redhat.com,\n\tEduardo Habkost ,\n\tMarkus Armbruster , cohuck@redhat.com,\n\tRichard Henderson ,\n\tqemu-devel@nongnu.org, Alexander Graf ,\n\tborntraeger@de.ibm.com, Paolo Bonzini ,\n\tIgor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1769192,"web_url":"http://patchwork.ozlabs.org/comment/1769192/","msgid":"<7b5c88bf-50be-d692-2925-c549bfd79202@redhat.com>","list_archive_url":null,"date":"2017-09-15T13:36:15","subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","submitter":{"id":70402,"url":"http://patchwork.ozlabs.org/api/people/70402/","name":"David Hildenbrand","email":"david@redhat.com"},"content":"On 15.09.2017 15:17, Alex Bennée wrote:\n> \n> David Hildenbrand writes:\n> \n>> On 13.09.2017 18:13, Alex Bennée wrote:\n>>>\n>>> David Hildenbrand writes:\n>>>\n>>>> Specifying more than 1 CPU (e.g. -smp 5) leads to SIGP errors (the\n>>>> guest tries to bring these CPUs up but fails), because we don't support\n>>>> multiple CPUs on s390x under TCG.\n>>>>\n>>>> Let's bail out if more than 1 is specified, so we don't raise people's\n>>>> hope.\n>>>\n>>> Why does this restriction exist? Without MTTCG enabled -smp > 1 should\n>>> be safe from any races.\n>>\n>> Because the actual SIGP code (instruction to start/stop ... CPUs) is not\n>> implemented yet.\n> \n> Ahh OK, I assume something like ARM's PCSI interface then.\n> \n> When you do get around to implementing just ensure you use the async\n> mechanism to initialise the target processor state to avoid races in\n> MTTCG. Essentially you queue the work up on the target and then it is\n> run before the powered up vCPU starts running code.\n\nOne step at a time, right now I only test with single threaded. MTTCG is\nthe next step. But I have a good feeling about mttcg, at least speaking\nabout the SIGP implementation (for the \"critical\" stuff - start, stop,\ninitialize - I reuse the KVM code which uses even sync work).\n\n> \n> --\n> Alex Bennée\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=david@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtxJk65Bfz9sRm\n\tfor ;\n\tFri, 15 Sep 2017 23:36:52 +1000 (AEST)","from localhost ([::1]:53428 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dsqnZ-0006k3-Pl\n\tfor incoming@patchwork.ozlabs.org; Fri, 15 Sep 2017 09:36:49 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:47609)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dsqnD-0006jr-3x\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 09:36:28 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dsqnA-00075S-0i\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 09:36:27 -0400","from mx1.redhat.com ([209.132.183.28]:55452)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1dsqn9-00073z-Qb\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 09:36:23 -0400","from smtp.corp.redhat.com\n\t(int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 6E39925BAC;\n\tFri, 15 Sep 2017 13:36:22 +0000 (UTC)","from [10.36.117.187] (ovpn-117-187.ams2.redhat.com [10.36.117.187])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 10BCF74463;\n\tFri, 15 Sep 2017 13:36:16 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 6E39925BAC","To":"=?utf-8?q?Alex_Benn=C3=A9e?= ","References":"<20170913132417.24384-1-david@redhat.com>\n\t<20170913132417.24384-12-david@redhat.com>\n\t<87lglia85d.fsf@linaro.org>\n\t\n\t<87vakk85k8.fsf@linaro.org>","From":"David Hildenbrand ","Organization":"Red Hat GmbH","Message-ID":"<7b5c88bf-50be-d692-2925-c549bfd79202@redhat.com>","Date":"Fri, 15 Sep 2017 15:36:15 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<87vakk85k8.fsf@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.16","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.39]);\n\tFri, 15 Sep 2017 13:36:22 +0000 (UTC)","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"Re: [Qemu-devel] [PATCH v5 11/22] s390x: allow only 1 CPU with TCG","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Matthew Rosato , thuth@redhat.com,\n\tEduardo Habkost ,\n\tMarkus Armbruster , cohuck@redhat.com,\n\tRichard Henderson ,\n\tqemu-devel@nongnu.org, Alexander Graf ,\n\tborntraeger@de.ibm.com, Paolo Bonzini ,\n\tIgor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]