[{"id":1768119,"web_url":"http://patchwork.ozlabs.org/comment/1768119/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:07:43","subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n> Saradc integer divider control register is 8-bits width.\n> \n> Signed-off-by: David Wu \n> ---\n> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++\n> drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++\n> 2 files changed, 37 insertions(+)\n> \n\nAcked-by: Philipp Tomsich ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xst7y0hcKz9sBZ\n\tfor ;\n\tThu, 14 Sep 2017 06:10:37 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 42FFFC2231F; Wed, 13 Sep 2017 20:09:04 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 0B3C1C222A8;\n\tWed, 13 Sep 2017 20:08:05 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 8640EC22254; Wed, 13 Sep 2017 20:07:50 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id DAAD4C221AD\n\tfor ; Wed, 13 Sep 2017 20:07:46 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:62926\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dsDwl-0004RU-PD; Wed, 13 Sep 2017 22:07:43 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"David Wu ","In-Reply-To":"<1505302336-74720-1-git-send-email-david.wu@rock-chips.com>","References":"<1505302336-74720-1-git-send-email-david.wu@rock-chips.com>","Message-Id":"","Date":"Wed, 13 Sep 2017 22:07:43 +0200","Cc":"huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1768159,"web_url":"http://patchwork.ozlabs.org/comment/1768159/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:41:48","subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"On Wed, 13 Sep 2017, David Wu wrote:\n\n> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n> Saradc integer divider control register is 8-bits width.\n>\n> Signed-off-by: David Wu \n\nReviewed-by: Philipp Tomsich \n\nSee below for comments.\n\n> ---\n> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++\n> drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++\n> 2 files changed, 37 insertions(+)\n>\n> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h\n> index 2b1197f..31f7685 100644\n> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h\n> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h\n> @@ -89,6 +89,11 @@ enum {\n> \tMCU_CLK_DIV_SHIFT\t\t= 0,\n> \tMCU_CLK_DIV_MASK\t\t= GENMASK(4, 0),\n>\n> +\t/* CLKSEL_CON25 */\n> +\tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n> +\tCLK_SARADC_DIV_CON_MASK\t\t= 0xff << CLK_SARADC_DIV_CON_SHIFT,\n\nPlease use GENMASK.\n\n> +\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n> +\n> \t/* CLKSEL43_CON */\n> \tGMAC_MUX_SEL_EXTCLK = BIT(8),\n>\n> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\n> index 2be1f57..2eedf77 100644\n> --- a/drivers/clk/rockchip/clk_rk3368.c\n> +++ b/drivers/clk/rockchip/clk_rk3368.c\n> @@ -12,6 +12,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)\n> \treturn rk3368_spi_get_clk(cru, clk_id);\n> }\n>\n> +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)\n> +{\n> +\tu32 div, val;\n> +\n> +\tval = readl(&cru->clksel_con[25]);\n> +\tdiv = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n> +\t\t\t CLK_SARADC_DIV_CON_WIDTH);\n\nPlease reuse the functions from bitfield.h.\n\n> +\n> +\treturn DIV_TO_RATE(OSC_HZ, div);\n> +}\n> +\n> +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)\n> +{\n> +\tint src_clk_div;\n> +\n> +\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n> +\tassert(src_clk_div < 128);\n> +\n> +\trk_clrsetreg(&cru->clksel_con[25],\n> +\t\t CLK_SARADC_DIV_CON_MASK,\n> +\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn rk3368_saradc_get_clk(cru);\n> +}\n> +\n> static ulong rk3368_clk_get_rate(struct clk *clk)\n> {\n> \tstruct rk3368_clk_priv *priv = dev_get_priv(clk->dev);\n> @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk)\n> \t\trate = rk3368_mmc_get_clk(priv->cru, clk->id);\n> \t\tbreak;\n> #endif\n> +\tcase SCLK_SARADC:\n> +\t\trate = rk3368_saradc_get_clk(priv->cru);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)\n> \t\tret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);\n> \t\tbreak;\n> #endif\n> +\tcase SCLK_SARADC:\n> +\t\tret = rk3368_saradc_set_clk(priv->cru, rate);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xstr96bp2z9ryv\n\tfor ;\n\tThu, 14 Sep 2017 06:42:01 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid AE584C22420; Wed, 13 Sep 2017 20:41:57 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 5F861C22294;\n\tWed, 13 Sep 2017 20:41:55 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B9D26C222B7; Wed, 13 Sep 2017 20:41:52 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 63CF1C22294\n\tfor ; Wed, 13 Sep 2017 20:41:52 +0000 (UTC)","from [86.59.122.178] (port=60371 helo=android.lan)\n\tby mail.theobroma-systems.com with esmtps\n\t(TLS1.2:RSA_AES_128_CBC_SHA1:128)\n\t(Exim 4.80) (envelope-from )\n\tid 1dsETm-0005ad-0X; Wed, 13 Sep 2017 22:41:50 +0200","from [10.11.0.14] (helo=vpn-10-11-0-14.lan)\n\tby android.lan with esmtp (Exim 4.84_2)\n\t(envelope-from )\n\tid 1dsETl-00084K-Iq; Wed, 13 Sep 2017 22:41:49 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","Date":"Wed, 13 Sep 2017 22:41:48 +0200 (CEST)","From":"Philipp Tomsich ","X-X-Sender":"ptomsich@vpn-10-11-0-14.lan","To":"David Wu ","In-Reply-To":"<1505302336-74720-1-git-send-email-david.wu@rock-chips.com>","Message-ID":"","References":"<1505302336-74720-1-git-send-email-david.wu@rock-chips.com>","User-Agent":"Alpine 2.21 (OSX 202 2017-01-01)","MIME-Version":"1.0","Cc":"huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1768163,"web_url":"http://patchwork.ozlabs.org/comment/1768163/","msgid":"<6878D2E3-EEE2-492D-91FF-24F2F2DEB504@theobroma-systems.com>","list_archive_url":null,"date":"2017-09-13T20:44:18","subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> On 13 Sep 2017, at 22:41, Philipp Tomsich wrote:\n> \n> \n> \n> On Wed, 13 Sep 2017, David Wu wrote:\n> \n>> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n>> Saradc integer divider control register is 8-bits width.\n>> \n>> Signed-off-by: David Wu >\n> \n> Reviewed-by: Philipp Tomsich >\n> \n> See below for comments.\n> \n>> ---\n>> arch/arm/include/asm/arch-rockchip/cru_rk3368.h | 5 ++++\n>> drivers/clk/rockchip/clk_rk3368.c | 32 +++++++++++++++++++++++++\n>> 2 files changed, 37 insertions(+)\n>> \n>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h\n>> index 2b1197f..31f7685 100644\n>> --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h\n>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h\n>> @@ -89,6 +89,11 @@ enum {\n>> \tMCU_CLK_DIV_SHIFT\t\t= 0,\n>> \tMCU_CLK_DIV_MASK\t\t= GENMASK(4, 0),\n>> \n>> +\t/* CLKSEL_CON25 */\n>> +\tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n>> +\tCLK_SARADC_DIV_CON_MASK\t\t= 0xff << CLK_SARADC_DIV_CON_SHIFT,\n> \n> Please use GENMASK.\n> \n>> +\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n>> +\n>> \t/* CLKSEL43_CON */\n>> \tGMAC_MUX_SEL_EXTCLK = BIT(8),\n>> \n>> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\n>> index 2be1f57..2eedf77 100644\n>> --- a/drivers/clk/rockchip/clk_rk3368.c\n>> +++ b/drivers/clk/rockchip/clk_rk3368.c\n>> @@ -12,6 +12,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> #include \n>> #include \n>> #include \n>> @@ -397,6 +398,31 @@ static ulong rk3368_spi_set_clk(struct rk3368_cru *cru, ulong clk_id, uint hz)\n>> \treturn rk3368_spi_get_clk(cru, clk_id);\n>> }\n>> \n>> +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)\n>> +{\n>> +\tu32 div, val;\n>> +\n>> +\tval = readl(&cru->clksel_con[25]);\n>> +\tdiv = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n>> +\t\t\t CLK_SARADC_DIV_CON_WIDTH);\n> \n> Please reuse the functions from bitfield.h.\n\nIt’s apparently too late to do code reviews: please ignore this comment.\n\n> \n>> +\n>> +\treturn DIV_TO_RATE(OSC_HZ, div);\n>> +}\n>> +\n>> +static ulong rk3368_saradc_set_clk(struct rk3368_cru *cru, uint hz)\n>> +{\n>> +\tint src_clk_div;\n>> +\n>> +\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n>> +\tassert(src_clk_div < 128);\n>> +\n>> +\trk_clrsetreg(&cru->clksel_con[25],\n>> +\t\t CLK_SARADC_DIV_CON_MASK,\n>> +\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n>> +\n>> +\treturn rk3368_saradc_get_clk(cru);\n>> +}\n>> +\n>> static ulong rk3368_clk_get_rate(struct clk *clk)\n>> {\n>> \tstruct rk3368_clk_priv *priv = dev_get_priv(clk->dev);\n>> @@ -419,6 +445,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk)\n>> \t\trate = rk3368_mmc_get_clk(priv->cru, clk->id);\n>> \t\tbreak;\n>> #endif\n>> +\tcase SCLK_SARADC:\n>> +\t\trate = rk3368_saradc_get_clk(priv->cru);\n>> +\t\tbreak;\n>> \tdefault:\n>> \t\treturn -ENOENT;\n>> \t}\n>> @@ -453,6 +482,9 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)\n>> \t\tret = rk3368_gmac_set_clk(priv->cru, clk->id, rate);\n>> \t\tbreak;\n>> #endif\n>> +\tcase SCLK_SARADC:\n>> +\t\tret = rk3368_saradc_set_clk(priv->cru, rate);\n>> +\t\tbreak;\n>> \tdefault:\n>> \t\treturn -ENOENT;\n>> \t}","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xstv82kr6z9ryv\n\tfor ;\n\tThu, 14 Sep 2017 06:44:36 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 143A2C22420; Wed, 13 Sep 2017 20:44:26 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 43F9BC22294;\n\tWed, 13 Sep 2017 20:44:24 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B91A9C22294; Wed, 13 Sep 2017 20:44:22 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 6F7CAC22168\n\tfor ; Wed, 13 Sep 2017 20:44:22 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:64461\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dsEWC-0005bl-4X; Wed, 13 Sep 2017 22:44:20 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","From":"\"Dr. Philipp Tomsich\" ","Message-Id":"<6878D2E3-EEE2-492D-91FF-24F2F2DEB504@theobroma-systems.com>","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","Date":"Wed, 13 Sep 2017 22:44:18 +0200","In-Reply-To":"","To":"David Wu ","References":"<1505302336-74720-1-git-send-email-david.wu@rock-chips.com>\n\t","X-Mailer":"Apple Mail (2.3273)","X-Content-Filtered-By":"Mailman/MimeDel 2.1.18","Cc":"huangtao@rock-chips.com, Elaine Zhang ,\n\tU-Boot Mailing List ,\n\tAndy Yan , chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1768648,"web_url":"http://patchwork.ozlabs.org/comment/1768648/","msgid":"<2494C065-F364-422F-8E4B-AC4FBCC6E8ED@theobroma-systems.com>","list_archive_url":null,"date":"2017-09-14T14:55:25","subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> On 14 Sep 2017, at 13:17, David.Wu wrote:\n> \n> Hi Philipp,\n> \n> 在 2017/9/14 4:41, Philipp Tomsich 写道:\n>>> +static ulong rk3368_saradc_get_clk(struct rk3368_cru *cru)\n>>> +{\n>>> + u32 div, val;\n>>> +\n>>> + val = readl(&cru->clksel_con[25]);\n>>> + div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,\n>>> + CLK_SARADC_DIV_CON_WIDTH);\n>> Please reuse the functions from bitfield.h.\n> \n> Ah, the bitfield_extract function is from bitfield.h here.\n> \n\nI was suffering from a lack of sleep yesterday, so just ignore this comment of mine.\n—Phil.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtM6q6Z37z9s0Z\n\tfor ;\n\tFri, 15 Sep 2017 00:56:19 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 990F7C21DB2; Thu, 14 Sep 2017 14:55:52 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C1C73C21E01;\n\tThu, 14 Sep 2017 14:55:41 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid C42C9C21DB2; Thu, 14 Sep 2017 14:55:38 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 43FFBC21D5F\n\tfor ; Thu, 14 Sep 2017 14:55:34 +0000 (UTC)","from [86.59.122.178] (port=52765 helo=[10.4.9.36])\n\tby mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dsVY6-0003bp-BQ; Thu, 14 Sep 2017 16:55:26 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<5cb33a24-5e59-ec30-90fa-0a30f7de4b2b@rock-chips.com>","Date":"Thu, 14 Sep 2017 16:55:25 +0200","Message-Id":"<2494C065-F364-422F-8E4B-AC4FBCC6E8ED@theobroma-systems.com>","References":"<1505302336-74720-1-git-send-email-david.wu@rock-chips.com>\n\t\n\t<5cb33a24-5e59-ec30-90fa-0a30f7de4b2b@rock-chips.com>","To":"\"David.Wu\" ","X-Mailer":"Apple Mail (2.3273)","Cc":"huangtao@rock-chips.com, zhangqing@rock-chips.com, u-boot@lists.denx.de, \n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t6/8] clk: rockchip: Add rk3368 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]