[{"id":1768121,"web_url":"http://patchwork.ozlabs.org/comment/1768121/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:07:42","subject":"Re: [U-Boot] [U-Boot,\n\t5/8] clk: rockchip: Add rk3328 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n> Saradc integer divider control register is 10-bits width.\n> \n> Signed-off-by: David Wu \n> ---\n> drivers/clk/rockchip/clk_rk3328.c | 37 +++++++++++++++++++++++++++++++++++++\n> 1 file changed, 37 insertions(+)\n> \n\nAcked-by: Philipp Tomsich ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xst9g0TD8z9sBW\n\tfor ;\n\tThu, 14 Sep 2017 06:12:06 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid CC5C3C22341; Wed, 13 Sep 2017 20:10:04 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 8F054C2230C;\n\tWed, 13 Sep 2017 20:08:44 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid E932BC21F2B; Wed, 13 Sep 2017 20:07:50 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id EFA3DC2218E\n\tfor ; Wed, 13 Sep 2017 20:07:46 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:62926\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dsDwk-0004RU-TY; Wed, 13 Sep 2017 22:07:43 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"David Wu ","In-Reply-To":"<1505299969-13329-1-git-send-email-david.wu@rock-chips.com>","References":"<1505299969-13329-1-git-send-email-david.wu@rock-chips.com>","Message-Id":"","Date":"Wed, 13 Sep 2017 22:07:42 +0200","Cc":"huangtao@rock-chips.com, linux-rockchip@lists.infradead.org,\n\tzhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com,\n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t5/8] clk: rockchip: Add rk3328 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1768164,"web_url":"http://patchwork.ozlabs.org/comment/1768164/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:44:34","subject":"Re: [U-Boot] [U-Boot,\n\t5/8] clk: rockchip: Add rk3328 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"On Wed, 13 Sep 2017, David Wu wrote:\n\n> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).\n> Saradc integer divider control register is 10-bits width.\n>\n> Signed-off-by: David Wu \n\nReviewed-by: Philipp Tomsich \n\nSee below for comments.\n\n> ---\n> drivers/clk/rockchip/clk_rk3328.c | 37 +++++++++++++++++++++++++++++++++++++\n> 1 file changed, 37 insertions(+)\n>\n> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c\n> index c3a6650..e1ae7b2 100644\n> --- a/drivers/clk/rockchip/clk_rk3328.c\n> +++ b/drivers/clk/rockchip/clk_rk3328.c\n> @@ -115,6 +115,7 @@ enum {\n> \t/* CLKSEL_CON23 */\n> \tCLK_SARADC_DIV_CON_SHIFT\t= 0,\n> \tCLK_SARADC_DIV_CON_MASK\t\t= 0x3ff << CLK_SARADC_DIV_CON_SHIFT,\n\nCan we use GENMASK here?\n\n> +\tCLK_SARADC_DIV_CON_WIDTH\t= 10,\n>\n> \t/* CLKSEL_CON24 */\n> \tCLK_PWM_PLL_SEL_CPLL\t\t= 0,\n> @@ -180,6 +181,11 @@ enum {\n> #define PLL_DIV_MIN\t16\n> #define PLL_DIV_MAX\t3200\n>\n> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)\n> +{\n> +\treturn (val >> shift) & ((1 << width) - 1);\n\nCan we use the functions from bitfield.h, please?\n\n> +}\n> +\n> /*\n> * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):\n> * Formulas also embedded within the Fractional PLL Verilog model:\n> @@ -478,6 +484,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)\n> \treturn DIV_TO_RATE(GPLL_HZ, div);\n> }\n>\n> +static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)\n> +{\n> +\tu32 div, val;\n> +\n> +\tval = readl(&cru->clksel_con[23]);\n> +\tdiv = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,\n> +\t\t\t CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn DIV_TO_RATE(OSC_HZ, div);\n> +}\n> +\n> +static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)\n> +{\n> +\tint src_clk_div;\n> +\n> +\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n> +\tassert(src_clk_div < 128);\n> +\n> +\trk_clrsetreg(&cru->clksel_con[23],\n> +\t\t CLK_SARADC_DIV_CON_MASK,\n> +\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn rk3328_saradc_get_clk(cru);\n> +}\n> +\n> static ulong rk3328_clk_get_rate(struct clk *clk)\n> {\n> \tstruct rk3328_clk_priv *priv = dev_get_priv(clk->dev);\n> @@ -501,6 +532,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)\n> \tcase SCLK_PWM:\n> \t\trate = rk3328_pwm_get_clk(priv->cru);\n> \t\tbreak;\n> +\tcase SCLK_SARADC:\n> +\t\trate = rk3328_saradc_get_clk(priv->cru);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> @@ -531,6 +565,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)\n> \tcase SCLK_PWM:\n> \t\tret = rk3328_pwm_set_clk(priv->cru, rate);\n> \t\tbreak;\n> +\tcase SCLK_SARADC:\n> +\t\tret = rk3328_saradc_set_clk(priv->cru, rate);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Wed, 13 Sep 2017 22:44:35 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","Date":"Wed, 13 Sep 2017 22:44:34 +0200 (CEST)","From":"Philipp Tomsich ","X-X-Sender":"ptomsich@vpn-10-11-0-14.lan","To":"David Wu ","In-Reply-To":"<1505299969-13329-1-git-send-email-david.wu@rock-chips.com>","Message-ID":"","References":"<1505299969-13329-1-git-send-email-david.wu@rock-chips.com>","User-Agent":"Alpine 2.21 (OSX 202 2017-01-01)","MIME-Version":"1.0","Cc":"huangtao@rock-chips.com, linux-rockchip@lists.infradead.org,\n\tzhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com,\n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t5/8] clk: rockchip: Add rk3328 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; 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