[{"id":1768129,"web_url":"http://patchwork.ozlabs.org/comment/1768129/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:07:41","subject":"Re: [U-Boot] [U-Boot,\n\t3/8] clk: rockchip: Add rv1108 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> Signed-off-by: David Wu \n> ---\n> arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++\n> drivers/clk/rockchip/clk_rv1108.c | 35 +++++++++++++++++++++++++\n> include/dt-bindings/clock/rv1108-cru.h | 2 ++\n> 3 files changed, 42 insertions(+)\n> \n\nAcked-by: Philipp Tomsich ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xstDq4j3Rz9rxj\n\tfor ;\n\tThu, 14 Sep 2017 06:14:51 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 692ACC2236D; Wed, 13 Sep 2017 20:09:20 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 6BE66C222D1;\n\tWed, 13 Sep 2017 20:08:26 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 2B0EDC220CB; Wed, 13 Sep 2017 20:07:48 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id 9CA26C21E9B\n\tfor ; Wed, 13 Sep 2017 20:07:45 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:62926\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dsDwj-0004RU-7b; Wed, 13 Sep 2017 22:07:41 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"David Wu ","In-Reply-To":"<1505297379-12638-4-git-send-email-david.wu@rock-chips.com>","References":"<1505297379-12638-4-git-send-email-david.wu@rock-chips.com>","Message-Id":"","Date":"Wed, 13 Sep 2017 22:07:41 +0200","Cc":"huangtao@rock-chips.com, linux-rockchip@lists.infradead.org,\n\tzhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com,\n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t3/8] clk: rockchip: Add rv1108 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1768165,"web_url":"http://patchwork.ozlabs.org/comment/1768165/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:45:37","subject":"Re: [U-Boot] [U-Boot,\n\t3/8] clk: rockchip: Add rv1108 Saradc clock support","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"On Wed, 13 Sep 2017, David Wu wrote:\n\n> Signed-off-by: David Wu \n\nReviewed-by: Philipp Tomsich \n\n> ---\n> arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 5 ++++\n> drivers/clk/rockchip/clk_rv1108.c | 35 +++++++++++++++++++++++++\n> include/dt-bindings/clock/rv1108-cru.h | 2 ++\n> 3 files changed, 42 insertions(+)\n>\n> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h\n> index 2a1ae69..b134559 100644\n> --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h\n> +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h\n> @@ -90,6 +90,11 @@ enum {\n> \tCORE_CLK_DIV_SHIFT\t= 0,\n> \tCORE_CLK_DIV_MASK\t= 0x1f << CORE_CLK_DIV_SHIFT,\n>\n> +\t/* CLKSEL_CON22 */\n> +\tCLK_SARADC_DIV_CON_SHIFT= 0,\n> +\tCLK_SARADC_DIV_CON_MASK\t= 0x3ff << CLK_SARADC_DIV_CON_SHIFT,\n\nCan we use GENMASK here?\n\n> +\tCLK_SARADC_DIV_CON_WIDTH= 10,\n> +\n> \t/* CLKSEL24_CON */\n> \tMAC_PLL_SEL_SHIFT\t= 12,\n> \tMAC_PLL_SEL_MASK\t= 1 << MAC_PLL_SEL_SHIFT,\n> diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c\n> index cf966bb..aa989c6 100644\n> --- a/drivers/clk/rockchip/clk_rv1108.c\n> +++ b/drivers/clk/rockchip/clk_rv1108.c\n> @@ -36,6 +36,11 @@ enum {\n> \t\t\t #hz \"Hz cannot be hit with PLL \"\\\n> \t\t\t \"divisors on line \" __stringify(__LINE__));\n>\n> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)\n> +{\n> +\treturn (val >> shift) & ((1 << width) - 1);\n\nThe comment regarding bitfield.h applies again.\n\n> +}\n> +\n> /* use interge mode*/\n\ntypo: integer\n\n> static inline int rv1108_pll_id(enum rk_clk_id clk_id)\n> {\n> @@ -130,6 +135,31 @@ static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)\n> \treturn DIV_TO_RATE(pll_rate, div);\n> }\n>\n> +static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)\n> +{\n> +\tu32 div, val;\n> +\n> +\tval = readl(&cru->clksel_con[22]);\n> +\tdiv = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,\n> +\t\t\t CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn DIV_TO_RATE(OSC_HZ, div);\n> +}\n> +\n> +static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)\n> +{\n> +\tint src_clk_div;\n> +\n> +\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n> +\tassert(src_clk_div < 128);\n> +\n> +\trk_clrsetreg(&cru->clksel_con[22],\n> +\t\t CLK_SARADC_DIV_CON_MASK,\n> +\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn rv1108_saradc_get_clk(cru);\n> +}\n> +\n> static ulong rv1108_clk_get_rate(struct clk *clk)\n> {\n> \tstruct rv1108_clk_priv *priv = dev_get_priv(clk->dev);\n> @@ -137,6 +167,8 @@ static ulong rv1108_clk_get_rate(struct clk *clk)\n> \tswitch (clk->id) {\n> \tcase 0 ... 63:\n> \t\treturn rkclk_pll_get_rate(priv->cru, clk->id);\n> +\tcase SCLK_SARADC:\n> +\t\treturn rv1108_saradc_get_clk(priv->cru);\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> @@ -154,6 +186,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)\n> \tcase SCLK_SFC:\n> \t\tnew_rate = rv1108_sfc_set_clk(priv->cru, rate);\n> \t\tbreak;\n> +\tcase SCLK_SARADC:\n> +\t\tnew_rate = rv1108_saradc_set_clk(priv->cru, rate);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h\n> index d2ad3bb..7defc6b 100644\n> --- a/include/dt-bindings/clock/rv1108-cru.h\n> +++ b/include/dt-bindings/clock/rv1108-cru.h\n> @@ -39,6 +39,7 @@\n> #define SCLK_MAC_TX\t\t\t88\n> #define SCLK_MACREF\t\t\t89\n> #define SCLK_MACREF_OUT\t\t\t90\n> +#define SCLK_SARADC\t\t\t91\n>\n>\n> /* aclk gates */\n> @@ -67,6 +68,7 @@\n> #define PCLK_TIMER\t\t\t270\n> #define PCLK_PERI\t\t\t271\n> #define PCLK_GMAC\t\t\t272\n> +#define PCLK_SARADC\t\t\t273\n>\n> /* hclk gates */\n> #define HCLK_I2S0_8CH\t\t\t320\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Wed, 13 Sep 2017 22:45:38 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","Date":"Wed, 13 Sep 2017 22:45:37 +0200 (CEST)","From":"Philipp Tomsich ","X-X-Sender":"ptomsich@vpn-10-11-0-14.lan","To":"David Wu ","In-Reply-To":"<1505297379-12638-4-git-send-email-david.wu@rock-chips.com>","Message-ID":"","References":"<1505297379-12638-4-git-send-email-david.wu@rock-chips.com>","User-Agent":"Alpine 2.21 (OSX 202 2017-01-01)","MIME-Version":"1.0","Cc":"huangtao@rock-chips.com, linux-rockchip@lists.infradead.org,\n\tzhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com,\n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t3/8] clk: rockchip: Add rv1108 Saradc clock support","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; 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