[{"id":1767570,"web_url":"http://patchwork.ozlabs.org/comment/1767570/","msgid":"","list_archive_url":null,"date":"2017-09-13T04:27:37","subject":"Re: [U-Boot] [PATCH] rockchip: enable TPL_SYSRESET for all rockchip\n\tSoCs","submitter":{"id":6170,"url":"http://patchwork.ozlabs.org/api/people/6170/","name":"Simon Glass","email":"sjg@chromium.org"},"content":"On 12 September 2017 at 19:39, Kever Yang wrote:\n> With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET\n> for do_reset() in TPL for Rockchip SoCs.\n>\n> References: 87c16d4 \"drivers: spl: consistently use the $(SPL_TPL_)\n> macro\"\n>\n> Signed-off-by: Kever Yang \n> ---\n>\n> arch/arm/Kconfig | 1 +\n> 1 file changed, 1 insertion(+)\n\nReviewed-by: Simon Glass ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=google.com header.i=@google.com\n\theader.b=\"mEhzUxqt\"; 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Tue, 12 Sep 2017 21:27:37 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0","DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com;\n\ts=20161025; \n\th=mime-version:sender:in-reply-to:references:from:date:message-id\n\t:subject:to:cc;\n\tbh=6MJ3vLjWHjOiZj68vBHUJE7f2z/Du2XcgwNzN6H0bVw=;\n\tb=mEhzUxqtAySyc8QFKow2BOKO+HuRoWHlgmPn8rFsfOfECPa6LFH+Or01/iHD3ttEyN\n\thRf3hbcYyAtBm1XQDUFdK4+ip7z28NznfM4AyKnAspcJbREwwi7FDvDkFkNkq0Cul19P\n\tAIfRTWoFN7xOJNvhzgFNhAnialT+VAFQY9eJ/PETvh2rBgvVK0njtUsvd+Fl196pup1B\n\tZQBpYKMSrsFZizHvGvKd4OpGuzkUGA71JZ8PhHR0/FFDwetazxZcfZj/scH/+/SP8LM1\n\tD538GJTGejekyoeTgyXZpsSLy/vdHyqkmBrBoRC4GmxjlF0lz4Uegpkv+LwvGNKxXNMf\n\tSZFQ==","v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org;\n\ts=google; \n\th=mime-version:sender:in-reply-to:references:from:date:message-id\n\t:subject:to:cc;\n\tbh=6MJ3vLjWHjOiZj68vBHUJE7f2z/Du2XcgwNzN6H0bVw=;\n\tb=jt8pZqZ4biGK8ktCSgWMnfMP6syp9XjsxQt1NaEETrowRtlnBCjcIc3ltrJoI4zwT8\n\tiU65toPI64fLvoqeuC17s/gXRtHqOJ8bSYzs1FV4APr5oxmGjDYUW0E8ehPNDiUi8aHi\n\t3FGtCKp4Ddn2LTPtEvIvSZOtDa/a4vpxwz0H8="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:sender:in-reply-to:references:from\n\t:date:message-id:subject:to:cc;\n\tbh=6MJ3vLjWHjOiZj68vBHUJE7f2z/Du2XcgwNzN6H0bVw=;\n\tb=CxXPPzh9aYlorA1mt4tzWUGL9cUR6A0+lRu29Or923bmHrvV70iBe9DA6B4p456nsL\n\t7KJMzHMEZrIleI+fozRoDXOCd9m9noswhqLoix87AIaL/4dxc1f9S72Udh8YYbjh4u+c\n\tsRsKJd9J6T9inVa3PLPL5Bs4KL5G853Iou+j05G3zAysLs8pMv52IJZqsrot5zQC2D7g\n\tEp7rAUGJC9WPJcNmrg09tly6IFGzXuxMJTMz9nqDA7CIfngqytszVwE8rYSF8Pj3heG2\n\t8d0pFoWT8xiTFojn2G3Y3XDi+qDeg3ZiAXm8J4QfpPggZc3sdv+iNZmVbOUTPG06h3az\n\trqrQ==","X-Gm-Message-State":"AHPjjUiay+8tlu0jadaGKGRhGAo8Oyo8/M7hoVmFV9wLmgkBkqtJQLAv\n\tHYKAvcAw8x6oHylOjqFqaf6NRyr2rctCYgGb9fTcM0mM","X-Google-Smtp-Source":"AOwi7QD5uwyzyvZpFMH+WzAo92FI+pD4JcLVXkjactyo+jbU+nWaPwI1NNCBCDPxsGIjSpugxFbmw0nFPnKInacuiH0=","X-Received":"by 10.200.63.154 with SMTP id d26mr24649951qtk.212.1505276878442;\n\tTue, 12 Sep 2017 21:27:58 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1505266746-17625-1-git-send-email-kever.yang@rock-chips.com>","References":"<1505266746-17625-1-git-send-email-kever.yang@rock-chips.com>","From":"Simon Glass ","Date":"Tue, 12 Sep 2017 22:27:37 -0600","X-Google-Sender-Auth":"VgoRAE4xHaYI1wUlq8I0TqTs1C0","Message-ID":"","To":"Kever Yang ","Cc":"U-Boot Mailing List ,\n\tAlbert Aribaud ","Subject":"Re: [U-Boot] [PATCH] rockchip: enable TPL_SYSRESET for all rockchip\n\tSoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777695,"web_url":"http://patchwork.ozlabs.org/comment/1777695/","msgid":"","list_archive_url":null,"date":"2017-09-29T17:53:14","subject":"Re: [U-Boot] rockchip: enable TPL_SYSRESET for all rockchip SoCs","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET\n> for do_reset() in TPL for Rockchip SoCs.\n> \n> References: 87c16d4 \"drivers: spl: consistently use the $(SPL_TPL_)\n> macro\"\n> \n> Signed-off-by: Kever Yang \n> Reviewed-by: Simon Glass \n> ---\n> \n> arch/arm/Kconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n\nReviewed-by: Philipp Tomsich ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y3fLc3ZfVz9s9Y\n\tfor ;\n\tSat, 30 Sep 2017 03:53:44 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 2F510C21E68; Fri, 29 Sep 2017 17:53:39 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A0A77C21E8A;\n\tFri, 29 Sep 2017 17:53:34 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid DA75DC21F09; Fri, 29 Sep 2017 17:53:19 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id B151AC21E63\n\tfor ; Fri, 29 Sep 2017 17:53:15 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:52368\n\thelo=vpn-10-11-0-14.lan) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1dxzTO-00050D-NZ; Fri, 29 Sep 2017 19:53:14 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"Kever Yang ","In-Reply-To":"<1505266746-17625-1-git-send-email-kever.yang@rock-chips.com>","References":"<1505266746-17625-1-git-send-email-kever.yang@rock-chips.com>","Message-Id":"","Date":"Fri, 29 Sep 2017 19:53:14 +0200","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] rockchip: enable TPL_SYSRESET for all rockchip SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1777701,"web_url":"http://patchwork.ozlabs.org/comment/1777701/","msgid":"","list_archive_url":null,"date":"2017-09-29T17:58:40","subject":"Re: [U-Boot] rockchip: enable TPL_SYSRESET for all rockchip SoCs","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> With Makefiles testing for $(SPL_TPL_)SYSRESET, we need TPL_SYSRESET\n> for do_reset() in TPL for Rockchip SoCs.\n> \n> References: 87c16d4 \"drivers: spl: consistently use the $(SPL_TPL_)\n> macro\"\n> \n> Signed-off-by: Kever Yang \n> Reviewed-by: Simon Glass \n> ---\n> \n> arch/arm/Kconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n\nApplied to u-boot-rockchip, thanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Fri, 29 Sep 2017 19:58:40 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"Kever Yang ","In-Reply-To":"<1505266746-17625-1-git-send-email-kever.yang@rock-chips.com>","References":"<1505266746-17625-1-git-send-email-kever.yang@rock-chips.com>","Message-Id":"","Date":"Fri, 29 Sep 2017 19:58:40 +0200","Cc":"u-boot@lists.denx.de","Subject":"Re: [U-Boot] rockchip: enable TPL_SYSRESET for all rockchip SoCs","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]