[{"id":1767791,"web_url":"http://patchwork.ozlabs.org/comment/1767791/","msgid":"<f8002ede-5ff5-6544-b8bf-c92cefc3f9d7@denx.de>","list_archive_url":null,"date":"2017-09-13T10:52:09","subject":"Re: [U-Boot] [PATCH v2 14/14] sunxi: sina33: Sync the device tree\n\twith the kernel","submitter":{"id":70701,"url":"http://patchwork.ozlabs.org/api/people/70701/","name":"Lukasz Majewski","email":"lukma@denx.de"},"content":"On 09/12/2017 09:01 PM, Maxime Ripard wrote:\n> The kernel DT of the SinA33 has evolved quite a bit. Make sure we sync it\n> and its upstream DTSI to be able to use the OTG. The DTs were taken from\n> the 4.13 kernel release.\n> \n> Reviewed-by: Simon Glass <sjg@chromium.org>\n> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>\n> ---\n>   arch/arm/dts/axp223.dtsi                      |  58 ++-\n>   arch/arm/dts/axp22x.dtsi                      |  10 +-\n>   arch/arm/dts/sun8i-a23-a33.dtsi               | 446 +++++++-----------\n>   arch/arm/dts/sun8i-a33-sinlinx-sina33.dts     |  43 ++-\n>   arch/arm/dts/sun8i-a33.dtsi                   | 477 +++++++++++++++----\n>   include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 127 +++++-\n>   include/dt-bindings/reset/sun8i-a23-a33-ccu.h |  87 +++-\n>   7 files changed, 914 insertions(+), 334 deletions(-)\n>   create mode 100644 arch/arm/dts/axp223.dtsi\n>   create mode 100644 include/dt-bindings/clock/sun8i-a23-a33-ccu.h\n>   create mode 100644 include/dt-bindings/reset/sun8i-a23-a33-ccu.h\n> \n> diff --git a/arch/arm/dts/axp223.dtsi b/arch/arm/dts/axp223.dtsi\n> new file mode 100644\n> index 000000000000..b91b6c1278c7\n> --- /dev/null\n> +++ b/arch/arm/dts/axp223.dtsi\n> @@ -0,0 +1,58 @@\n> +/*\n> + * Copyright 2016 Free Electrons\n> + *\n> + * Quentin Schulz <quentin.schulz@free-electrons.com>\n> + *\n> + * This file is dual-licensed: you can use it either under the terms\n> + * of the GPL or the X11 license, at your option. Note that this dual\n> + * licensing only applies to this file, and not this project as a\n> + * whole.\n> + *\n> + *  a) This file is free software; you can redistribute it and/or\n> + *     modify it under the terms of the GNU General Public License as\n> + *     published by the Free Software Foundation; either version 2 of the\n> + *     License, or (at your option) any later version.\n> + *\n> + *     This file is distributed in the hope that it will be useful,\n> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n> + *     GNU General Public License for more details.\n> + *\n> + * Or, alternatively,\n> + *\n> + *  b) Permission is hereby granted, free of charge, to any person\n> + *     obtaining a copy of this software and associated documentation\n> + *     files (the \"Software\"), to deal in the Software without\n> + *     restriction, including without limitation the rights to use,\n> + *     copy, modify, merge, publish, distribute, sublicense, and/or\n> + *     sell copies of the Software, and to permit persons to whom the\n> + *     Software is furnished to do so, subject to the following\n> + *     conditions:\n> + *\n> + *     The above copyright notice and this permission notice shall be\n> + *     included in all copies or substantial portions of the Software.\n> + *\n> + *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n> + *     OTHER DEALINGS IN THE SOFTWARE.\n> + */\n> +\n> +/*\n> + * AXP223 Integrated Power Management Chip\n> + * http://www.x-powers.com/product/AXP22X.php\n> + * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf\n> + *\n> + * The AXP223 shares most of its logic with the AXP221 but it has some\n> + * differences, for the VBUS driver for example.\n> + */\n> +\n> +#include \"axp22x.dtsi\"\n> +\n> +&usb_power_supply {\n> +\tcompatible = \"x-powers,axp223-usb-power-supply\";\n> +};\n> diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi\n> index 458b6681e3ec..87fb08e812ec 100644\n> --- a/arch/arm/dts/axp22x.dtsi\n> +++ b/arch/arm/dts/axp22x.dtsi\n> @@ -52,6 +52,16 @@\n>   \tinterrupt-controller;\n>   \t#interrupt-cells = <1>;\n>   \n> +\tac_power_supply: ac-power-supply {\n> +\t\tcompatible = \"x-powers,axp221-ac-power-supply\";\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tbattery_power_supply: battery-power-supply {\n> +\t\tcompatible = \"x-powers,axp221-battery-power-supply\";\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n>   \tregulators {\n>   \t\t/* Default work frequency for buck regulators */\n>   \t\tx-powers,dcdc-freq = <3000>;\n> diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi\n> index f97c38f097d1..ea50dda75adc 100644\n> --- a/arch/arm/dts/sun8i-a23-a33.dtsi\n> +++ b/arch/arm/dts/sun8i-a23-a33.dtsi\n> @@ -46,7 +46,8 @@\n>   \n>   #include <dt-bindings/interrupt-controller/arm-gic.h>\n>   \n> -#include <dt-bindings/pinctrl/sun4i-a10.h>\n> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>\n> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>\n>   \n>   / {\n>   \tinterrupt-parent = <&gic>;\n> @@ -60,7 +61,9 @@\n>   \t\t\tcompatible = \"allwinner,simple-framebuffer\",\n>   \t\t\t\t     \"simple-framebuffer\";\n>   \t\t\tallwinner,pipeline = \"de_be0-lcd0\";\n> -\t\t\tclocks = <&pll6 0>;\n> +\t\t\tclocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,\n> +\t\t\t\t <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,\n> +\t\t\t\t <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;\n>   \t\t\tstatus = \"disabled\";\n>   \t\t};\n>   \t};\n> @@ -80,7 +83,7 @@\n>   \t\t#address-cells = <1>;\n>   \t\t#size-cells = <0>;\n>   \n> -\t\tcpu@0 {\n> +\t\tcpu0: cpu@0 {\n>   \t\t\tcompatible = \"arm,cortex-a7\";\n>   \t\t\tdevice_type = \"cpu\";\n>   \t\t\treg = <0>;\n> @@ -102,151 +105,16 @@\n>   \t\t\t#clock-cells = <0>;\n>   \t\t\tcompatible = \"fixed-clock\";\n>   \t\t\tclock-frequency = <24000000>;\n> +\t\t\tclock-accuracy = <50000>;\n>   \t\t\tclock-output-names = \"osc24M\";\n>   \t\t};\n>   \n> -\t\tosc32k: osc32k_clk {\n> +\t\text_osc32k: ext_osc32k_clk {\n>   \t\t\t#clock-cells = <0>;\n>   \t\t\tcompatible = \"fixed-clock\";\n>   \t\t\tclock-frequency = <32768>;\n> -\t\t\tclock-output-names = \"osc32k\";\n> -\t\t};\n> -\n> -\t\tpll1: clk@01c20000 {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n> -\t\t\treg = <0x01c20000 0x4>;\n> -\t\t\tclocks = <&osc24M>;\n> -\t\t\tclock-output-names = \"pll1\";\n> -\t\t};\n> -\n> -\t\t/* dummy clock until actually implemented */\n> -\t\tpll5: pll5_clk {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"fixed-clock\";\n> -\t\t\tclock-frequency = <0>;\n> -\t\t\tclock-output-names = \"pll5\";\n> -\t\t};\n> -\n> -\t\tpll6: clk@01c20028 {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n> -\t\t\treg = <0x01c20028 0x4>;\n> -\t\t\tclocks = <&osc24M>;\n> -\t\t\tclock-output-names = \"pll6\", \"pll6x2\";\n> -\t\t};\n> -\n> -\t\tcpu: cpu_clk@01c20050 {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n> -\t\t\treg = <0x01c20050 0x4>;\n> -\n> -\t\t\t/*\n> -\t\t\t * PLL1 is listed twice here.\n> -\t\t\t * While it looks suspicious, it's actually documented\n> -\t\t\t * that way both in the datasheet and in the code from\n> -\t\t\t * Allwinner.\n> -\t\t\t */\n> -\t\t\tclocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;\n> -\t\t\tclock-output-names = \"cpu\";\n> -\t\t};\n> -\n> -\t\taxi: axi_clk@01c20050 {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a23-axi-clk\";\n> -\t\t\treg = <0x01c20050 0x4>;\n> -\t\t\tclocks = <&cpu>;\n> -\t\t\tclock-output-names = \"axi\";\n> -\t\t};\n> -\n> -\t\tahb1: ahb1_clk@01c20054 {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n> -\t\t\treg = <0x01c20054 0x4>;\n> -\t\t\tclocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;\n> -\t\t\tclock-output-names = \"ahb1\";\n> -\t\t};\n> -\n> -\t\tapb1: apb1_clk@01c20054 {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n> -\t\t\treg = <0x01c20054 0x4>;\n> -\t\t\tclocks = <&ahb1>;\n> -\t\t\tclock-output-names = \"apb1\";\n> -\t\t};\n> -\n> -\t\tapb1_gates: clk@01c20068 {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a23-apb1-gates-clk\";\n> -\t\t\treg = <0x01c20068 0x4>;\n> -\t\t\tclocks = <&apb1>;\n> -\t\t\tclock-indices = <0>, <5>,\n> -\t\t\t\t\t<12>, <13>;\n> -\t\t\tclock-output-names = \"apb1_codec\", \"apb1_pio\",\n> -\t\t\t\t\t\"apb1_daudio0\",\t\"apb1_daudio1\";\n> -\t\t};\n> -\n> -\t\tapb2: clk@01c20058 {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n> -\t\t\treg = <0x01c20058 0x4>;\n> -\t\t\tclocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;\n> -\t\t\tclock-output-names = \"apb2\";\n> -\t\t};\n> -\n> -\t\tapb2_gates: clk@01c2006c {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a23-apb2-gates-clk\";\n> -\t\t\treg = <0x01c2006c 0x4>;\n> -\t\t\tclocks = <&apb2>;\n> -\t\t\tclock-indices = <0>, <1>,\n> -\t\t\t\t\t<2>, <16>,\n> -\t\t\t\t\t<17>, <18>,\n> -\t\t\t\t\t<19>, <20>;\n> -\t\t\tclock-output-names = \"apb2_i2c0\", \"apb2_i2c1\",\n> -\t\t\t\t\t\"apb2_i2c2\", \"apb2_uart0\",\n> -\t\t\t\t\t\"apb2_uart1\", \"apb2_uart2\",\n> -\t\t\t\t\t\"apb2_uart3\", \"apb2_uart4\";\n> -\t\t};\n> -\n> -\t\tmmc0_clk: clk@01c20088 {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n> -\t\t\treg = <0x01c20088 0x4>;\n> -\t\t\tclocks = <&osc24M>, <&pll6 0>;\n> -\t\t\tclock-output-names = \"mmc0\",\n> -\t\t\t\t\t     \"mmc0_output\",\n> -\t\t\t\t\t     \"mmc0_sample\";\n> -\t\t};\n> -\n> -\t\tmmc1_clk: clk@01c2008c {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n> -\t\t\treg = <0x01c2008c 0x4>;\n> -\t\t\tclocks = <&osc24M>, <&pll6 0>;\n> -\t\t\tclock-output-names = \"mmc1\",\n> -\t\t\t\t\t     \"mmc1_output\",\n> -\t\t\t\t\t     \"mmc1_sample\";\n> -\t\t};\n> -\n> -\t\tmmc2_clk: clk@01c20090 {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n> -\t\t\treg = <0x01c20090 0x4>;\n> -\t\t\tclocks = <&osc24M>, <&pll6 0>;\n> -\t\t\tclock-output-names = \"mmc2\",\n> -\t\t\t\t\t     \"mmc2_output\",\n> -\t\t\t\t\t     \"mmc2_sample\";\n> -\t\t};\n> -\n> -\t\tusb_clk: clk@01c200cc {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\t#reset-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a23-usb-clk\";\n> -\t\t\treg = <0x01c200cc 0x4>;\n> -\t\t\tclocks = <&osc24M>;\n> -\t\t\tclock-output-names = \"usb_phy0\", \"usb_phy1\", \"usb_hsic\",\n> -\t\t\t\t\t     \"usb_hsic_12M\", \"usb_ohci0\";\n> +\t\t\tclock-accuracy = <50000>;\n> +\t\t\tclock-output-names = \"ext-osc32k\";\n>   \t\t};\n>   \t};\n>   \n> @@ -260,24 +128,23 @@\n>   \t\t\tcompatible = \"allwinner,sun8i-a23-dma\";\n>   \t\t\treg = <0x01c02000 0x1000>;\n>   \t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&ahb1_gates 6>;\n> -\t\t\tresets = <&ahb1_rst 6>;\n> +\t\t\tclocks = <&ccu CLK_BUS_DMA>;\n> +\t\t\tresets = <&ccu RST_BUS_DMA>;\n>   \t\t\t#dma-cells = <1>;\n>   \t\t};\n>   \n>   \t\tmmc0: mmc@01c0f000 {\n> -\t\t\tcompatible = \"allwinner,sun7i-a20-mmc\",\n> -\t\t\t\t     \"allwinner,sun5i-a13-mmc\";\n> +\t\t\tcompatible = \"allwinner,sun7i-a20-mmc\";\n>   \t\t\treg = <0x01c0f000 0x1000>;\n> -\t\t\tclocks = <&ahb1_gates 8>,\n> -\t\t\t\t <&mmc0_clk 0>,\n> -\t\t\t\t <&mmc0_clk 1>,\n> -\t\t\t\t <&mmc0_clk 2>;\n> +\t\t\tclocks = <&ccu CLK_BUS_MMC0>,\n> +\t\t\t\t <&ccu CLK_MMC0>,\n> +\t\t\t\t <&ccu CLK_MMC0_OUTPUT>,\n> +\t\t\t\t <&ccu CLK_MMC0_SAMPLE>;\n>   \t\t\tclock-names = \"ahb\",\n>   \t\t\t\t      \"mmc\",\n>   \t\t\t\t      \"output\",\n>   \t\t\t\t      \"sample\";\n> -\t\t\tresets = <&ahb1_rst 8>;\n> +\t\t\tresets = <&ccu RST_BUS_MMC0>;\n>   \t\t\treset-names = \"ahb\";\n>   \t\t\tinterrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\tstatus = \"disabled\";\n> @@ -286,18 +153,17 @@\n>   \t\t};\n>   \n>   \t\tmmc1: mmc@01c10000 {\n> -\t\t\tcompatible = \"allwinner,sun7i-a20-mmc\",\n> -\t\t\t\t     \"allwinner,sun5i-a13-mmc\";\n> +\t\t\tcompatible = \"allwinner,sun7i-a20-mmc\";\n>   \t\t\treg = <0x01c10000 0x1000>;\n> -\t\t\tclocks = <&ahb1_gates 9>,\n> -\t\t\t\t <&mmc1_clk 0>,\n> -\t\t\t\t <&mmc1_clk 1>,\n> -\t\t\t\t <&mmc1_clk 2>;\n> +\t\t\tclocks = <&ccu CLK_BUS_MMC1>,\n> +\t\t\t\t <&ccu CLK_MMC1>,\n> +\t\t\t\t <&ccu CLK_MMC1_OUTPUT>,\n> +\t\t\t\t <&ccu CLK_MMC1_SAMPLE>;\n>   \t\t\tclock-names = \"ahb\",\n>   \t\t\t\t      \"mmc\",\n>   \t\t\t\t      \"output\",\n>   \t\t\t\t      \"sample\";\n> -\t\t\tresets = <&ahb1_rst 9>;\n> +\t\t\tresets = <&ccu RST_BUS_MMC1>;\n>   \t\t\treset-names = \"ahb\";\n>   \t\t\tinterrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\tstatus = \"disabled\";\n> @@ -306,18 +172,17 @@\n>   \t\t};\n>   \n>   \t\tmmc2: mmc@01c11000 {\n> -\t\t\tcompatible = \"allwinner,sun7i-a20-mmc\",\n> -\t\t\t\t     \"allwinner,sun5i-a13-mmc\";\n> +\t\t\tcompatible = \"allwinner,sun7i-a20-mmc\";\n>   \t\t\treg = <0x01c11000 0x1000>;\n> -\t\t\tclocks = <&ahb1_gates 10>,\n> -\t\t\t\t <&mmc2_clk 0>,\n> -\t\t\t\t <&mmc2_clk 1>,\n> -\t\t\t\t <&mmc2_clk 2>;\n> +\t\t\tclocks = <&ccu CLK_BUS_MMC2>,\n> +\t\t\t\t <&ccu CLK_MMC2>,\n> +\t\t\t\t <&ccu CLK_MMC2_OUTPUT>,\n> +\t\t\t\t <&ccu CLK_MMC2_SAMPLE>;\n>   \t\t\tclock-names = \"ahb\",\n>   \t\t\t\t      \"mmc\",\n>   \t\t\t\t      \"output\",\n>   \t\t\t\t      \"sample\";\n> -\t\t\tresets = <&ahb1_rst 10>;\n> +\t\t\tresets = <&ccu RST_BUS_MMC2>;\n>   \t\t\treset-names = \"ahb\";\n>   \t\t\tinterrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\tstatus = \"disabled\";\n> @@ -325,12 +190,55 @@\n>   \t\t\t#size-cells = <0>;\n>   \t\t};\n>   \n> +\t\tnfc: nand@01c03000 {\n> +\t\t\tcompatible = \"allwinner,sun4i-a10-nand\";\n> +\t\t\treg = <0x01c03000 0x1000>;\n> +\t\t\tinterrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;\n> +\t\t\tclock-names = \"ahb\", \"mod\";\n> +\t\t\tresets = <&ccu RST_BUS_NAND>;\n> +\t\t\treset-names = \"ahb\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t};\n> +\n> +\t\tusb_otg: usb@01c19000 {\n> +\t\t\t/* compatible gets set in SoC specific dtsi file */\n> +\t\t\treg = <0x01c19000 0x0400>;\n> +\t\t\tclocks = <&ccu CLK_BUS_OTG>;\n> +\t\t\tresets = <&ccu RST_BUS_OTG>;\n> +\t\t\tinterrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tinterrupt-names = \"mc\";\n> +\t\t\tphys = <&usbphy 0>;\n> +\t\t\tphy-names = \"usb\";\n> +\t\t\textcon = <&usbphy 0>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tusbphy: phy@01c19400 {\n> +\t\t\t/*\n> +\t\t\t * compatible and address regions get set in\n> +\t\t\t * SoC specific dtsi file\n> +\t\t\t */\n> +\t\t\tclocks = <&ccu CLK_USB_PHY0>,\n> +\t\t\t\t <&ccu CLK_USB_PHY1>;\n> +\t\t\tclock-names = \"usb0_phy\",\n> +\t\t\t\t      \"usb1_phy\";\n> +\t\t\tresets = <&ccu RST_USB_PHY0>,\n> +\t\t\t\t <&ccu RST_USB_PHY1>;\n> +\t\t\treset-names = \"usb0_reset\",\n> +\t\t\t\t      \"usb1_reset\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\t#phy-cells = <1>;\n> +\t\t};\n> +\n>   \t\tehci0: usb@01c1a000 {\n>   \t\t\tcompatible = \"allwinner,sun8i-a23-ehci\", \"generic-ehci\";\n>   \t\t\treg = <0x01c1a000 0x100>;\n>   \t\t\tinterrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&ahb1_gates 26>;\n> -\t\t\tresets = <&ahb1_rst 26>;\n> +\t\t\tclocks = <&ccu CLK_BUS_EHCI>;\n> +\t\t\tresets = <&ccu RST_BUS_EHCI>;\n>   \t\t\tphys = <&usbphy 1>;\n>   \t\t\tphy-names = \"usb\";\n>   \t\t\tstatus = \"disabled\";\n> @@ -340,101 +248,100 @@\n>   \t\t\tcompatible = \"allwinner,sun8i-a23-ohci\", \"generic-ohci\";\n>   \t\t\treg = <0x01c1a400 0x100>;\n>   \t\t\tinterrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&ahb1_gates 29>, <&usb_clk 16>;\n> -\t\t\tresets = <&ahb1_rst 29>;\n> +\t\t\tclocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;\n> +\t\t\tresets = <&ccu RST_BUS_OHCI>;\n>   \t\t\tphys = <&usbphy 1>;\n>   \t\t\tphy-names = \"usb\";\n>   \t\t\tstatus = \"disabled\";\n>   \t\t};\n>   \n> +\t\tccu: clock@01c20000 {\n> +\t\t\treg = <0x01c20000 0x400>;\n> +\t\t\tclocks = <&osc24M>, <&rtc 0>;\n> +\t\t\tclock-names = \"hosc\", \"losc\";\n> +\t\t\t#clock-cells = <1>;\n> +\t\t\t#reset-cells = <1>;\n> +\t\t};\n> +\n>   \t\tpio: pinctrl@01c20800 {\n>   \t\t\t/* compatible gets set in SoC specific dtsi file */\n>   \t\t\treg = <0x01c20800 0x400>;\n>   \t\t\t/* interrupts get set in SoC specific dtsi file */\n> -\t\t\tclocks = <&apb1_gates 5>;\n> +\t\t\tclocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;\n> +\t\t\tclock-names = \"apb\", \"hosc\", \"losc\";\n>   \t\t\tgpio-controller;\n>   \t\t\tinterrupt-controller;\n>   \t\t\t#interrupt-cells = <3>;\n>   \t\t\t#gpio-cells = <3>;\n>   \n>   \t\t\tuart0_pins_a: uart0@0 {\n> -\t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n> -\t\t\t\tallwinner,function = \"uart0\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PF2\", \"PF4\";\n> +\t\t\t\tfunction = \"uart0\";\n> +\t\t\t};\n> +\n> +\t\t\tuart1_pins_a: uart1@0 {\n> +\t\t\t\tpins = \"PG6\", \"PG7\";\n> +\t\t\t\tfunction = \"uart1\";\n> +\t\t\t};\n> +\n> +\t\t\tuart1_pins_cts_rts_a: uart1-cts-rts@0 {\n> +\t\t\t\tpins = \"PG8\", \"PG9\";\n> +\t\t\t\tfunction = \"uart1\";\n>   \t\t\t};\n>   \n>   \t\t\tmmc0_pins_a: mmc0@0 {\n> -\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\",\n> -\t\t\t\t\t\t \"PF3\", \"PF4\", \"PF5\";\n> -\t\t\t\tallwinner,function = \"mmc0\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PF0\", \"PF1\", \"PF2\",\n> +\t\t\t\t       \"PF3\", \"PF4\", \"PF5\";\n> +\t\t\t\tfunction = \"mmc0\";\n> +\t\t\t\tdrive-strength = <30>;\n> +\t\t\t\tbias-pull-up;\n>   \t\t\t};\n>   \n>   \t\t\tmmc1_pins_a: mmc1@0 {\n> -\t\t\t\tallwinner,pins = \"PG0\", \"PG1\", \"PG2\",\n> -\t\t\t\t\t\t \"PG3\", \"PG4\", \"PG5\";\n> -\t\t\t\tallwinner,function = \"mmc1\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PG0\", \"PG1\", \"PG2\",\n> +\t\t\t\t       \"PG3\", \"PG4\", \"PG5\";\n> +\t\t\t\tfunction = \"mmc1\";\n> +\t\t\t\tdrive-strength = <30>;\n> +\t\t\t\tbias-pull-up;\n>   \t\t\t};\n>   \n>   \t\t\tmmc2_8bit_pins: mmc2_8bit {\n> -\t\t\t\tallwinner,pins = \"PC5\", \"PC6\", \"PC8\",\n> -\t\t\t\t\t\t \"PC9\", \"PC10\", \"PC11\",\n> -\t\t\t\t\t\t \"PC12\", \"PC13\", \"PC14\",\n> -\t\t\t\t\t\t \"PC15\", \"PC16\";\n> -\t\t\t\tallwinner,function = \"mmc2\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_30_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PC5\", \"PC6\", \"PC8\",\n> +\t\t\t\t       \"PC9\", \"PC10\", \"PC11\",\n> +\t\t\t\t       \"PC12\", \"PC13\", \"PC14\",\n> +\t\t\t\t       \"PC15\", \"PC16\";\n> +\t\t\t\tfunction = \"mmc2\";\n> +\t\t\t\tdrive-strength = <30>;\n> +\t\t\t\tbias-pull-up;\n>   \t\t\t};\n>   \n>   \t\t\tpwm0_pins: pwm0 {\n> -\t\t\t\tallwinner,pins = \"PH0\";\n> -\t\t\t\tallwinner,function = \"pwm0\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PH0\";\n> +\t\t\t\tfunction = \"pwm0\";\n>   \t\t\t};\n>   \n>   \t\t\ti2c0_pins_a: i2c0@0 {\n> -\t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n> -\t\t\t\tallwinner,function = \"i2c0\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PH2\", \"PH3\";\n> +\t\t\t\tfunction = \"i2c0\";\n>   \t\t\t};\n>   \n>   \t\t\ti2c1_pins_a: i2c1@0 {\n> -\t\t\t\tallwinner,pins = \"PH4\", \"PH5\";\n> -\t\t\t\tallwinner,function = \"i2c1\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PH4\", \"PH5\";\n> +\t\t\t\tfunction = \"i2c1\";\n>   \t\t\t};\n>   \n>   \t\t\ti2c2_pins_a: i2c2@0 {\n> -\t\t\t\tallwinner,pins = \"PE12\", \"PE13\";\n> -\t\t\t\tallwinner,function = \"i2c2\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PE12\", \"PE13\";\n> +\t\t\t\tfunction = \"i2c2\";\n>   \t\t\t};\n> -\t\t};\n> -\n> -\t\tahb1_rst: reset@01c202c0 {\n> -\t\t\t#reset-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n> -\t\t\treg = <0x01c202c0 0xc>;\n> -\t\t};\n>   \n> -\t\tapb1_rst: reset@01c202d0 {\n> -\t\t\t#reset-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n> -\t\t\treg = <0x01c202d0 0x4>;\n> -\t\t};\n> -\n> -\t\tapb2_rst: reset@01c202d8 {\n> -\t\t\t#reset-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n> -\t\t\treg = <0x01c202d8 0x4>;\n> +\t\t\tlcd_rgb666_pins: lcd-rgb666@0 {\n> +\t\t\t\tpins = \"PD2\", \"PD3\", \"PD4\", \"PD5\", \"PD6\", \"PD7\",\n> +\t\t\t\t       \"PD10\", \"PD11\", \"PD12\", \"PD13\", \"PD14\", \"PD15\",\n> +\t\t\t\t       \"PD18\", \"PD19\", \"PD20\", \"PD21\", \"PD22\", \"PD23\",\n> +\t\t\t\t       \"PD24\", \"PD25\", \"PD26\", \"PD27\";\n> +\t\t\t\tfunction = \"lcd0\";\n> +\t\t\t};\n>   \t\t};\n>   \n>   \t\ttimer@01c20c00 {\n> @@ -472,8 +379,8 @@\n>   \t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\treg-shift = <2>;\n>   \t\t\treg-io-width = <4>;\n> -\t\t\tclocks = <&apb2_gates 16>;\n> -\t\t\tresets = <&apb2_rst 16>;\n> +\t\t\tclocks = <&ccu CLK_BUS_UART0>;\n> +\t\t\tresets = <&ccu RST_BUS_UART0>;\n>   \t\t\tdmas = <&dma 6>, <&dma 6>;\n>   \t\t\tdma-names = \"rx\", \"tx\";\n>   \t\t\tstatus = \"disabled\";\n> @@ -485,8 +392,8 @@\n>   \t\t\tinterrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\treg-shift = <2>;\n>   \t\t\treg-io-width = <4>;\n> -\t\t\tclocks = <&apb2_gates 17>;\n> -\t\t\tresets = <&apb2_rst 17>;\n> +\t\t\tclocks = <&ccu CLK_BUS_UART1>;\n> +\t\t\tresets = <&ccu RST_BUS_UART1>;\n>   \t\t\tdmas = <&dma 7>, <&dma 7>;\n>   \t\t\tdma-names = \"rx\", \"tx\";\n>   \t\t\tstatus = \"disabled\";\n> @@ -498,8 +405,8 @@\n>   \t\t\tinterrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\treg-shift = <2>;\n>   \t\t\treg-io-width = <4>;\n> -\t\t\tclocks = <&apb2_gates 18>;\n> -\t\t\tresets = <&apb2_rst 18>;\n> +\t\t\tclocks = <&ccu CLK_BUS_UART2>;\n> +\t\t\tresets = <&ccu RST_BUS_UART2>;\n>   \t\t\tdmas = <&dma 8>, <&dma 8>;\n>   \t\t\tdma-names = \"rx\", \"tx\";\n>   \t\t\tstatus = \"disabled\";\n> @@ -511,8 +418,8 @@\n>   \t\t\tinterrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\treg-shift = <2>;\n>   \t\t\treg-io-width = <4>;\n> -\t\t\tclocks = <&apb2_gates 19>;\n> -\t\t\tresets = <&apb2_rst 19>;\n> +\t\t\tclocks = <&ccu CLK_BUS_UART3>;\n> +\t\t\tresets = <&ccu RST_BUS_UART3>;\n>   \t\t\tdmas = <&dma 9>, <&dma 9>;\n>   \t\t\tdma-names = \"rx\", \"tx\";\n>   \t\t\tstatus = \"disabled\";\n> @@ -524,8 +431,8 @@\n>   \t\t\tinterrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t\treg-shift = <2>;\n>   \t\t\treg-io-width = <4>;\n> -\t\t\tclocks = <&apb2_gates 20>;\n> -\t\t\tresets = <&apb2_rst 20>;\n> +\t\t\tclocks = <&ccu CLK_BUS_UART4>;\n> +\t\t\tresets = <&ccu RST_BUS_UART4>;\n>   \t\t\tdmas = <&dma 10>, <&dma 10>;\n>   \t\t\tdma-names = \"rx\", \"tx\";\n>   \t\t\tstatus = \"disabled\";\n> @@ -535,8 +442,8 @@\n>   \t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n>   \t\t\treg = <0x01c2ac00 0x400>;\n>   \t\t\tinterrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&apb2_gates 0>;\n> -\t\t\tresets = <&apb2_rst 0>;\n> +\t\t\tclocks = <&ccu CLK_BUS_I2C0>;\n> +\t\t\tresets = <&ccu RST_BUS_I2C0>;\n>   \t\t\tstatus = \"disabled\";\n>   \t\t\t#address-cells = <1>;\n>   \t\t\t#size-cells = <0>;\n> @@ -546,8 +453,8 @@\n>   \t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n>   \t\t\treg = <0x01c2b000 0x400>;\n>   \t\t\tinterrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&apb2_gates 1>;\n> -\t\t\tresets = <&apb2_rst 1>;\n> +\t\t\tclocks = <&ccu CLK_BUS_I2C1>;\n> +\t\t\tresets = <&ccu RST_BUS_I2C1>;\n>   \t\t\tstatus = \"disabled\";\n>   \t\t\t#address-cells = <1>;\n>   \t\t\t#size-cells = <0>;\n> @@ -557,17 +464,44 @@\n>   \t\t\tcompatible = \"allwinner,sun6i-a31-i2c\";\n>   \t\t\treg = <0x01c2b400 0x400>;\n>   \t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&apb2_gates 2>;\n> -\t\t\tresets = <&apb2_rst 2>;\n> +\t\t\tclocks = <&ccu CLK_BUS_I2C2>;\n> +\t\t\tresets = <&ccu RST_BUS_I2C2>;\n>   \t\t\tstatus = \"disabled\";\n>   \t\t\t#address-cells = <1>;\n>   \t\t\t#size-cells = <0>;\n>   \t\t};\n>   \n> +\t\tmali: gpu@1c40000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-a23-mali\",\n> +\t\t\t\t     \"allwinner,sun7i-a20-mali\", \"arm,mali-400\";\n> +\t\t\treg = <0x01c40000 0x10000>;\n> +\t\t\tinterrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t\t     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t\t     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t\t     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t\t     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t\t     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t\t     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tinterrupt-names = \"gp\",\n> +\t\t\t\t\t  \"gpmmu\",\n> +\t\t\t\t\t  \"pp0\",\n> +\t\t\t\t\t  \"ppmmu0\",\n> +\t\t\t\t\t  \"pp1\",\n> +\t\t\t\t\t  \"ppmmu1\",\n> +\t\t\t\t\t  \"pmu\";\n> +\t\t\tclocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;\n> +\t\t\tclock-names = \"bus\", \"core\";\n> +\t\t\tresets = <&ccu RST_BUS_GPU>;\n> +\t\t\t#cooling-cells = <2>;\n> +\n> +\t\t\tassigned-clocks = <&ccu CLK_GPU>;\n> +\t\t\tassigned-clock-rates = <384000000>;\n> +\t\t};\n> +\n>   \t\tgic: interrupt-controller@01c81000 {\n>   \t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n>   \t\t\treg = <0x01c81000 0x1000>,\n> -\t\t\t      <0x01c82000 0x1000>,\n> +\t\t\t      <0x01c82000 0x2000>,\n>   \t\t\t      <0x01c84000 0x2000>,\n>   \t\t\t      <0x01c86000 0x2000>;\n>   \t\t\tinterrupt-controller;\n> @@ -580,13 +514,16 @@\n>   \t\t\treg = <0x01f00000 0x54>;\n>   \t\t\tinterrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,\n>   \t\t\t\t     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclock-output-names = \"osc32k\";\n> +\t\t\tclocks = <&ext_osc32k>;\n> +\t\t\t#clock-cells = <1>;\n>   \t\t};\n>   \n> -\t\tnmi_intc: interrupt-controller@01f00c0c {\n> -\t\t\tcompatible = \"allwinner,sun6i-a31-sc-nmi\";\n> +\t\tnmi_intc: interrupt-controller@1f00c00 {\n> +\t\t\tcompatible = \"allwinner,sun6i-a31-r-intc\";\n>   \t\t\tinterrupt-controller;\n>   \t\t\t#interrupt-cells = <2>;\n> -\t\t\treg = <0x01f00c0c 0x38>;\n> +\t\t\treg = <0x01f00c00 0x400>;\n>   \t\t\tinterrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;\n>   \t\t};\n>   \n> @@ -632,6 +569,10 @@\n>   \t\t\t\tcompatible = \"allwinner,sun6i-a31-clock-reset\";\n>   \t\t\t\t#reset-cells = <1>;\n>   \t\t\t};\n> +\n> +\t\t\tcodec_analog: codec-analog {\n> +\t\t\t\tcompatible = \"allwinner,sun8i-a23-codec-analog\";\n> +\t\t\t};\n>   \t\t};\n>   \n>   \t\tcpucfg@01f01c00 {\n> @@ -654,7 +595,8 @@\n>   \t\t\tcompatible = \"allwinner,sun8i-a23-r-pinctrl\";\n>   \t\t\treg = <0x01f02c00 0x400>;\n>   \t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&apb0_gates 0>;\n> +\t\t\tclocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;\n> +\t\t\tclock-names = \"apb\", \"hosc\", \"losc\";\n>   \t\t\tresets = <&apb0_rst 0>;\n>   \t\t\tgpio-controller;\n>   \t\t\tinterrupt-controller;\n> @@ -664,17 +606,15 @@\n>   \t\t\t#gpio-cells = <3>;\n>   \n>   \t\t\tr_rsb_pins: r_rsb {\n> -\t\t\t\tallwinner,pins = \"PL0\", \"PL1\";\n> -\t\t\t\tallwinner,function = \"s_rsb\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_20_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_PULL_UP>;\n> +\t\t\t\tpins = \"PL0\", \"PL1\";\n> +\t\t\t\tfunction = \"s_rsb\";\n> +\t\t\t\tdrive-strength = <20>;\n> +\t\t\t\tbias-pull-up;\n>   \t\t\t};\n>   \n>   \t\t\tr_uart_pins_a: r_uart@0 {\n> -\t\t\t\tallwinner,pins = \"PL2\", \"PL3\";\n> -\t\t\t\tallwinner,function = \"s_uart\";\n> -\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\t\t\tpins = \"PL2\", \"PL3\";\n> +\t\t\t\tfunction = \"s_uart\";\n>   \t\t\t};\n>   \t\t};\n>   \n> diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts\n> index fef6abc0a703..b1bc88c46c67 100644\n> --- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts\n> +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts\n> @@ -61,6 +61,31 @@\n>   \tchosen {\n>   \t\tstdout-path = \"serial0:115200n8\";\n>   \t};\n> +\n> +\tpanel {\n> +\t\tcompatible = \"netron-dy,e231732\";\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tport@0 {\n> +\t\t\treg = <0>;\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\n> +\t\t\tpanel_input: endpoint@0 {\n> +\t\t\t\treg = <0>;\n> +\t\t\t\tremote-endpoint = <&tcon0_out_panel>;\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +};\n> +\n> +&de {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&cpu0 {\n> +\tcpu-supply = <&reg_dcdc3>;\n>   };\n>   \n>   &ehci0 {\n> @@ -207,12 +232,30 @@\n>   \tregulator-name = \"vcc-rtc\";\n>   };\n>   \n> +&tcon0 {\n> +\tpinctrl-names = \"default\";\n> +\tpinctrl-0 = <&lcd_rgb666_pins>;\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&tcon0_out {\n> +\ttcon0_out_panel: endpoint@0 {\n> +\t\treg = <0>;\n> +\t\tremote-endpoint = <&panel_input>;\n> +\t};\n> +};\n> +\n>   &uart0 {\n>   \tpinctrl-names = \"default\";\n>   \tpinctrl-0 = <&uart0_pins_b>;\n>   \tstatus = \"okay\";\n>   };\n>   \n> +&usb_otg {\n> +\tdr_mode = \"peripheral\";\n> +\tstatus = \"okay\";\n> +};\n> +\n>   &usbphy {\n>   \tstatus = \"okay\";\n>   \tusb1_vbus-supply = <&reg_vcc5v0>; /* USB1 VBUS is always on */\n> diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi\n> index 001d8402ca18..22660919bd08 100644\n> --- a/arch/arm/dts/sun8i-a33.dtsi\n> +++ b/arch/arm/dts/sun8i-a33.dtsi\n> @@ -43,19 +43,137 @@\n>    */\n>   \n>   #include \"sun8i-a23-a33.dtsi\"\n> +#include <dt-bindings/thermal/thermal.h>\n>   \n>   / {\n> +\tcpu0_opp_table: opp_table0 {\n> +\t\tcompatible = \"operating-points-v2\";\n> +\t\topp-shared;\n> +\n> +\t\topp-120000000 {\n> +\t\t\topp-hz = /bits/ 64 <120000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-240000000 {\n> +\t\t\topp-hz = /bits/ 64 <240000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-312000000 {\n> +\t\t\topp-hz = /bits/ 64 <312000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-408000000 {\n> +\t\t\topp-hz = /bits/ 64 <408000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-480000000 {\n> +\t\t\topp-hz = /bits/ 64 <480000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-504000000 {\n> +\t\t\topp-hz = /bits/ 64 <504000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-600000000 {\n> +\t\t\topp-hz = /bits/ 64 <600000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-648000000 {\n> +\t\t\topp-hz = /bits/ 64 <648000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-720000000 {\n> +\t\t\topp-hz = /bits/ 64 <720000000>;\n> +\t\t\topp-microvolt = <1100000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-816000000 {\n> +\t\t\topp-hz = /bits/ 64 <816000000>;\n> +\t\t\topp-microvolt = <1100000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-912000000 {\n> +\t\t\topp-hz = /bits/ 64 <912000000>;\n> +\t\t\topp-microvolt = <1200000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-1008000000 {\n> +\t\t\topp-hz = /bits/ 64 <1008000000>;\n> +\t\t\topp-microvolt = <1200000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\t};\n> +\n>   \tcpus {\n> +\t\tcpu@0 {\n> +\t\t\tclocks = <&ccu CLK_CPUX>;\n> +\t\t\tclock-names = \"cpu\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> +\t\t\t#cooling-cells = <2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> +\t\t};\n> +\n>   \t\tcpu@2 {\n>   \t\t\tcompatible = \"arm,cortex-a7\";\n>   \t\t\tdevice_type = \"cpu\";\n>   \t\t\treg = <2>;\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n>   \t\t};\n>   \n>   \t\tcpu@3 {\n>   \t\t\tcompatible = \"arm,cortex-a7\";\n>   \t\t\tdevice_type = \"cpu\";\n>   \t\t\treg = <3>;\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> +\t\t};\n> +\t};\n> +\n> +\tde: display-engine {\n> +\t\tcompatible = \"allwinner,sun8i-a33-display-engine\";\n> +\t\tallwinner,pipelines = <&fe0>;\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tiio-hwmon {\n> +\t\tcompatible = \"iio-hwmon\";\n> +\t\tio-channels = <&ths>;\n> +\t};\n> +\n> +\tmali_opp_table: gpu-opp-table {\n> +\t\tcompatible = \"operating-points-v2\";\n> +\n> +\t\topp-144000000 {\n> +\t\t\topp-hz = /bits/ 64 <144000000>;\n> +\t\t};\n> +\n> +\t\topp-240000000 {\n> +\t\t\topp-hz = /bits/ 64 <240000000>;\n> +\t\t};\n> +\n> +\t\topp-384000000 {\n> +\t\t\topp-hz = /bits/ 64 <384000000>;\n>   \t\t};\n>   \t};\n>   \n> @@ -63,113 +181,310 @@\n>   \t\treg = <0x40000000 0x80000000>;\n>   \t};\n>   \n> -\tclocks {\n> -\t\t/* Dummy clock for pll11 (DDR1) until actually implemented */\n> -\t\tpll11: pll11_clk {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"fixed-clock\";\n> -\t\t\tclock-frequency = <0>;\n> -\t\t\tclock-output-names = \"pll11\";\n> -\t\t};\n> -\n> -\t\tahb1_gates: clk@01c20060 {\n> -\t\t\t#clock-cells = <1>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a33-ahb1-gates-clk\";\n> -\t\t\treg = <0x01c20060 0x8>;\n> -\t\t\tclocks = <&ahb1>;\n> -\t\t\tclock-indices = <1>, <5>,\n> -\t\t\t\t        <6>, <8>, <9>,\n> -\t\t\t\t        <10>, <13>, <14>,\n> -\t\t\t\t\t<19>, <20>,\n> -\t\t\t\t\t<21>, <24>, <26>,\n> -\t\t\t\t\t<29>, <32>, <36>,\n> -\t\t\t\t\t<40>, <44>, <46>,\n> -\t\t\t\t\t<52>, <53>,\n> -\t\t\t\t\t<54>, <57>,\n> -\t\t\t\t\t<58>;\n> -\t\t\tclock-output-names = \"ahb1_mipidsi\", \"ahb1_ss\",\n> -\t\t\t\t\t\"ahb1_dma\",\"ahb1_mmc0\", \"ahb1_mmc1\",\n> -\t\t\t\t\t\"ahb1_mmc2\", \"ahb1_nand\", \"ahb1_sdram\",\n> -\t\t\t\t\t\"ahb1_hstimer\", \"ahb1_spi0\",\n> -\t\t\t\t\t\"ahb1_spi1\", \"ahb1_otg\", \"ahb1_ehci\",\n> -\t\t\t\t\t\"ahb1_ohci\", \"ahb1_ve\", \"ahb1_lcd\",\n> -\t\t\t\t\t\"ahb1_csi\", \"ahb1_be\",\t\"ahb1_fe\",\n> -\t\t\t\t\t\"ahb1_gpu\", \"ahb1_msgbox\",\n> -\t\t\t\t\t\"ahb1_spinlock\", \"ahb1_drc\",\n> -\t\t\t\t\t\"ahb1_sat\";\n> -\t\t};\n> -\n> -\t\tss_clk: clk@01c2009c {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun4i-a10-mod0-clk\";\n> -\t\t\treg = <0x01c2009c 0x4>;\n> -\t\t\tclocks = <&osc24M>, <&pll6 0>;\n> -\t\t\tclock-output-names = \"ss\";\n> -\t\t};\n> -\n> -\t\tmbus_clk: clk@01c2015c {\n> -\t\t\t#clock-cells = <0>;\n> -\t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n> -\t\t\treg = <0x01c2015c 0x4>;\n> -\t\t\tclocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>;\n> -\t\t\tclock-output-names = \"mbus\";\n> +\tsound: sound {\n> +\t\tcompatible = \"simple-audio-card\";\n> +\t\tsimple-audio-card,name = \"sun8i-a33-audio\";\n> +\t\tsimple-audio-card,format = \"i2s\";\n> +\t\tsimple-audio-card,frame-master = <&link_codec>;\n> +\t\tsimple-audio-card,bitclock-master = <&link_codec>;\n> +\t\tsimple-audio-card,mclk-fs = <512>;\n> +\t\tsimple-audio-card,aux-devs = <&codec_analog>;\n> +\t\tsimple-audio-card,routing =\n> +\t\t\t\"Left DAC\", \"AIF1 Slot 0 Left\",\n> +\t\t\t\"Right DAC\", \"AIF1 Slot 0 Right\";\n> +\t\tstatus = \"disabled\";\n> +\n> +\t\tsimple-audio-card,cpu {\n> +\t\t\tsound-dai = <&dai>;\n> +\t\t};\n> +\n> +\t\tlink_codec: simple-audio-card,codec {\n> +\t\t\tsound-dai = <&codec>;\n>   \t\t};\n>   \t};\n>   \n>   \tsoc@01c00000 {\n> +\t\ttcon0: lcd-controller@01c0c000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-a33-tcon\";\n> +\t\t\treg = <0x01c0c000 0x1000>;\n> +\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_LCD>,\n> +\t\t\t\t <&ccu CLK_LCD_CH0>;\n> +\t\t\tclock-names = \"ahb\",\n> +\t\t\t\t      \"tcon-ch0\";\n> +\t\t\tclock-output-names = \"tcon-pixel-clock\";\n> +\t\t\tresets = <&ccu RST_BUS_LCD>;\n> +\t\t\treset-names = \"lcd\";\n> +\t\t\tstatus = \"disabled\";\n> +\n> +\t\t\tports {\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\n> +\t\t\t\ttcon0_in: port@0 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <0>;\n> +\n> +\t\t\t\t\ttcon0_in_drc0: endpoint@0 {\n> +\t\t\t\t\t\treg = <0>;\n> +\t\t\t\t\t\tremote-endpoint = <&drc0_out_tcon0>;\n> +\t\t\t\t\t};\n> +\t\t\t\t};\n> +\n> +\t\t\t\ttcon0_out: port@1 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <1>;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\n>   \t\tcrypto: crypto-engine@01c15000 {\n>   \t\t\tcompatible = \"allwinner,sun4i-a10-crypto\";\n>   \t\t\treg = <0x01c15000 0x1000>;\n>   \t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tclocks = <&ahb1_gates 5>, <&ss_clk>;\n> +\t\t\tclocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;\n>   \t\t\tclock-names = \"ahb\", \"mod\";\n> -\t\t\tresets = <&ahb1_rst 5>;\n> +\t\t\tresets = <&ccu RST_BUS_SS>;\n>   \t\t\treset-names = \"ahb\";\n>   \t\t};\n>   \n> -\t\tusb_otg: usb@01c19000 {\n> -\t\t\tcompatible = \"allwinner,sun8i-a33-musb\";\n> -\t\t\treg = <0x01c19000 0x0400>;\n> -\t\t\tclocks = <&ahb1_gates 24>;\n> -\t\t\tresets = <&ahb1_rst 24>;\n> -\t\t\tinterrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;\n> -\t\t\tinterrupt-names = \"mc\";\n> -\t\t\tphys = <&usbphy 0>;\n> -\t\t\tphy-names = \"usb\";\n> -\t\t\textcon = <&usbphy 0>;\n> +\t\tdai: dai@01c22c00 {\n> +\t\t\t#sound-dai-cells = <0>;\n> +\t\t\tcompatible = \"allwinner,sun6i-a31-i2s\";\n> +\t\t\treg = <0x01c22c00 0x200>;\n> +\t\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;\n> +\t\t\tclock-names = \"apb\", \"mod\";\n> +\t\t\tresets = <&ccu RST_BUS_CODEC>;\n> +\t\t\tdmas = <&dma 15>, <&dma 15>;\n> +\t\t\tdma-names = \"rx\", \"tx\";\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tcodec: codec@01c22e00 {\n> +\t\t\t#sound-dai-cells = <0>;\n> +\t\t\tcompatible = \"allwinner,sun8i-a33-codec\";\n> +\t\t\treg = <0x01c22e00 0x400>;\n> +\t\t\tinterrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;\n> +\t\t\tclock-names = \"bus\", \"mod\";\n>   \t\t\tstatus = \"disabled\";\n>   \t\t};\n>   \n> -\t\tusbphy: phy@01c19400 {\n> -\t\t\tcompatible = \"allwinner,sun8i-a33-usb-phy\";\n> -\t\t\treg = <0x01c19400 0x14>,\n> -\t\t\t      <0x01c1a800 0x4>;\n> -\t\t\treg-names = \"phy_ctrl\",\n> -\t\t\t\t    \"pmu1\";\n> -\t\t\tclocks = <&usb_clk 8>,\n> -\t\t\t\t <&usb_clk 9>;\n> -\t\t\tclock-names = \"usb0_phy\",\n> -\t\t\t\t      \"usb1_phy\";\n> -\t\t\tresets = <&usb_clk 0>,\n> -\t\t\t\t <&usb_clk 1>;\n> -\t\t\treset-names = \"usb0_reset\",\n> -\t\t\t\t      \"usb1_reset\";\n> +\t\tths: ths@01c25000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-a33-ths\";\n> +\t\t\treg = <0x01c25000 0x100>;\n> +\t\t\t#thermal-sensor-cells = <0>;\n> +\t\t\t#io-channel-cells = <0>;\n> +\t\t};\n> +\n> +\t\tfe0: display-frontend@01e00000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-a33-display-frontend\";\n> +\t\t\treg = <0x01e00000 0x20000>;\n> +\t\t\tinterrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,\n> +\t\t\t\t <&ccu CLK_DRAM_DE_FE>;\n> +\t\t\tclock-names = \"ahb\", \"mod\",\n> +\t\t\t\t      \"ram\";\n> +\t\t\tresets = <&ccu RST_BUS_DE_FE>;\n>   \t\t\tstatus = \"disabled\";\n> -\t\t\t#phy-cells = <1>;\n> +\n> +\t\t\tports {\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\n> +\t\t\t\tfe0_out: port@1 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <1>;\n> +\n> +\t\t\t\t\tfe0_out_be0: endpoint@0 {\n> +\t\t\t\t\t\treg = <0>;\n> +\t\t\t\t\t\tremote-endpoint = <&be0_in_fe0>;\n> +\t\t\t\t\t};\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tbe0: display-backend@01e60000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-a33-display-backend\";\n> +\t\t\treg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;\n> +\t\t\treg-names = \"be\", \"sat\";\n> +\t\t\tinterrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,\n> +\t\t\t\t <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;\n> +\t\t\tclock-names = \"ahb\", \"mod\",\n> +\t\t\t\t      \"ram\", \"sat\";\n> +\t\t\tresets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;\n> +\t\t\treset-names = \"be\", \"sat\";\n> +\t\t\tassigned-clocks = <&ccu CLK_DE_BE>;\n> +\t\t\tassigned-clock-rates = <300000000>;\n> +\n> +\t\t\tports {\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\n> +\t\t\t\tbe0_in: port@0 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <0>;\n> +\n> +\t\t\t\t\tbe0_in_fe0: endpoint@0 {\n> +\t\t\t\t\t\treg = <0>;\n> +\t\t\t\t\t\tremote-endpoint = <&fe0_out_be0>;\n> +\t\t\t\t\t};\n> +\t\t\t\t};\n> +\n> +\t\t\t\tbe0_out: port@1 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <1>;\n> +\n> +\t\t\t\t\tbe0_out_drc0: endpoint@0 {\n> +\t\t\t\t\t\treg = <0>;\n> +\t\t\t\t\t\tremote-endpoint = <&drc0_in_be0>;\n> +\t\t\t\t\t};\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\n> +\t\tdrc0: drc@01e70000 {\n> +\t\t\tcompatible = \"allwinner,sun8i-a33-drc\";\n> +\t\t\treg = <0x01e70000 0x10000>;\n> +\t\t\tinterrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t\tclocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,\n> +\t\t\t\t <&ccu CLK_DRAM_DRC>;\n> +\t\t\tclock-names = \"ahb\", \"mod\", \"ram\";\n> +\t\t\tresets = <&ccu RST_BUS_DRC>;\n> +\n> +\t\t\tassigned-clocks = <&ccu CLK_DRC>;\n> +\t\t\tassigned-clock-rates = <300000000>;\n> +\n> +\t\t\tports {\n> +\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t#size-cells = <0>;\n> +\n> +\t\t\t\tdrc0_in: port@0 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <0>;\n> +\n> +\t\t\t\t\tdrc0_in_be0: endpoint@0 {\n> +\t\t\t\t\t\treg = <0>;\n> +\t\t\t\t\t\tremote-endpoint = <&be0_out_drc0>;\n> +\t\t\t\t\t};\n> +\t\t\t\t};\n> +\n> +\t\t\t\tdrc0_out: port@1 {\n> +\t\t\t\t\t#address-cells = <1>;\n> +\t\t\t\t\t#size-cells = <0>;\n> +\t\t\t\t\treg = <1>;\n> +\n> +\t\t\t\t\tdrc0_out_tcon0: endpoint@0 {\n> +\t\t\t\t\t\treg = <0>;\n> +\t\t\t\t\t\tremote-endpoint = <&tcon0_in_drc0>;\n> +\t\t\t\t\t};\n> +\t\t\t\t};\n> +\t\t\t};\n> +\t\t};\n> +\t};\n> +\n> +\tthermal-zones {\n> +\t\tcpu_thermal {\n> +\t\t\t/* milliseconds */\n> +\t\t\tpolling-delay-passive = <250>;\n> +\t\t\tpolling-delay = <1000>;\n> +\t\t\tthermal-sensors = <&ths>;\n> +\n> +\t\t\tcooling-maps {\n> +\t\t\t\tmap0 {\n> +\t\t\t\t\ttrip = <&cpu_alert0>;\n> +\t\t\t\t\tcooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n> +\t\t\t\t};\n> +\t\t\t\tmap1 {\n> +\t\t\t\t\ttrip = <&cpu_alert1>;\n> +\t\t\t\t\tcooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n> +\t\t\t\t};\n> +\n> +\t\t\t\tmap2 {\n> +\t\t\t\t\ttrip = <&gpu_alert0>;\n> +\t\t\t\t\tcooling-device = <&mali 1 THERMAL_NO_LIMIT>;\n> +\t\t\t\t};\n> +\n> +\t\t\t\tmap3 {\n> +\t\t\t\t\ttrip = <&gpu_alert1>;\n> +\t\t\t\t\tcooling-device = <&mali 2 THERMAL_NO_LIMIT>;\n> +\t\t\t\t};\n> +\t\t\t};\n> +\n> +\t\t\ttrips {\n> +\t\t\t\tcpu_alert0: cpu_alert0 {\n> +\t\t\t\t\t/* milliCelsius */\n> +\t\t\t\t\ttemperature = <75000>;\n> +\t\t\t\t\thysteresis = <2000>;\n> +\t\t\t\t\ttype = \"passive\";\n> +\t\t\t\t};\n> +\n> +\t\t\t\tgpu_alert0: gpu_alert0 {\n> +\t\t\t\t\t/* milliCelsius */\n> +\t\t\t\t\ttemperature = <85000>;\n> +\t\t\t\t\thysteresis = <2000>;\n> +\t\t\t\t\ttype = \"passive\";\n> +\t\t\t\t};\n> +\n> +\t\t\t\tcpu_alert1: cpu_alert1 {\n> +\t\t\t\t\t/* milliCelsius */\n> +\t\t\t\t\ttemperature = <90000>;\n> +\t\t\t\t\thysteresis = <2000>;\n> +\t\t\t\t\ttype = \"hot\";\n> +\t\t\t\t};\n> +\n> +\t\t\t\tgpu_alert1: gpu_alert1 {\n> +\t\t\t\t\t/* milliCelsius */\n> +\t\t\t\t\ttemperature = <95000>;\n> +\t\t\t\t\thysteresis = <2000>;\n> +\t\t\t\t\ttype = \"hot\";\n> +\t\t\t\t};\n> +\n> +\t\t\t\tcpu_crit: cpu_crit {\n> +\t\t\t\t\t/* milliCelsius */\n> +\t\t\t\t\ttemperature = <110000>;\n> +\t\t\t\t\thysteresis = <2000>;\n> +\t\t\t\t\ttype = \"critical\";\n> +\t\t\t\t};\n> +\t\t\t};\n>   \t\t};\n>   \t};\n>   };\n>   \n> +&ccu {\n> +\tcompatible = \"allwinner,sun8i-a33-ccu\";\n> +};\n> +\n> +&mali {\n> +\toperating-points-v2 = <&mali_opp_table>;\n> +};\n> +\n>   &pio {\n>   \tcompatible = \"allwinner,sun8i-a33-pinctrl\";\n>   \tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n>   \t\t     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n>   \n>   \tuart0_pins_b: uart0@1 {\n> -\t\tallwinner,pins = \"PB0\", \"PB1\";\n> -\t\tallwinner,function = \"uart0\";\n> -\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n> -\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n> +\t\tpins = \"PB0\", \"PB1\";\n> +\t\tfunction = \"uart0\";\n>   \t};\n>   \n>   };\n> +\n> +&usb_otg {\n> +\tcompatible = \"allwinner,sun8i-a33-musb\";\n> +};\n> +\n> +&usbphy {\n> +\tcompatible = \"allwinner,sun8i-a33-usb-phy\";\n> +\treg = <0x01c19400 0x14>, <0x01c1a800 0x4>;\n> +\treg-names = \"phy_ctrl\", \"pmu1\";\n> +};\n> diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h\n> new file mode 100644\n> index 000000000000..f8222b6b2cc3\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h\n> @@ -0,0 +1,127 @@\n> +/*\n> + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>\n> + *\n> + * This file is dual-licensed: you can use it either under the terms\n> + * of the GPL or the X11 license, at your option. Note that this dual\n> + * licensing only applies to this file, and not this project as a\n> + * whole.\n> + *\n> + *  a) This file is free software; you can redistribute it and/or\n> + *     modify it under the terms of the GNU General Public License as\n> + *     published by the Free Software Foundation; either version 2 of the\n> + *     License, or (at your option) any later version.\n> + *\n> + *     This file is distributed in the hope that it will be useful,\n> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n> + *     GNU General Public License for more details.\n> + *\n> + * Or, alternatively,\n> + *\n> + *  b) Permission is hereby granted, free of charge, to any person\n> + *     obtaining a copy of this software and associated documentation\n> + *     files (the \"Software\"), to deal in the Software without\n> + *     restriction, including without limitation the rights to use,\n> + *     copy, modify, merge, publish, distribute, sublicense, and/or\n> + *     sell copies of the Software, and to permit persons to whom the\n> + *     Software is furnished to do so, subject to the following\n> + *     conditions:\n> + *\n> + *     The above copyright notice and this permission notice shall be\n> + *     included in all copies or substantial portions of the Software.\n> + *\n> + *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n> + *     OTHER DEALINGS IN THE SOFTWARE.\n> + */\n> +\n> +#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_\n> +#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_\n> +\n> +#define CLK_CPUX\t\t18\n> +\n> +#define CLK_BUS_MIPI_DSI\t23\n> +#define CLK_BUS_SS\t\t24\n> +#define CLK_BUS_DMA\t\t25\n> +#define CLK_BUS_MMC0\t\t26\n> +#define CLK_BUS_MMC1\t\t27\n> +#define CLK_BUS_MMC2\t\t28\n> +#define CLK_BUS_NAND\t\t29\n> +#define CLK_BUS_DRAM\t\t30\n> +#define CLK_BUS_HSTIMER\t\t31\n> +#define CLK_BUS_SPI0\t\t32\n> +#define CLK_BUS_SPI1\t\t33\n> +#define CLK_BUS_OTG\t\t34\n> +#define CLK_BUS_EHCI\t\t35\n> +#define CLK_BUS_OHCI\t\t36\n> +#define CLK_BUS_VE\t\t37\n> +#define CLK_BUS_LCD\t\t38\n> +#define CLK_BUS_CSI\t\t39\n> +#define CLK_BUS_DE_BE\t\t40\n> +#define CLK_BUS_DE_FE\t\t41\n> +#define CLK_BUS_GPU\t\t42\n> +#define CLK_BUS_MSGBOX\t\t43\n> +#define CLK_BUS_SPINLOCK\t44\n> +#define CLK_BUS_DRC\t\t45\n> +#define CLK_BUS_SAT\t\t46\n> +#define CLK_BUS_CODEC\t\t47\n> +#define CLK_BUS_PIO\t\t48\n> +#define CLK_BUS_I2S0\t\t49\n> +#define CLK_BUS_I2S1\t\t50\n> +#define CLK_BUS_I2C0\t\t51\n> +#define CLK_BUS_I2C1\t\t52\n> +#define CLK_BUS_I2C2\t\t53\n> +#define CLK_BUS_UART0\t\t54\n> +#define CLK_BUS_UART1\t\t55\n> +#define CLK_BUS_UART2\t\t56\n> +#define CLK_BUS_UART3\t\t57\n> +#define CLK_BUS_UART4\t\t58\n> +#define CLK_NAND\t\t59\n> +#define CLK_MMC0\t\t60\n> +#define CLK_MMC0_SAMPLE\t\t61\n> +#define CLK_MMC0_OUTPUT\t\t62\n> +#define CLK_MMC1\t\t63\n> +#define CLK_MMC1_SAMPLE\t\t64\n> +#define CLK_MMC1_OUTPUT\t\t65\n> +#define CLK_MMC2\t\t66\n> +#define CLK_MMC2_SAMPLE\t\t67\n> +#define CLK_MMC2_OUTPUT\t\t68\n> +#define CLK_SS\t\t\t69\n> +#define CLK_SPI0\t\t70\n> +#define CLK_SPI1\t\t71\n> +#define CLK_I2S0\t\t72\n> +#define CLK_I2S1\t\t73\n> +#define CLK_USB_PHY0\t\t74\n> +#define CLK_USB_PHY1\t\t75\n> +#define CLK_USB_HSIC\t\t76\n> +#define CLK_USB_HSIC_12M\t77\n> +#define CLK_USB_OHCI\t\t78\n> +\n> +#define CLK_DRAM_VE\t\t80\n> +#define CLK_DRAM_CSI\t\t81\n> +#define CLK_DRAM_DRC\t\t82\n> +#define CLK_DRAM_DE_FE\t\t83\n> +#define CLK_DRAM_DE_BE\t\t84\n> +#define CLK_DE_BE\t\t85\n> +#define CLK_DE_FE\t\t86\n> +#define CLK_LCD_CH0\t\t87\n> +#define CLK_LCD_CH1\t\t88\n> +#define CLK_CSI_SCLK\t\t89\n> +#define CLK_CSI_MCLK\t\t90\n> +#define CLK_VE\t\t\t91\n> +#define CLK_AC_DIG\t\t92\n> +#define CLK_AC_DIG_4X\t\t93\n> +#define CLK_AVS\t\t\t94\n> +\n> +#define CLK_DSI_SCLK\t\t96\n> +#define CLK_DSI_DPHY\t\t97\n> +#define CLK_DRC\t\t\t98\n> +#define CLK_GPU\t\t\t99\n> +#define CLK_ATS\t\t\t100\n> +\n> +#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */\n> diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h\n> new file mode 100644\n> index 000000000000..6121f2b0cd0a\n> --- /dev/null\n> +++ b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h\n> @@ -0,0 +1,87 @@\n> +/*\n> + * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>\n> + *\n> + * This file is dual-licensed: you can use it either under the terms\n> + * of the GPL or the X11 license, at your option. Note that this dual\n> + * licensing only applies to this file, and not this project as a\n> + * whole.\n> + *\n> + *  a) This file is free software; you can redistribute it and/or\n> + *     modify it under the terms of the GNU General Public License as\n> + *     published by the Free Software Foundation; either version 2 of the\n> + *     License, or (at your option) any later version.\n> + *\n> + *     This file is distributed in the hope that it will be useful,\n> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of\n> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n> + *     GNU General Public License for more details.\n> + *\n> + * Or, alternatively,\n> + *\n> + *  b) Permission is hereby granted, free of charge, to any person\n> + *     obtaining a copy of this software and associated documentation\n> + *     files (the \"Software\"), to deal in the Software without\n> + *     restriction, including without limitation the rights to use,\n> + *     copy, modify, merge, publish, distribute, sublicense, and/or\n> + *     sell copies of the Software, and to permit persons to whom the\n> + *     Software is furnished to do so, subject to the following\n> + *     conditions:\n> + *\n> + *     The above copyright notice and this permission notice shall be\n> + *     included in all copies or substantial portions of the Software.\n> + *\n> + *     THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES\n> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\n> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT\n> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,\n> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING\n> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR\n> + *     OTHER DEALINGS IN THE SOFTWARE.\n> + */\nShouldn't we use the SPDX license header?\n\nTom what is the policy for importing dts[i] files from Linux kernel?\n\n> +\n> +#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_\n> +#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_\n> +\n> +#define RST_USB_PHY0\t\t0\n> +#define RST_USB_PHY1\t\t1\n> +#define RST_USB_HSIC\t\t2\n> +#define RST_MBUS\t\t3\n> +#define RST_BUS_MIPI_DSI\t4\n> +#define RST_BUS_SS\t\t5\n> +#define RST_BUS_DMA\t\t6\n> +#define RST_BUS_MMC0\t\t7\n> +#define RST_BUS_MMC1\t\t8\n> +#define RST_BUS_MMC2\t\t9\n> +#define RST_BUS_NAND\t\t10\n> +#define RST_BUS_DRAM\t\t11\n> +#define RST_BUS_HSTIMER\t\t12\n> +#define RST_BUS_SPI0\t\t13\n> +#define RST_BUS_SPI1\t\t14\n> +#define RST_BUS_OTG\t\t15\n> +#define RST_BUS_EHCI\t\t16\n> +#define RST_BUS_OHCI\t\t17\n> +#define RST_BUS_VE\t\t18\n> +#define RST_BUS_LCD\t\t19\n> +#define RST_BUS_CSI\t\t20\n> +#define RST_BUS_DE_BE\t\t21\n> +#define RST_BUS_DE_FE\t\t22\n> +#define RST_BUS_GPU\t\t23\n> +#define RST_BUS_MSGBOX\t\t24\n> +#define RST_BUS_SPINLOCK\t25\n> +#define RST_BUS_DRC\t\t26\n> +#define RST_BUS_SAT\t\t27\n> +#define RST_BUS_LVDS\t\t28\n> +#define RST_BUS_CODEC\t\t29\n> +#define RST_BUS_I2S0\t\t30\n> +#define RST_BUS_I2S1\t\t31\n> +#define RST_BUS_I2C0\t\t32\n> +#define RST_BUS_I2C1\t\t33\n> +#define RST_BUS_I2C2\t\t34\n> +#define RST_BUS_UART0\t\t35\n> +#define RST_BUS_UART1\t\t36\n> +#define RST_BUS_UART2\t\t37\n> +#define RST_BUS_UART3\t\t38\n> +#define RST_BUS_UART4\t\t39\n> +\n> +#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */\n> \n\nReviewed-by: Łukasz Majewski <lukma@denx.de>","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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