[{"id":1767891,"web_url":"http://patchwork.ozlabs.org/comment/1767891/","msgid":"<76747133-5540-f266-d81b-fb9803e6b1c9@foss.arm.com>","list_archive_url":null,"date":"2017-09-13T13:36:37","subject":"Re: [AArch64, patch] Refactor of aarch64-ldpstp.md","submitter":{"id":71950,"url":"http://patchwork.ozlabs.org/api/people/71950/","name":"Jackson Woodruff","email":"jackson.woodruff@foss.arm.com"},"content":"Hi,\n\nSince I rebased the patch that this is based on, I have also rebased \nthis patch.\n\nJackson.\n\nOn 09/12/2017 07:15 PM, Jackson Woodruff wrote:\n> Hi all,\n> \n> This patch removes a lot of duplicated code in aarch64-ldpstp.md.\n> \n> The patterns that did not previously generate a base register now\n> do not check for aarch64_mem_pair_operand in the pattern. This has\n> been extracted to a check in aarch64_operands_ok_for_ldpstp.\n> \n> All patterns in the file used to have explicit switching code to\n> swap loads and stores that were in the wrong order.\n> \n> This has been extracted into aarch64_ldp_str_operands\n> and aarch64_gen_adjusted_ldp_stp.\n> \n> This patch is based on my patch here: \n> https://gcc.gnu.org/ml/gcc-patches/2017-09/msg00346.html so should go in \n> after it.\n> \n> \n> Bootstrap and regtest OK on AArch64.\n> \n> OK for trunk?\n> \n> Jackson.\n> \n> gcc/\n> \n> 2017-09-07  Jackson Woodruff  <jackson.woodruff@arm.com>\n> \n>      * config/aarch64/aarch64-ldpstp.md: Replace uses of\n>      aarch64_mem_pair_operand with memory_operand and delete\n>      operand swapping code.\n>      * config/aarch64/aarch64.c (aarch64_operands_ok_for_ldpstp):\n>      Add check for legitimate_address.\n>      (aarch64_gen_adjusted_ldpstp): Add swap.\n>      (aarch64_swap_ldrstr_operands): New.\n>      * config/aarch64/aarch64-protos.h: Add\n>      aarch64_swap_ldrstr_operands.\ndiff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md\nindex 14e860d258e548d4118d957675f8bdbb74615337..126bb702f6399d13ab2dc6c8b99bcbbf3b3a7516 100644\n--- a/gcc/config/aarch64/aarch64-ldpstp.md\n+++ b/gcc/config/aarch64/aarch64-ldpstp.md\n@@ -20,26 +20,18 @@\n \n (define_peephole2\n   [(set (match_operand:GPI 0 \"register_operand\" \"\")\n-\t(match_operand:GPI 1 \"aarch64_mem_pair_operand\" \"\"))\n+\t(match_operand:GPI 1 \"memory_operand\" \"\"))\n    (set (match_operand:GPI 2 \"register_operand\" \"\")\n \t(match_operand:GPI 3 \"memory_operand\" \"\"))]\n   \"aarch64_operands_ok_for_ldpstp (operands, true, <MODE>mode)\"\n   [(parallel [(set (match_dup 0) (match_dup 1))\n \t      (set (match_dup 2) (match_dup 3))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n-  [(set (match_operand:GPI 0 \"aarch64_mem_pair_operand\" \"\")\n+  [(set (match_operand:GPI 0 \"memory_operand\" \"\")\n \t(match_operand:GPI 1 \"aarch64_reg_or_zero\" \"\"))\n    (set (match_operand:GPI 2 \"memory_operand\" \"\")\n \t(match_operand:GPI 3 \"aarch64_reg_or_zero\" \"\"))]\n@@ -47,39 +39,23 @@\n   [(parallel [(set (match_dup 0) (match_dup 1))\n \t      (set (match_dup 2) (match_dup 3))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[0], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[2], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 0);\n })\n \n (define_peephole2\n   [(set (match_operand:GPF 0 \"register_operand\" \"\")\n-\t(match_operand:GPF 1 \"aarch64_mem_pair_operand\" \"\"))\n+\t(match_operand:GPF 1 \"memory_operand\" \"\"))\n    (set (match_operand:GPF 2 \"register_operand\" \"\")\n \t(match_operand:GPF 3 \"memory_operand\" \"\"))]\n   \"aarch64_operands_ok_for_ldpstp (operands, true, <MODE>mode)\"\n   [(parallel [(set (match_dup 0) (match_dup 1))\n \t      (set (match_dup 2) (match_dup 3))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n-  [(set (match_operand:GPF 0 \"aarch64_mem_pair_operand\" \"\")\n+  [(set (match_operand:GPF 0 \"memory_operand\" \"\")\n \t(match_operand:GPF 1 \"aarch64_reg_or_fp_zero\" \"\"))\n    (set (match_operand:GPF 2 \"memory_operand\" \"\")\n \t(match_operand:GPF 3 \"aarch64_reg_or_fp_zero\" \"\"))]\n@@ -87,39 +63,23 @@\n   [(parallel [(set (match_dup 0) (match_dup 1))\n \t      (set (match_dup 2) (match_dup 3))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[0], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[2], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 0);\n })\n \n (define_peephole2\n   [(set (match_operand:DREG 0 \"register_operand\" \"\")\n-\t(match_operand:DREG 1 \"aarch64_mem_pair_operand\" \"\"))\n+\t(match_operand:DREG 1 \"memory_operand\" \"\"))\n    (set (match_operand:DREG2 2 \"register_operand\" \"\")\n \t(match_operand:DREG2 3 \"memory_operand\" \"\"))]\n   \"aarch64_operands_ok_for_ldpstp (operands, true, <MODE>mode)\"\n   [(parallel [(set (match_dup 0) (match_dup 1))\n \t      (set (match_dup 2) (match_dup 3))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n-  [(set (match_operand:DREG 0 \"aarch64_mem_pair_operand\" \"\")\n+  [(set (match_operand:DREG 0 \"memory_operand\" \"\")\n \t(match_operand:DREG 1 \"register_operand\" \"\"))\n    (set (match_operand:DREG2 2 \"memory_operand\" \"\")\n \t(match_operand:DREG2 3 \"register_operand\" \"\"))]\n@@ -128,57 +88,33 @@\n   [(parallel [(set (match_dup 0) (match_dup 1))\n \t      (set (match_dup 2) (match_dup 3))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[0], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[2], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 0);\n })\n \n ;; Handle sign/zero extended consecutive load/store.\n \n (define_peephole2\n   [(set (match_operand:DI 0 \"register_operand\" \"\")\n-\t(sign_extend:DI (match_operand:SI 1 \"aarch64_mem_pair_operand\" \"\")))\n+\t(sign_extend:DI (match_operand:SI 1 \"memory_operand\" \"\")))\n    (set (match_operand:DI 2 \"register_operand\" \"\")\n \t(sign_extend:DI (match_operand:SI 3 \"memory_operand\" \"\")))]\n   \"aarch64_operands_ok_for_ldpstp (operands, true, SImode)\"\n   [(parallel [(set (match_dup 0) (sign_extend:DI (match_dup 1)))\n \t      (set (match_dup 2) (sign_extend:DI (match_dup 3)))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n (define_peephole2\n   [(set (match_operand:DI 0 \"register_operand\" \"\")\n-\t(zero_extend:DI (match_operand:SI 1 \"aarch64_mem_pair_operand\" \"\")))\n+\t(zero_extend:DI (match_operand:SI 1 \"memory_operand\" \"\")))\n    (set (match_operand:DI 2 \"register_operand\" \"\")\n \t(zero_extend:DI (match_operand:SI 3 \"memory_operand\" \"\")))]\n   \"aarch64_operands_ok_for_ldpstp (operands, true, SImode)\"\n   [(parallel [(set (match_dup 0) (zero_extend:DI (match_dup 1)))\n \t      (set (match_dup 2) (zero_extend:DI (match_dup 3)))])]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[2]);\n-      std::swap (operands[1], operands[3]);\n-    }\n+  aarch64_swap_ldrstr_operands (operands, 1);\n })\n \n ;; Handle storing of a floating point zero.\n@@ -186,7 +122,7 @@\n ;; as aarch64_operands_ok_for_ldpstp checks that the modes are\n ;; compatible.\n (define_peephole2\n-  [(set (match_operand:DSX 0 \"aarch64_mem_pair_operand\" \"\")\n+  [(set (match_operand:DSX 0 \"memory_operand\" \"\")\n \t(match_operand:DSX 1 \"aarch64_reg_zero_or_fp_zero\" \"\"))\n    (set (match_operand:<FCVT_TARGET> 2 \"memory_operand\" \"\")\n \t(match_operand:<FCVT_TARGET> 3 \"aarch64_reg_zero_or_fp_zero\" \"\"))]\n@@ -224,18 +160,6 @@\n   \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, <MODE>mode)\"\n   [(const_int 0)]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[6]);\n-      std::swap (operands[1], operands[7]);\n-      std::swap (operands[2], operands[4]);\n-      std::swap (operands[3], operands[5]);\n-    }\n-\n   if (aarch64_gen_adjusted_ldpstp (operands, true, <MODE>mode, UNKNOWN))\n     DONE;\n   else\n@@ -256,18 +180,6 @@\n   \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, <MODE>mode)\"\n   [(const_int 0)]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[6]);\n-      std::swap (operands[1], operands[7]);\n-      std::swap (operands[2], operands[4]);\n-      std::swap (operands[3], operands[5]);\n-    }\n-\n   if (aarch64_gen_adjusted_ldpstp (operands, true, <MODE>mode, UNKNOWN))\n     DONE;\n   else\n@@ -288,18 +200,6 @@\n   \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, SImode)\"\n   [(const_int 0)]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[6]);\n-      std::swap (operands[1], operands[7]);\n-      std::swap (operands[2], operands[4]);\n-      std::swap (operands[3], operands[5]);\n-    }\n-\n   if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, SIGN_EXTEND))\n     DONE;\n   else\n@@ -320,18 +220,6 @@\n   \"aarch64_operands_adjust_ok_for_ldpstp (operands, true, SImode)\"\n   [(const_int 0)]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[1], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[3], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[6]);\n-      std::swap (operands[1], operands[7]);\n-      std::swap (operands[2], operands[4]);\n-      std::swap (operands[3], operands[5]);\n-    }\n-\n   if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, ZERO_EXTEND))\n     DONE;\n   else\n@@ -352,18 +240,6 @@\n   \"aarch64_operands_adjust_ok_for_ldpstp (operands, false, <MODE>mode)\"\n   [(const_int 0)]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[0], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[2], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[6]);\n-      std::swap (operands[1], operands[7]);\n-      std::swap (operands[2], operands[4]);\n-      std::swap (operands[3], operands[5]);\n-    }\n-\n   if (aarch64_gen_adjusted_ldpstp (operands, false, <MODE>mode, UNKNOWN))\n     DONE;\n   else\n@@ -384,18 +260,6 @@\n   \"aarch64_operands_adjust_ok_for_ldpstp (operands, false, <MODE>mode)\"\n   [(const_int 0)]\n {\n-  rtx base, offset_1, offset_2;\n-\n-  extract_base_offset_in_addr (operands[0], &base, &offset_1);\n-  extract_base_offset_in_addr (operands[2], &base, &offset_2);\n-  if (INTVAL (offset_1) > INTVAL (offset_2))\n-    {\n-      std::swap (operands[0], operands[6]);\n-      std::swap (operands[1], operands[7]);\n-      std::swap (operands[2], operands[4]);\n-      std::swap (operands[3], operands[5]);\n-    }\n-\n   if (aarch64_gen_adjusted_ldpstp (operands, false, <MODE>mode, UNKNOWN))\n     DONE;\n   else\ndiff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex e67c2ed5e80a2e4f4858cfcd40573efd2a8a4416..2cee3ff5b695db2fecd73471c398408e4657b8ca 100644\n--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -469,6 +469,7 @@ int aarch64_ccmp_mode_to_code (machine_mode mode);\n bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);\n bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);\n bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);\n+void aarch64_swap_ldrstr_operands (rtx *, bool);\n \n extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,\n \t\t\t\t\t      tree, HOST_WIDE_INT);\ndiff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c\nindex ea2ff88f91a18b3fcd43bd0dcafd9ebdcc0b2366..4c5ed9610cb8bbb337bbfcb9260d7fd227c68ce8 100644\n--- a/gcc/config/aarch64/aarch64.c\n+++ b/gcc/config/aarch64/aarch64.c\n@@ -14770,9 +14770,18 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n \n       /* In increasing order, the last load can clobber the address.  */\n       if (offval_1 > offval_2 && reg_mentioned_p (reg_2, mem_2))\n-      return false;\n+\treturn false;\n     }\n \n+  /* One of the memory accesses must be a mempair operand.\n+     If it is not the first one, they need to be swapped by the\n+     peephole.  */\n+  if (!(aarch64_legitimate_address_p (GET_MODE (mem_1),\n+\t\t\t\t      XEXP (mem_1, 0), PARALLEL, 0)\n+\t|| aarch64_legitimate_address_p (GET_MODE (mem_2),\n+\t\t\t\t\t XEXP (mem_2, 0), PARALLEL, 0)))\n+    return false;\n+\n   if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))\n     rclass_1 = FP_REGS;\n   else\n@@ -14790,6 +14799,40 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,\n   return true;\n }\n \n+/* Given OPERANDS of consecutive load/store that can be merged,\n+   swap them if they are not in ascending order.  */\n+void\n+aarch64_swap_ldrstr_operands (rtx* operands, bool load)\n+{\n+  rtx mem_1, mem_2, base_1, base_2, offset_1, offset_2;\n+  HOST_WIDE_INT offval_1, offval_2;\n+\n+  if (load)\n+    {\n+      mem_1 = operands[1];\n+      mem_2 = operands[3];\n+    }\n+  else\n+    {\n+      mem_1 = operands[0];\n+      mem_2 = operands[2];\n+    }\n+\n+  extract_base_offset_in_addr (mem_1, &base_1, &offset_1);\n+  extract_base_offset_in_addr (mem_2, &base_2, &offset_2);\n+\n+  offval_1 = INTVAL (offset_1);\n+  offval_2 = INTVAL (offset_2);\n+\n+  if (offval_1 > offval_2)\n+    {\n+      /* Irrespective of whether this is a load or a store,\n+\t we do the same swap.  */\n+      std::swap (operands[0], operands[2]);\n+      std::swap (operands[1], operands[3]);\n+    }\n+}\n+\n /* Given OPERANDS of consecutive load/store, check if we can merge\n    them into ldp/stp by adjusting the offset.  LOAD is true if they\n    are load instructions.  MODE is the mode of memory operands.\n@@ -14949,7 +14992,7 @@ bool\n aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,\n \t\t\t     scalar_mode mode, RTX_CODE code)\n {\n-  rtx base, offset, t1, t2;\n+  rtx base, offset_1, offset_2, t1, t2;\n   rtx mem_1, mem_2, mem_3, mem_4;\n   HOST_WIDE_INT off_val, abs_off, adj_off, new_off, stp_off_limit, msize;\n \n@@ -14969,13 +15012,24 @@ aarch64_gen_adjusted_ldpstp (rtx *operands, bool load,\n       gcc_assert (code == UNKNOWN);\n     }\n \n-  extract_base_offset_in_addr (mem_1, &base, &offset);\n-  gcc_assert (base != NULL_RTX && offset != NULL_RTX);\n+  extract_base_offset_in_addr (mem_1, &base, &offset_1);\n+  extract_base_offset_in_addr (mem_2, &base, &offset_2);\n+  gcc_assert (base != NULL_RTX && offset_1 != NULL_RTX\n+\t      && offset_2 != NULL_RTX);\n+\n+  if (INTVAL (offset_1) > INTVAL (offset_2))\n+    {\n+      std::swap (operands[0], operands[6]);\n+      std::swap (operands[1], operands[7]);\n+      std::swap (operands[2], operands[4]);\n+      std::swap (operands[3], operands[5]);\n+    }\n+\n \n   /* Adjust offset thus it can fit in ldp/stp instruction.  */\n   msize = GET_MODE_SIZE (mode);\n   stp_off_limit = msize * 0x40;\n-  off_val = INTVAL (offset);\n+  off_val = INTVAL (offset_1);\n   abs_off = (off_val < 0) ? -off_val : off_val;\n   new_off = abs_off % stp_off_limit;\n   adj_off = abs_off - new_off;","headers":{"Return-Path":"<gcc-patches-return-462034-incoming=patchwork.ozlabs.org@gcc.gnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462034-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"dwbw6Nn/\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsjPm3ZVjz9s4s\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 23:37:00 +1000 (AEST)","(qmail 27488 invoked by alias); 13 Sep 2017 13:36:44 -0000","(qmail 26830 invoked by uid 89); 13 Sep 2017 13:36:43 -0000","from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by\n\tsourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 13 Sep 2017 13:36:40 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\t9FA6C15A2; Wed, 13 Sep 2017 06:36:39 -0700 (PDT)","from [10.2.206.195] (e112997-lin.cambridge.arm.com\n\t[10.2.206.195])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id D52553F58C; Wed, 13 Sep 2017 06:36:38 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:from:to:references:message-id:date:mime-version\n\t:in-reply-to:content-type; q=dns; s=default; b=Fdh8IJx4Uf5FtlWv7\n\tJEjnH7VDls5/6QhxYouPjs44YqLHQ7umt012xhGnkXh2QyqbnznWvF+9LIk+bQx/\n\tRgEp+xpWgz+p+6Uj+i93wurYypn2InR8vjAYwN+la46I/xQkMmqDs9stoac6NKan\n\t/TY9xGL+r3MD9nu8CwWjxKbqd4=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:subject:from:to:references:message-id:date:mime-version\n\t:in-reply-to:content-type; s=default; bh=mpLPt1ediSiako198WW78pY\n\ti5G4=; b=dwbw6Nn/c7ygHDlqkoMHNk5yb7SKUGyUo7isHMszELxQ7/aTYYCzi1k\n\thHVTu9zZT7xGmzQmkLBTrvKJcD1pcKLE1szu0BpFq21U1b5g53QD1UfZtlzSvPzC\n\tPauUDHGTGWf3msR3xU1HihcaGizUfp6JLigFwIh0NtGvQlUKlTYQ=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"<gcc-patches.gcc.gnu.org>","List-Unsubscribe":"<mailto:gcc-patches-unsubscribe-incoming=patchwork.ozlabs.org@gcc.gnu.org>","List-Archive":"<http://gcc.gnu.org/ml/gcc-patches/>","List-Post":"<mailto:gcc-patches@gcc.gnu.org>","List-Help":"<mailto:gcc-patches-help@gcc.gnu.org>","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-20.5 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, MEDICAL_SUBJECT,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Subject":"Re: [AArch64, patch] Refactor of aarch64-ldpstp.md","From":"Jackson Woodruff <jackson.woodruff@foss.arm.com>","To":"GCC Patches <gcc-patches@gcc.gnu.org>,\n\tJames Greenhalgh <James.Greenhalgh@arm.com>,\n\tRichard Earnshaw <Richard.Earnshaw@arm.com>","References":"<f9eac5a4-0567-4da8-8eb7-803a5d6e8324@foss.arm.com>","Message-ID":"<76747133-5540-f266-d81b-fb9803e6b1c9@foss.arm.com>","Date":"Wed, 13 Sep 2017 14:36:37 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:52.0) Gecko/20100101 Thunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<f9eac5a4-0567-4da8-8eb7-803a5d6e8324@foss.arm.com>","Content-Type":"multipart/mixed;\n\tboundary=\"------------5B0227390222DCC1C49236BB\"","X-IsSubscribed":"yes"}}]