[{"id":1775654,"web_url":"http://patchwork.ozlabs.org/comment/1775654/","msgid":"<47540beb-5bfa-9d18-4c42-a6d1ee63e62d@denx.de>","list_archive_url":null,"date":"2017-09-26T15:57:44","subject":"Re: [U-Boot] [PATCH] mtd: cfi: Add support for status register\n\tpolling","submitter":{"id":13,"url":"http://patchwork.ozlabs.org/api/people/13/","name":"Stefan Roese","email":"sr@denx.de"},"content":"On 12.09.2017 19:09, Marek Vasut wrote:\n> The status register is optional in the AMD command sets, but it's\n> presence can be checked by reading out CFI table entry 0xc bit 0.\n> If the register is present, prefer using it's bit 7 to determine\n> if the flash is busy over reading the flash ; this is needed ie.\n> on Hyperflash memories.\n> \n> Signed-off-by: Marek Vasut \n\nApplied to u-boot-cfi-flash/master.\n\nThanks,\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1lxK2Zq4z9t49\n\tfor ;\n\tWed, 27 Sep 2017 01:58:45 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 1162EC21F02; Tue, 26 Sep 2017 15:58:26 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9BB8BC21F01;\n\tTue, 26 Sep 2017 15:58:24 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid D2990C21E32; Tue, 26 Sep 2017 15:57:49 +0000 (UTC)","from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212])\n\tby lists.denx.de (Postfix) with ESMTPS id F2515C21E68\n\tfor ; Tue, 26 Sep 2017 15:57:46 +0000 (UTC)","from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mx1.mailbox.org (Postfix) with ESMTPS id BF11246AB1;\n\tTue, 26 Sep 2017 17:57:46 +0200 (CEST)","from smtp1.mailbox.org ([80.241.60.240])\n\tby spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de\n\t[80.241.56.116]) (amavisd-new, port 10030)\n\twith ESMTP id WbviJcswFX1K; Tue, 26 Sep 2017 17:57:44 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-Virus-Scanned":"amavisd-new at heinlein-support.de","To":"Marek Vasut , u-boot@lists.denx.de","References":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>","From":"Stefan Roese ","Message-ID":"<47540beb-5bfa-9d18-4c42-a6d1ee63e62d@denx.de>","Date":"Tue, 26 Sep 2017 17:57:44 +0200","MIME-Version":"1.0","In-Reply-To":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>","Content-Language":"en-US","Cc":"Marek Vasut ","Subject":"Re: [U-Boot] [PATCH] mtd: cfi: Add support for status register\n\tpolling","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806532,"web_url":"http://patchwork.ozlabs.org/comment/1806532/","msgid":"","list_archive_url":null,"date":"2017-11-17T16:43:57","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"On 09/12/2017 10:09 AM, Marek Vasut wrote:\n> The status register is optional in the AMD command sets, but it's\n> presence can be checked by reading out CFI table entry 0xc bit 0.\n> If the register is present, prefer using it's bit 7 to determine\n> if the flash is busy over reading the flash ; this is needed ie.\n> on Hyperflash memories.\n> \n> Signed-off-by: Marek Vasut \n> ---\n\nMarek,\n\nSome of our boards failed. I traced to this commit. Reverting this\ncommit fixes the issue. I happen to have two boards with slightly\ndifferent flash chip. One works and the other doesn't.\n\nThe working board has\n\n=> fli\n\nBank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors\n AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801\n Erase timeout: 2048 ms, write timeout: 1 ms\n Buffer write timeout: 3 ms, buffer size: 512 bytes\n\nThe failing board has\n\n=> fli\n\nBank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors\n AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801\n Erase timeout: 4096 ms, write timeout: 1 ms\n Buffer write timeout: 3 ms, buffer size: 64 bytes\n\nCan you investigate?\n\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"trScY2GO\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806647,"web_url":"http://patchwork.ozlabs.org/comment/1806647/","msgid":"<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>","list_archive_url":null,"date":"2017-11-17T19:02:55","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 11/17/2017 05:43 PM, York Sun wrote:\n> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>> The status register is optional in the AMD command sets, but it's\n>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>> If the register is present, prefer using it's bit 7 to determine\n>> if the flash is busy over reading the flash ; this is needed ie.\n>> on Hyperflash memories.\n>>\n>> Signed-off-by: Marek Vasut \n>> ---\n> \n> Marek,\n> \n> Some of our boards failed. I traced to this commit. Reverting this\n> commit fixes the issue. I happen to have two boards with slightly\n> different flash chip. One works and the other doesn't.\n\nI can't since I don't have the board with such a chip ...\nWhich chip is that ? Mine is Spansion S25KL256 hyperflash.\n\n> The working board has\n> \n> => fli\n> \n> Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors\n> AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801\n> Erase timeout: 2048 ms, write timeout: 1 ms\n> Buffer write timeout: 3 ms, buffer size: 512 bytes\n> \n> The failing board has\n> \n> => fli\n> \n> Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors\n> AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801\n> Erase timeout: 4096 ms, write timeout: 1 ms\n> Buffer write timeout: 3 ms, buffer size: 64 bytes\n> \n> Can you investigate?\n> \n> York\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"B4TXHVle\"; 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\n\tFri, 17 Nov 2017 11:02:57 -0800 (PST)","To":"York Sun ,\n\t\"u-boot@lists.denx.de\" ","References":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>\n\t","From":"Marek Vasut ","Message-ID":"<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>","Date":"Fri, 17 Nov 2017 20:02:55 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","Cc":"Priyanka Jain , Stefan Roese ,\n\tMarek Vasut ","Subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806649,"web_url":"http://patchwork.ozlabs.org/comment/1806649/","msgid":"<48035e40-b6a0-e55c-13f9-df7830e5dd35@gmail.com>","list_archive_url":null,"date":"2017-11-17T19:04:07","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 11/17/2017 08:02 PM, Marek Vasut wrote:\n> On 11/17/2017 05:43 PM, York Sun wrote:\n>> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>>> The status register is optional in the AMD command sets, but it's\n>>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>>> If the register is present, prefer using it's bit 7 to determine\n>>> if the flash is busy over reading the flash ; this is needed ie.\n>>> on Hyperflash memories.\n>>>\n>>> Signed-off-by: Marek Vasut \n>>> ---\n>>\n>> Marek,\n>>\n>> Some of our boards failed. I traced to this commit. Reverting this\n>> commit fixes the issue. I happen to have two boards with slightly\n>> different flash chip. One works and the other doesn't.\n> \n> I can't since I don't have the board with such a chip ...\n> Which chip is that ? Mine is Spansion S25KL256 hyperflash.\n\nS26KL256S (26 instead of 25), sorry.\n\n> \n>> The working board has\n>>\n>> => fli\n>>\n>> Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors\n>> AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801\n>> Erase timeout: 2048 ms, write timeout: 1 ms\n>> Buffer write timeout: 3 ms, buffer size: 512 bytes\n>>\n>> The failing board has\n>>\n>> => fli\n>>\n>> Bank # 1: CFI conformant flash (16 x 16) Size: 128 MB in 1024 Sectors\n>> AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2801\n>> Erase timeout: 4096 ms, write timeout: 1 ms\n>> Buffer write timeout: 3 ms, buffer size: 64 bytes\n>>\n>> Can you investigate?\n>>\n>> York\n>>\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"WPQ9pIL7\"; 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\n\tFri, 17 Nov 2017 11:04:10 -0800 (PST)","To":"York Sun ,\n\t\"u-boot@lists.denx.de\" ","References":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>\n\t\n\t<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>","From":"Marek Vasut ","Message-ID":"<48035e40-b6a0-e55c-13f9-df7830e5dd35@gmail.com>","Date":"Fri, 17 Nov 2017 20:04:07 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>","Content-Language":"en-US","Cc":"Priyanka Jain , Stefan Roese ","Subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806673,"web_url":"http://patchwork.ozlabs.org/comment/1806673/","msgid":"<7C559172-9E9C-4886-B6CD-B6D7136C2AD5@nxp.com>","list_archive_url":null,"date":"2017-11-17T19:48:43","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"On Nov 17, 2017, at 11:04, Marek Vasut > wrote:\r\n\r\nOn 11/17/2017 08:02 PM, Marek Vasut wrote:\r\nOn 11/17/2017 05:43 PM, York Sun wrote:\r\nOn 09/12/2017 10:09 AM, Marek Vasut wrote:\r\nThe status register is optional in the AMD command sets, but it's\r\npresence can be checked by reading out CFI table entry 0xc bit 0.\r\nIf the register is present, prefer using it's bit 7 to determine\r\nif the flash is busy over reading the flash ; this is needed ie.\r\non Hyperflash memories.\r\n\r\nSigned-off-by: Marek Vasut >\r\n---\r\n\r\nMarek,\r\n\r\nSome of our boards failed. I traced to this commit. Reverting this\r\ncommit fixes the issue. I happen to have two boards with slightly\r\ndifferent flash chip. One works and the other doesn't.\r\n\r\nI can't since I don't have the board with such a chip ...\r\nWhich chip is that ? Mine is Spansion S25KL256 hyperflash.\r\n\r\nS26KL256S (26 instead of 25), sorry.\r\n\r\nI have to wait for the team to confirm. The board is remote to me.\r\n\r\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"B0tlCz9l\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; "],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3ydpZy25Ykz9rvt\n\tfor ;\n\tSat, 18 Nov 2017 06:48:56 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 9DB39C21DDB; Fri, 17 Nov 2017 19:48:51 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 9E2C1C21D76;\n\tFri, 17 Nov 2017 19:48:48 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid B9FB9C21C73; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806715,"web_url":"http://patchwork.ozlabs.org/comment/1806715/","msgid":"","list_archive_url":null,"date":"2017-11-17T20:59:08","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"On 11/17/2017 11:04 AM, Marek Vasut wrote:\n> On 11/17/2017 08:02 PM, Marek Vasut wrote:\n>> On 11/17/2017 05:43 PM, York Sun wrote:\n>>> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>>>> The status register is optional in the AMD command sets, but it's\n>>>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>>>> If the register is present, prefer using it's bit 7 to determine\n>>>> if the flash is busy over reading the flash ; this is needed ie.\n>>>> on Hyperflash memories.\n>>>>\n>>>> Signed-off-by: Marek Vasut \n>>>> ---\n>>>\n>>> Marek,\n>>>\n>>> Some of our boards failed. I traced to this commit. Reverting this\n>>> commit fixes the issue. I happen to have two boards with slightly\n>>> different flash chip. One works and the other doesn't.\n>>\n>> I can't since I don't have the board with such a chip ...\n>> Which chip is that ? Mine is Spansion S25KL256 hyperflash.\n> \n> S26KL256S (26 instead of 25), sorry.\n> \n\nMy local board has chip S29GL01GS11TFIV1. The remote board has identical\nmanufacture ID and device ID. I guess they are the same part (maybe\ndifferent speed grade though). I haven't heard from the team who can\nvisually check the part number for me.\n\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"tpWxGxLa\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; "],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3ydr8C19M3z9s3w\n\tfor ;\n\tSat, 18 Nov 2017 07:59:23 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 49BA6C21DBB; Fri, 17 Nov 2017 20:59:16 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C44E3C21D76;\n\tFri, 17 Nov 2017 20:59:13 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 9BF47C21D76; Fri, 17 Nov 2017 20:59:11 +0000 (UTC)","from EUR01-DB5-obe.outbound.protection.outlook.com\n\t(mail-db5eur01on0049.outbound.protection.outlook.com [104.47.2.49])\n\tby lists.denx.de (Postfix) with ESMTPS id 2DC56C21C45\n\tfor ; Fri, 17 Nov 2017 20:59:11 +0000 (UTC)","from VI1PR04MB2078.eurprd04.prod.outlook.com (10.166.43.18) by\n\tVI1PR04MB1248.eurprd04.prod.outlook.com (10.162.121.157) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id\n\t15.20.218.12; Fri, 17 Nov 2017 20:59:09 +0000","from VI1PR04MB2078.eurprd04.prod.outlook.com\n\t([fe80::94f4:3642:3629:81bb]) by\n\tVI1PR04MB2078.eurprd04.prod.outlook.com\n\t([fe80::94f4:3642:3629:81bb%13]) with mapi id 15.20.0239.007;\n\tFri, 17 Nov 2017 20:59:08 +0000"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=iY/HQxyObOUHcdtrpujIxDCkLIYNWv+MPoT8pMhNLg4=;\n\tb=tpWxGxLaQA/uexFJ9qmfeVqT2yP1YBCaDxcVu2zqw4QXhFQyYL2DTCKLfB4iqpsvFWQfvhspU1g5Q6nkgz+Drldg941R86GcRPaVjXOGzIbzUZZL2qKSrTYvNfcc+R0micnM47bUIpdVuJpa+tP5Zsb1E9QNOH+nuOhmw415X4Q=","From":"York Sun ","To":"Marek Vasut , \"u-boot@lists.denx.de\"\n\t","Thread-Topic":"[U-Boot] mtd: cfi: Add support for status register polling","Thread-Index":"AQHTX8NC7MNPU9HO0keWSuadkLPX0w==","Date":"Fri, 17 Nov 2017 20:59:08 +0000","Message-ID":"","References":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>\n\t\n\t<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>\n\t<48035e40-b6a0-e55c-13f9-df7830e5dd35@gmail.com>","Accept-Language":"en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"tpWxGxLa\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806732,"web_url":"http://patchwork.ozlabs.org/comment/1806732/","msgid":"","list_archive_url":null,"date":"2017-11-17T21:48:40","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"On 11/17/2017 12:59 PM, York Sun wrote:\n> On 11/17/2017 11:04 AM, Marek Vasut wrote:\n>> On 11/17/2017 08:02 PM, Marek Vasut wrote:\n>>> On 11/17/2017 05:43 PM, York Sun wrote:\n>>>> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>>>>> The status register is optional in the AMD command sets, but it's\n>>>>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>>>>> If the register is present, prefer using it's bit 7 to determine\n>>>>> if the flash is busy over reading the flash ; this is needed ie.\n>>>>> on Hyperflash memories.\n>>>>>\n>>>>> Signed-off-by: Marek Vasut \n>>>>> ---\n>>>>\n>>>> Marek,\n>>>>\n>>>> Some of our boards failed. I traced to this commit. Reverting this\n>>>> commit fixes the issue. I happen to have two boards with slightly\n>>>> different flash chip. One works and the other doesn't.\n>>>\n>>> I can't since I don't have the board with such a chip ...\n>>> Which chip is that ? Mine is Spansion S25KL256 hyperflash.\n>>\n>> S26KL256S (26 instead of 25), sorry.\n>>\n> \n> My local board has chip S29GL01GS11TFIV1. The remote board has identical\n> manufacture ID and device ID. I guess they are the same part (maybe\n> different speed grade though). I haven't heard from the team who can\n> visually check the part number for me.\n> \n\nMarek,\n\nI got an email from our hardware team. At some point, our vendor had two\nparts with the same device ID. The other one is S29GL01GP13TFIV1.\nAccording to Cypress migration document, the old part doesn't support\nstatus register feature. I understand you already check lower software\nbits. But I am afraid this register is not valid for old parts which\ndon't support this feature. I checked the datasheet of S29GL01GP. It has\nno description of offset 0xC. Reading from the hardware, I got 0xFF. If\nthere is no \"valid\" bit to indicate we can use lower software bit\nregsiter, it is useless.\n\nComparing the logs\n\nFailing board\n\nFlash: York debug: manuId = 0x1\nYork debug: lsbits = 0xff\nYork debug: read offset 0xE as 0x28\nYork debug: read offset 0xF as 0x1\n128 MiB\n\n\nWorking board\n\nFlash: York debug: manuId = 0x1\nYork debug: lsbits = 0x3\nYork debug: read offset 0xE as 0x28\nYork debug: read offset 0xF as 0x1\n128 MiB\n\nIf there is no other way to know the \"lower software bits\" register is\nvalid, then we have to abandon this feature.\n\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"LROxWdPh\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806825,"web_url":"http://patchwork.ozlabs.org/comment/1806825/","msgid":"<0aae01d7-0808-d7d2-e2ae-96b6c7c662d5@gmail.com>","list_archive_url":null,"date":"2017-11-18T10:23:14","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 11/17/2017 10:48 PM, York Sun wrote:\n> On 11/17/2017 12:59 PM, York Sun wrote:\n>> On 11/17/2017 11:04 AM, Marek Vasut wrote:\n>>> On 11/17/2017 08:02 PM, Marek Vasut wrote:\n>>>> On 11/17/2017 05:43 PM, York Sun wrote:\n>>>>> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>>>>>> The status register is optional in the AMD command sets, but it's\n>>>>>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>>>>>> If the register is present, prefer using it's bit 7 to determine\n>>>>>> if the flash is busy over reading the flash ; this is needed ie.\n>>>>>> on Hyperflash memories.\n>>>>>>\n>>>>>> Signed-off-by: Marek Vasut \n>>>>>> ---\n>>>>>\n>>>>> Marek,\n>>>>>\n>>>>> Some of our boards failed. I traced to this commit. Reverting this\n>>>>> commit fixes the issue. I happen to have two boards with slightly\n>>>>> different flash chip. One works and the other doesn't.\n>>>>\n>>>> I can't since I don't have the board with such a chip ...\n>>>> Which chip is that ? Mine is Spansion S25KL256 hyperflash.\n>>>\n>>> S26KL256S (26 instead of 25), sorry.\n>>>\n>>\n>> My local board has chip S29GL01GS11TFIV1. The remote board has identical\n>> manufacture ID and device ID. I guess they are the same part (maybe\n>> different speed grade though). I haven't heard from the team who can\n>> visually check the part number for me.\n>>\n> \n> Marek,\n> \n> I got an email from our hardware team. At some point, our vendor had two\n> parts with the same device ID. The other one is S29GL01GP13TFIV1.\n> According to Cypress migration document, the old part doesn't support\n> status register feature. I understand you already check lower software\n> bits.\n\nWhich lower software bits ?\n\n> But I am afraid this register is not valid for old parts which\n> don't support this feature. I checked the datasheet of S29GL01GP. It has\n> no description of offset 0xC. Reading from the hardware, I got 0xFF. If\n> there is no \"valid\" bit to indicate we can use lower software bit\n> regsiter, it is useless.\n\nI am happy to dump you whatever you need from the hyperflash (which is\nin fact a CFI NOR flash with different interface), if that helps us\nidentify how to improve the condition to discern flashes which do and do\nnot support this polling feature.\n\nSince CFI is a standard, there must be a way to do it.\n\n> Comparing the logs\n> \n> Failing board\n> \n> Flash: York debug: manuId = 0x1\n> York debug: lsbits = 0xff\n> York debug: read offset 0xE as 0x28\n> York debug: read offset 0xF as 0x1\n> 128 MiB\n> \n> \n> Working board\n> \n> Flash: York debug: manuId = 0x1\n> York debug: lsbits = 0x3\n> York debug: read offset 0xE as 0x28\n> York debug: read offset 0xF as 0x1\n> 128 MiB\n> \n> If there is no other way to know the \"lower software bits\" register is\n> valid, then we have to abandon this feature.\n\nWe cannot because then that breaks hyperflash support, so we need to\nfigure out how to improve the condition to discern the flashes.\n\n> York\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Sat, 18 Nov 2017 02:24:39 -0800 (PST)","from [192.168.1.4] (ip-86-49-107-50.net.upcbroadband.cz.\n\t[86.49.107.50]) by smtp.gmail.com with ESMTPSA id\n\t30sm4034770edz.42.2017.11.18.02.24.37\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSat, 18 Nov 2017 02:24:38 -0800 (PST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=GEzV/yqf8jonkurdzrX+uFZFAZcci8bJtVJJTv3W3H4=;\n\tb=J8Fe4q5+tj/CCnFzPC+CXbiLIPMwyLVtyCTFbfwbojb5V0SK3uH9s65k7+zuuRagd5\n\tRiHc8EmZz1RlLmMPzmKAsbKimzdIxEAyR5cKtdQ+GbrjzTHA80+gbWeXar/etTis2K11\n\t3pwZZilFNpTtvV9U3iBnWcgpBdefhhMuoAm2vTvmD8Wppi41KGDlqJo+OWLh/cgGQtSJ\n\thPuqMWFFBTnBihhjCUCkdJ/BmnE8hhVGRWPQ2JfO8UPLwq6+1C7pXCqJJ/O8lcc7okyw\n\tLW32zNGtluvZ4poLgkLEGUTM6rC+mMRTpLKXVU5wmiQaSwAbC/r9Jp+rfGQpgkKJFEiz\n\ta/1Q==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=GEzV/yqf8jonkurdzrX+uFZFAZcci8bJtVJJTv3W3H4=;\n\tb=MMYnNfikwddJ+7+sbyOjD6UsrR3l435FbeVPZHAEavrqXdobLfCY6C/keU2dVS8mjB\n\tQXH8Y4VQPU9OLJORV6HmInm2ubS6hsO7DmoOCEG7JcvvMw5DRwbzlsZR/If5J/62XxYV\n\toObEjeH6gXqXLkZtRk+VZcj7vs8U7lYJvuP6ffeGaPXMTeOJhPNrY297hdZZsoUx+4pW\n\t1Cd+JUekFRr3DtvywjRcDHdilkW2vPXpceWA/Em7L1xKoadMuddmi0NCSGZRtKIwVw/Z\n\trL14JzggQ6YEJELlfyoBWftvWhPdn7YfZZweHWxNIwGS6SOwY+sIG0u3HqDega6b6ix2\n\tscQw==","X-Gm-Message-State":"AJaThX56FYZuofZMKr4jutjrfwBzktis72SnV/936/BioiLPjgZPi3rz\n\t5bQe/yS3B1cvGpw5U2PlHT0=","X-Google-Smtp-Source":"AGs4zMZBxhdL8Fxt1InJqR6fA1yP6lnuPZyFVqtEGyzQZkYEmk8qbBns1eAusJXo0n+a2jsx5KGqRg==","X-Received":"by 10.80.205.143 with SMTP id p15mr11422306edi.255.1511000678836;\n\tSat, 18 Nov 2017 02:24:38 -0800 (PST)","To":"York Sun ,\n\t\"u-boot@lists.denx.de\" ","References":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>\n\t\n\t<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>\n\t<48035e40-b6a0-e55c-13f9-df7830e5dd35@gmail.com>\n\t\n\t","From":"Marek Vasut ","Message-ID":"<0aae01d7-0808-d7d2-e2ae-96b6c7c662d5@gmail.com>","Date":"Sat, 18 Nov 2017 11:23:14 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","Cc":"Priyanka Jain , Stefan Roese ","Subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1806885,"web_url":"http://patchwork.ozlabs.org/comment/1806885/","msgid":"","list_archive_url":null,"date":"2017-11-18T19:11:28","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":67822,"url":"http://patchwork.ozlabs.org/api/people/67822/","name":"York Sun","email":"york.sun@nxp.com"},"content":"On 11/18/2017 02:24 AM, Marek Vasut wrote:\n> On 11/17/2017 10:48 PM, York Sun wrote:\n>> On 11/17/2017 12:59 PM, York Sun wrote:\n>>> On 11/17/2017 11:04 AM, Marek Vasut wrote:\n>>>> On 11/17/2017 08:02 PM, Marek Vasut wrote:\n>>>>> On 11/17/2017 05:43 PM, York Sun wrote:\n>>>>>> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>>>>>>> The status register is optional in the AMD command sets, but it's\n>>>>>>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>>>>>>> If the register is present, prefer using it's bit 7 to determine\n>>>>>>> if the flash is busy over reading the flash ; this is needed ie.\n>>>>>>> on Hyperflash memories.\n>>>>>>>\n>>>>>>> Signed-off-by: Marek Vasut \n>>>>>>> ---\n>>>>>>\n>>>>>> Marek,\n>>>>>>\n>>>>>> Some of our boards failed. I traced to this commit. Reverting this\n>>>>>> commit fixes the issue. I happen to have two boards with slightly\n>>>>>> different flash chip. One works and the other doesn't.\n>>>>>\n>>>>> I can't since I don't have the board with such a chip ...\n>>>>> Which chip is that ? Mine is Spansion S25KL256 hyperflash.\n>>>>\n>>>> S26KL256S (26 instead of 25), sorry.\n>>>>\n>>>\n>>> My local board has chip S29GL01GS11TFIV1. The remote board has identical\n>>> manufacture ID and device ID. I guess they are the same part (maybe\n>>> different speed grade though). I haven't heard from the team who can\n>>> visually check the part number for me.\n>>>\n>>\n>> Marek,\n>>\n>> I got an email from our hardware team. At some point, our vendor had two\n>> parts with the same device ID. The other one is S29GL01GP13TFIV1.\n>> According to Cypress migration document, the old part doesn't support\n>> status register feature. I understand you already check lower software\n>> bits.\n> \n> Which lower software bits ?\n\nRegister at offset 0xC. This register is not part of CFI. But there is\nCFI extention, explained below.\n\n> \n>> But I am afraid this register is not valid for old parts which\n>> don't support this feature. I checked the datasheet of S29GL01GP. It has\n>> no description of offset 0xC. Reading from the hardware, I got 0xFF. If\n>> there is no \"valid\" bit to indicate we can use lower software bit\n>> regsiter, it is useless.\n> \n> I am happy to dump you whatever you need from the hyperflash (which is\n> in fact a CFI NOR flash with different interface), if that helps us\n> identify how to improve the condition to discern flashes which do and do\n> not support this polling feature.\n> \n> Since CFI is a standard, there must be a way to do it.\n\nIn vendor specific extended query, it has a register at address 53h in\nthis document http://www.cypress.com/file/213771/download.\n\n> \n>> Comparing the logs\n>>\n>> Failing board\n>>\n>> Flash: York debug: manuId = 0x1\n>> York debug: lsbits = 0xff\n>> York debug: read offset 0xE as 0x28\n>> York debug: read offset 0xF as 0x1\n>> 128 MiB\n>>\n>>\n>> Working board\n>>\n>> Flash: York debug: manuId = 0x1\n>> York debug: lsbits = 0x3\n>> York debug: read offset 0xE as 0x28\n>> York debug: read offset 0xF as 0x1\n>> 128 MiB\n>>\n>> If there is no other way to know the \"lower software bits\" register is\n>> valid, then we have to abandon this feature.\n> \n> We cannot because then that breaks hyperflash support, so we need to\n> figure out how to improve the condition to discern the flashes.\n> \n\nI sent you a patch. Please review.\n\nYork","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"sMsGmZ/z\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=york.sun@nxp.com; "],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yfPjX1WtPz9s0Z\n\tfor ;\n\tSun, 19 Nov 2017 06:11:44 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid C6A35C21DDA; Sat, 18 Nov 2017 19:11:36 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 6C091C21D8C;\n\tSat, 18 Nov 2017 19:11:34 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 97EC2C21D8C; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1814487,"web_url":"http://patchwork.ozlabs.org/comment/1814487/","msgid":"<7ba58d31-2050-0923-a571-ed800c4009a6@gmail.com>","list_archive_url":null,"date":"2017-12-02T09:14:34","subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 11/18/2017 08:11 PM, York Sun wrote:\n> On 11/18/2017 02:24 AM, Marek Vasut wrote:\n>> On 11/17/2017 10:48 PM, York Sun wrote:\n>>> On 11/17/2017 12:59 PM, York Sun wrote:\n>>>> On 11/17/2017 11:04 AM, Marek Vasut wrote:\n>>>>> On 11/17/2017 08:02 PM, Marek Vasut wrote:\n>>>>>> On 11/17/2017 05:43 PM, York Sun wrote:\n>>>>>>> On 09/12/2017 10:09 AM, Marek Vasut wrote:\n>>>>>>>> The status register is optional in the AMD command sets, but it's\n>>>>>>>> presence can be checked by reading out CFI table entry 0xc bit 0.\n>>>>>>>> If the register is present, prefer using it's bit 7 to determine\n>>>>>>>> if the flash is busy over reading the flash ; this is needed ie.\n>>>>>>>> on Hyperflash memories.\n>>>>>>>>\n>>>>>>>> Signed-off-by: Marek Vasut \n>>>>>>>> ---\n>>>>>>>\n>>>>>>> Marek,\n>>>>>>>\n>>>>>>> Some of our boards failed. I traced to this commit. Reverting this\n>>>>>>> commit fixes the issue. I happen to have two boards with slightly\n>>>>>>> different flash chip. One works and the other doesn't.\n>>>>>>\n>>>>>> I can't since I don't have the board with such a chip ...\n>>>>>> Which chip is that ? Mine is Spansion S25KL256 hyperflash.\n>>>>>\n>>>>> S26KL256S (26 instead of 25), sorry.\n>>>>>\n>>>>\n>>>> My local board has chip S29GL01GS11TFIV1. The remote board has identical\n>>>> manufacture ID and device ID. I guess they are the same part (maybe\n>>>> different speed grade though). I haven't heard from the team who can\n>>>> visually check the part number for me.\n>>>>\n>>>\n>>> Marek,\n>>>\n>>> I got an email from our hardware team. At some point, our vendor had two\n>>> parts with the same device ID. The other one is S29GL01GP13TFIV1.\n>>> According to Cypress migration document, the old part doesn't support\n>>> status register feature. I understand you already check lower software\n>>> bits.\n>>\n>> Which lower software bits ?\n> \n> Register at offset 0xC. This register is not part of CFI. But there is\n> CFI extention, explained below.\n> \n>>\n>>> But I am afraid this register is not valid for old parts which\n>>> don't support this feature. I checked the datasheet of S29GL01GP. It has\n>>> no description of offset 0xC. Reading from the hardware, I got 0xFF. If\n>>> there is no \"valid\" bit to indicate we can use lower software bit\n>>> regsiter, it is useless.\n>>\n>> I am happy to dump you whatever you need from the hyperflash (which is\n>> in fact a CFI NOR flash with different interface), if that helps us\n>> identify how to improve the condition to discern flashes which do and do\n>> not support this polling feature.\n>>\n>> Since CFI is a standard, there must be a way to do it.\n> \n> In vendor specific extended query, it has a register at address 53h in\n> this document http://www.cypress.com/file/213771/download.\n\nCool, that works!\n\n>>\n>>> Comparing the logs\n>>>\n>>> Failing board\n>>>\n>>> Flash: York debug: manuId = 0x1\n>>> York debug: lsbits = 0xff\n>>> York debug: read offset 0xE as 0x28\n>>> York debug: read offset 0xF as 0x1\n>>> 128 MiB\n>>>\n>>>\n>>> Working board\n>>>\n>>> Flash: York debug: manuId = 0x1\n>>> York debug: lsbits = 0x3\n>>> York debug: read offset 0xE as 0x28\n>>> York debug: read offset 0xF as 0x1\n>>> 128 MiB\n>>>\n>>> If there is no other way to know the \"lower software bits\" register is\n>>> valid, then we have to abandon this feature.\n>>\n>> We cannot because then that breaks hyperflash support, so we need to\n>> figure out how to improve the condition to discern the flashes.\n>>\n> \n> I sent you a patch. Please review.\n\nDone, thanks\n\n> York\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"uzt2YG5q\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3yppcF55lpz9t3x\n\tfor ;\n\tSat, 2 Dec 2017 22:21:16 +1100 (AEDT)","by lists.denx.de (Postfix, from userid 105)\n\tid 2A902C21FE1; Sat, 2 Dec 2017 11:21:09 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 8C63BC21E76;\n\tSat, 2 Dec 2017 11:21:06 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 8380DC21E76; Sat, 2 Dec 2017 11:21:05 +0000 (UTC)","from mail-pl0-f48.google.com (mail-pl0-f48.google.com\n\t[209.85.160.48])\n\tby lists.denx.de (Postfix) with ESMTPS id D0C93C21DA3\n\tfor ; Sat, 2 Dec 2017 11:21:04 +0000 (UTC)","by mail-pl0-f48.google.com with SMTP id q7so7778221plk.0\n\tfor ; Sat, 02 Dec 2017 03:21:04 -0800 (PST)","from [192.168.43.97] ([219.100.139.57])\n\tby smtp.gmail.com with ESMTPSA id\n\tp85sm15620073pfk.147.2017.12.02.03.20.59\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSat, 02 Dec 2017 03:21:02 -0800 (PST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=EJv90T4LCkTtKSHSg2/76h0X44M17Vl9HMdnHX5nefg=;\n\tb=uzt2YG5qGORysNUxb6vRdILAMcEz/5tGSxDbtYsTK3JwYCep9qSGnE0asHg6A3ZOgZ\n\t2d84E0epP6slpavto+vAUawt5fIlj9Y6XoJ+tFL9ngtHN5pyRSFa33x/bThaG4ILt0ce\n\t4GhPLjtqsYG4qNw0EVCEoIt8X0O24bIw8zWu0s9uLDOKOIqOoYO2pAg7A0RoTxcqPYyU\n\tPYgGEceAV2NmbrHqv79YFG3q6kQT1qQ16aBRVka+dMnn5H0ln/0J0HOHweQglUdK9PTm\n\tjcaXdgrwNTILp8df3bxMMF8CoCS+LXddAAzsnSjrFsw5GH0TCFJ2c7GqDFFC2UNknMjv\n\ty8pg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=EJv90T4LCkTtKSHSg2/76h0X44M17Vl9HMdnHX5nefg=;\n\tb=XL8alS9J24zCdO1chAhn+6EVHHAXzYO0LpP3b0HFT8tt+IybTM1vVjrSiUl58kIKFr\n\tiPzo3LTe1/I78ofs/qkbA/5tRAlE5/GYIL1Eg7vfTN9YOcf4LE4N7/2wRZtMOxIpNbR0\n\tqZsAjadInEUD0RYUdBXW62NFV6GwBel5HqOhPrO8Flut9a4cYgj15emNP1cTxSm4RjTj\n\tYWzTKsUR2MQxvKDyoknoFVkiXai6Vmw8Hy7B4lb0xQ0FMVauAx0GKEozPLTnIFVeBp4G\n\tHywzG5COjWXL4vqQTXesvSsIsN99RroWoKXNgAolF90UKRJT6klr+Q8vQzngvpxHH3Xw\n\tFHSg==","X-Gm-Message-State":"AJaThX4mSEP053HbxMGRRYzsnCDUR0Lq0tfAYFKqClFy83Bl6F6UlfDf\n\teWOSwXWQUhgYusBCrZ6xLao=","X-Google-Smtp-Source":"AGs4zMYFr0IglUYzbnYBjt9OEb110G2F2408uUMzaXv6bviZl8eBOo72rX5k4hGi7UUDTFixFG3eIQ==","X-Received":"by 10.159.241.1 with SMTP id q1mr9083184plr.383.1512213662942;\n\tSat, 02 Dec 2017 03:21:02 -0800 (PST)","To":"York Sun ,\n\t\"u-boot@lists.denx.de\" ","References":"<20170912170931.29974-1-marek.vasut+renesas@gmail.com>\n\t\n\t<48e13a2e-3380-4ff5-ad64-6b3e23910156@gmail.com>\n\t<48035e40-b6a0-e55c-13f9-df7830e5dd35@gmail.com>\n\t\n\t\n\t<0aae01d7-0808-d7d2-e2ae-96b6c7c662d5@gmail.com>\n\t","From":"Marek Vasut ","Message-ID":"<7ba58d31-2050-0923-a571-ed800c4009a6@gmail.com>","Date":"Sat, 2 Dec 2017 10:14:34 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","Cc":"Priyanka Jain , Stefan Roese ","Subject":"Re: [U-Boot] mtd: cfi: Add support for status register polling","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]