[{"id":1773915,"web_url":"http://patchwork.ozlabs.org/comment/1773915/","msgid":"","list_archive_url":null,"date":"2017-09-22T22:15:56","subject":"Re: [U-Boot] [PATCH 3/6] ARM: rmobile: Move HSUSB configuration to\n\tboard on ULCB","submitter":{"id":1028,"url":"http://patchwork.ozlabs.org/api/people/1028/","name":"Nobuhiro Iwamatsu","email":"iwamatsu@nigauri.org"},"content":"Hi,\n\n2017-09-13 2:07 GMT+09:00 Marek Vasut :\n> In order to use ehci-generic driver, move the configuration of HSUSB\n> block into the board file. This configuration should not have been in\n> the Gen3 EHCI USB driver in the first place, so move it to the board\n> file until there is a proper infrastructure and driver for the HSUSB\n> block.\n>\n> Signed-off-by: Marek Vasut \n> Cc: Nobuhiro Iwamatsu \n\nApplied to rmobile branch.\n\nThanks,\n Nobuhiro\n\n> ---\n> board/renesas/ulcb/ulcb.c | 16 ++++++++++++++++\n> 1 file changed, 16 insertions(+)\n>\n> diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c\n> index dc23228f4f..578b14be7b 100644\n> --- a/board/renesas/ulcb/ulcb.c\n> +++ b/board/renesas/ulcb/ulcb.c\n> @@ -53,6 +53,7 @@ void s_init(void)\n> #define SD0_MSTP314 BIT(14)\n> #define SD1_MSTP313 BIT(13)\n> #define SD2_MSTP312 BIT(12) /* either MMC0 */\n> +#define HSUSB_MSTP704 BIT(4) /* HSUSB */\n>\n> #define SD0CKCR 0xE6150074\n> #define SD1CKCR 0xE6150078\n> @@ -90,6 +91,13 @@ int board_early_init_f(void)\n> /* -/W 32 Power resume control register 2 (3DG) */\n> #define SYSC_PWRONCR2 0xE618010C\n>\n> +/* HSUSB block registers */\n> +#define HSUSB_REG_LPSTS 0xE6590102\n> +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)\n> +#define HSUSB_REG_UGCTRL2 0xE6590184\n> +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30\n> +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10\n> +\n> int board_init(void)\n> {\n> /* adress of boot parameters */\n> @@ -105,6 +113,14 @@ int board_init(void)\n> /* USB1 pull-up */\n> setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN);\n>\n> + /* Configure the HSUSB block */\n> + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704);\n> + /* Choice USB0SEL */\n> + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL,\n> + HSUSB_REG_UGCTRL2_USB0SEL_EHCI);\n> + /* low power status */\n> + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);\n> +\n> #ifdef CONFIG_RENESAS_RAVB\n> /* EtherAVB Enable */\n> /* GPSR2 */\n> --\n> 2.11.0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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