[{"id":1774105,"web_url":"http://patchwork.ozlabs.org/comment/1774105/","msgid":"<CABMQnVJF+faS871CXADFOYF4m5hncjU2hAoX2bhGid_t1s=NXw@mail.gmail.com>","list_archive_url":null,"date":"2017-09-24T05:46:13","subject":"Re: [U-Boot] [PATCH 6/6] usb: Drop the EHCI RCar Gen3","submitter":{"id":1028,"url":"http://patchwork.ozlabs.org/api/people/1028/","name":"Nobuhiro Iwamatsu","email":"iwamatsu@nigauri.org"},"content":"Hi,\n\n2017-09-13 2:07 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:\n> Since we use EHCI generic driver on RCar Gen3 , this driver is useless.\n> Remove it.\n>\n> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>\n> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\n\nAcked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\n\nBest regards,\n  Nobuhiro\n\n> ---\n>  drivers/usb/host/Kconfig          |   8 ---\n>  drivers/usb/host/Makefile         |   1 -\n>  drivers/usb/host/ehci-rcar_gen3.c | 106 --------------------------------------\n>  3 files changed, 115 deletions(-)\n>  delete mode 100644 drivers/usb/host/ehci-rcar_gen3.c\n>\n> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig\n> index eb035a476b..5438feb8f5 100644\n> --- a/drivers/usb/host/Kconfig\n> +++ b/drivers/usb/host/Kconfig\n> @@ -148,14 +148,6 @@ config USB_EHCI_PCI\n>         help\n>           Enables support for the PCI-based EHCI controller.\n>\n> -config USB_EHCI_RCAR_GEN3\n> -       bool \"Support for Renesas RCar M3/H3 EHCI USB controller\"\n> -       depends on RCAR_GEN3\n> -       default y\n> -       ---help---\n> -         Enables support for the on-chip EHCI controller on Renesas\n> -         R8A7795 and R8A7796 SoCs.\n> -\n>  config USB_EHCI_ZYNQ\n>         bool \"Support for Xilinx Zynq on-chip EHCI USB controller\"\n>         depends on ARCH_ZYNQ\n> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile\n> index ab5a99faa8..d3ff591a71 100644\n> --- a/drivers/usb/host/Makefile\n> +++ b/drivers/usb/host/Makefile\n> @@ -46,7 +46,6 @@ obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o\n>  obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o\n>  obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o\n>  obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o\n> -obj-$(CONFIG_USB_EHCI_RCAR_GEN3) += ehci-rcar_gen3.o\n>  obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o\n>\n>  # xhci\n> diff --git a/drivers/usb/host/ehci-rcar_gen3.c b/drivers/usb/host/ehci-rcar_gen3.c\n> deleted file mode 100644\n> index 525e7f3573..0000000000\n> --- a/drivers/usb/host/ehci-rcar_gen3.c\n> +++ /dev/null\n> @@ -1,106 +0,0 @@\n> -/*\n> - * drivers/usb/host/ehci-rcar_gen3.\n> - *     This file is EHCI HCD (Host Controller Driver) for USB.\n> - *\n> - * Copyright (C) 2015-2017 Renesas Electronics Corporation\n> - *\n> - * SPDX-License-Identifier:     GPL-2.0+\n> - */\n> -\n> -#include <common.h>\n> -#include <errno.h>\n> -#include <wait_bit.h>\n> -#include <asm/io.h>\n> -#include <usb/ehci-ci.h>\n> -#include \"ehci.h\"\n> -\n> -#define RCAR_GEN3_USB_BASE(n)  (0xEE080000 + ((n) * 0x20000))\n> -\n> -#define EHCI_USBCMD            0x120\n> -\n> -#define CORE_SPD_RSM_TIMSET    0x30c\n> -#define CORE_OC_TIMSET         0x310\n> -\n> -/* Register offset */\n> -#define AHB_OFFSET             0x200\n> -\n> -#define BASE_HSUSB             0xE6590000\n> -#define REG_LPSTS              (BASE_HSUSB + 0x0102)   /* 16bit */\n> -#define SUSPM                  0x4000\n> -#define SUSPM_NORMAL           BIT(14)\n> -#define REG_UGCTRL2            (BASE_HSUSB + 0x0184)   /* 32bit */\n> -#define USB0SEL                        0x00000030\n> -#define USB0SEL_EHCI           0x00000010\n> -\n> -#define SMSTPCR7               0xE615014C\n> -#define SMSTPCR700             BIT(0)  /* EHCI3 */\n> -#define SMSTPCR701             BIT(1)  /* EHCI2 */\n> -#define SMSTPCR702             BIT(2)  /* EHCI1 */\n> -#define SMSTPCR703             BIT(3)  /* EHCI0 */\n> -#define SMSTPCR704             BIT(4)  /* HSUSB */\n> -\n> -#define AHB_PLL_RST            BIT(1)\n> -\n> -#define USBH_INTBEN            BIT(2)\n> -#define USBH_INTAEN            BIT(1)\n> -\n> -#define AHB_INT_ENABLE         0x200\n> -#define AHB_USBCTR             0x20c\n> -\n> -int ehci_hcd_stop(int index)\n> -{\n> -#if defined(CONFIG_R8A7795)\n> -       const u32 mask = SMSTPCR703 | SMSTPCR702 | SMSTPCR701 | SMSTPCR700;\n> -#else\n> -       const u32 mask = SMSTPCR703 | SMSTPCR702;\n> -#endif\n> -       const u32 base = RCAR_GEN3_USB_BASE(index);\n> -       int ret;\n> -\n> -       /* Reset EHCI */\n> -       setbits_le32((uintptr_t)(base + EHCI_USBCMD), CMD_RESET);\n> -       ret = wait_for_bit(\"ehci-rcar\", (void *)(uintptr_t)base + EHCI_USBCMD,\n> -                          CMD_RESET, false, 10, true);\n> -       if (ret) {\n> -               printf(\"ehci-rcar: reset failed (index=%i, ret=%i).\\n\",\n> -                      index, ret);\n> -       }\n> -\n> -       setbits_le32(SMSTPCR7, BIT(3 - index));\n> -\n> -       if ((readl(SMSTPCR7) & mask) == mask)\n> -               setbits_le32(SMSTPCR7, SMSTPCR704);\n> -\n> -       return 0;\n> -}\n> -\n> -int ehci_hcd_init(int index, enum usb_init_type init,\n> -                 struct ehci_hccr **hccr, struct ehci_hcor **hcor)\n> -{\n> -       const void __iomem *base =\n> -               (void __iomem *)(uintptr_t)RCAR_GEN3_USB_BASE(index);\n> -       struct usb_ehci *ehci = (struct usb_ehci *)(uintptr_t)base;\n> -\n> -       clrbits_le32(SMSTPCR7, BIT(3 - index));\n> -       clrbits_le32(SMSTPCR7, SMSTPCR704);\n> -\n> -       *hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);\n> -       *hcor = (struct ehci_hcor *)((uintptr_t)*hccr +\n> -                       HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));\n> -\n> -       /* Enable interrupt */\n> -       setbits_le32(base + AHB_INT_ENABLE, USBH_INTBEN | USBH_INTAEN);\n> -       writel(0x014e029b, base + CORE_SPD_RSM_TIMSET);\n> -       writel(0x000209ab, base + CORE_OC_TIMSET);\n> -\n> -       /* Choice USB0SEL */\n> -       clrsetbits_le32(REG_UGCTRL2, USB0SEL, USB0SEL_EHCI);\n> -\n> -       /* Clock & Reset */\n> -       clrbits_le32(base + AHB_USBCTR, AHB_PLL_RST);\n> -\n> -       /* low power status */\n> -       clrsetbits_le16(REG_LPSTS, SUSPM, SUSPM_NORMAL);\n> -\n> -       return 0;\n> -}\n> --\n> 2.11.0\n>","headers":{"Return-Path":"<u-boot-bounces@lists.denx.de>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nigauri-org.20150623.gappssmtp.com\n\theader.i=@nigauri-org.20150623.gappssmtp.com\n\theader.b=\"wLlkuznm\"; dkim-atps=neutral"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0GST3q0Rz9t4b\n\tfor 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<20170912170725.29733-6-marek.vasut+renesas@gmail.com>","References":"<20170912170725.29733-1-marek.vasut+renesas@gmail.com>\n\t<20170912170725.29733-6-marek.vasut+renesas@gmail.com>","From":"Nobuhiro Iwamatsu <iwamatsu@nigauri.org>","Date":"Sun, 24 Sep 2017 14:46:13 +0900","Message-ID":"<CABMQnVJF+faS871CXADFOYF4m5hncjU2hAoX2bhGid_t1s=NXw@mail.gmail.com>","To":"Marek Vasut <marek.vasut@gmail.com>","Cc":"U-Boot <u-boot@lists.denx.de>,\n\tMarek Vasut <marek.vasut+renesas@gmail.com>","Subject":"Re: [U-Boot] [PATCH 6/6] usb: Drop the EHCI RCar Gen3","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion 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