[{"id":1767288,"web_url":"http://patchwork.ozlabs.org/comment/1767288/","msgid":"","list_archive_url":null,"date":"2017-09-12T18:50:11","subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"Hi Richard,\n\nOn 09/12/2017 01:25 PM, Richard Henderson wrote:\n> Signed-off-by: Richard Henderson \n> ---\n> target/arm/cpu.h | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n> \n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 98b9b26fd3..419f008277 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -486,7 +486,7 @@ typedef struct CPUARMState {\n> * the two execution states, and means we do not need to explicitly\n> * map these registers when changing states.\n> */\n> - float64 regs[64];\n> + float64 regs[64] __attribute__((aligned(16)));\n\nI understand this should be aligned to the biggest vector register the \nhost support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it \ncorrect?\n\nI'd rather use a #define such HOST_VECTOR_LENGTH_BITS_MAX and \nQEMU_ALIGNED(HOST_VECTOR_LENGTH_BITS_MAX / BITS_PER_BYTE) or directly \nQEMU_ALIGNED(HOST_VECTOR_LENGTH_MAX), using the define makes it \nself-explanatory. Or shorter:\n\n float64 regs[64] QEMU_ALIGNED(HOST_VECTOR_SIZE);\n\nWhat do you think?\n\nRegards,\n\nPhil.\n\n> \n> uint32_t xregs[16];\n> /* We store these fpcsr fields separately for convenience. */\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BJUL0dqJ\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsDQT091vz9s8J\n\tfor ;\n\tWed, 13 Sep 2017 04:50:57 +1000 (AEST)","from localhost ([::1]:38142 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drqGt-0005gM-62\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:50:55 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:59652)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from )\n\tid 1drqGJ-0005eo-Hj\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:50:20 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from )\n\tid 1drqGG-0006no-DY\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:50:19 -0400","from mail-qk0-x236.google.com ([2607:f8b0:400d:c09::236]:38243)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1drqGG-0006mp-8Z\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:50:16 -0400","by mail-qk0-x236.google.com with SMTP id a128so27084808qkc.5\n\tfor ; Tue, 12 Sep 2017 11:50:14 -0700 (PDT)","from [192.168.1.10] ([181.93.89.178])\n\tby smtp.gmail.com with ESMTPSA id\n\tn66sm7929936qka.47.2017.09.12.11.50.12\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 11:50:13 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=Lx2EWWrCcNq4jk4hF3fEmyjOBotoFefbYptRe3B/URs=;\n\tb=BJUL0dqJlpX8qcrFaEMFXJprqVTmDBqr6WRPsuo51Sf+XaPpjXWRac9ahYZkAAFId/\n\teOJ1BS3gO0Se71eFRHxeuv8/nmgg+Yvq8aYFajlymQm4MaWvGo3ZD6A5h+HH3lPsgeeI\n\txllhJLzPWjj7O0vI05Z/5IedscyC28idaOZG8RbqJk9OGW7MiWI1VbJDf36IEU5KeIP+\n\tFfu/KVbsoStcOBcSh5DDeCKwLK1WMY5vSy6/N0ZJBn2+epszVZb1dNPISS4b851DDZjK\n\tQoaEQZMPrKZYi9v11FRXfDBBL4PRzpt336gxxuh2EgHO6InnNco+q5hEGyaMjURhNIZx\n\tzIYg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:subject:to:cc:references:from:message-id\n\t:date:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=Lx2EWWrCcNq4jk4hF3fEmyjOBotoFefbYptRe3B/URs=;\n\tb=Md6KxVLYrrlcTS1XAcbnaIfwIHynhBQNg9i9AYjANwSW824aCituhL49v8tZ6e1sxj\n\t654Ju8yKIp1vUqVfqCo2dJbf1RMcDfHnArvsQE98tL5ttUyWxY9rE8HEPAsZMrsIfMG1\n\tUDb8myV0y6WfD68P2F7rVvEz5rb0As1rruvWL+iJLlknigjUxaD0/HSpPySovkSkvo+G\n\tOwBLq93QoDcG8AO2YkNuvpOn2GViXkw0wqohwMCAM41KS3Tf2b9OhBpQ3mNKYd3kSwLs\n\tgltmRbdpqC3uWczRDzz6hTG4nKV0OgziZDB3s6j7LQMgKIrUbZJdweb0kHWf9qdO6s43\n\tDkVg==","X-Gm-Message-State":"AHPjjUjfU2DbQZa8vBlYycUFR6LDqihDSrTHXKurP1DEfzWofK4vxakN\n\tKj1k50+D5jtjWw==","X-Google-Smtp-Source":"AOwi7QBn1/1fCPWg6R/DShsTx/RuY4a3P0jHGpru0pbKpFzsYKA+AU2C/FN4rRkQ3xDS0ydmN9fqYQ==","X-Received":"by 10.55.184.1 with SMTP id i1mr7598024qkf.236.1505242214385;\n\tTue, 12 Sep 2017 11:50:14 -0700 (PDT)","To":"Richard Henderson , qemu-devel@nongnu.org","References":"<20170912162513.21694-1-richard.henderson@linaro.org>\n\t<20170912162513.21694-8-richard.henderson@linaro.org>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"","Date":"Tue, 12 Sep 2017 15:50:11 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170912162513.21694-8-richard.henderson@linaro.org>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::236","Subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alex.bennee@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767293,"web_url":"http://patchwork.ozlabs.org/comment/1767293/","msgid":"","list_archive_url":null,"date":"2017-09-12T18:55:31","subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 12 September 2017 at 17:25, Richard Henderson\n wrote:\n> Signed-off-by: Richard Henderson \n> ---\n> target/arm/cpu.h | 2 +-\n> 1 file changed, 1 insertion(+), 1 deletion(-)\n>\n> diff --git a/target/arm/cpu.h b/target/arm/cpu.h\n> index 98b9b26fd3..419f008277 100644\n> --- a/target/arm/cpu.h\n> +++ b/target/arm/cpu.h\n> @@ -486,7 +486,7 @@ typedef struct CPUARMState {\n> * the two execution states, and means we do not need to explicitly\n> * map these registers when changing states.\n> */\n> - float64 regs[64];\n> + float64 regs[64] __attribute__((aligned(16)));\n>\n> uint32_t xregs[16];\n> /* We store these fpcsr fields separately for convenience. */\n> --\n> 2.13.5\n\nI notice we have a QEMU_ALIGNED() macro to wrap the __attribute__,\nthough we use it less often than not at the moment...\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"WUYcDkiN\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsDXb3W7Mz9s7g\n\tfor ;\n\tWed, 13 Sep 2017 04:56:15 +1000 (AEST)","from localhost ([::1]:38168 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drqM1-0001Na-FP\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:56:13 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:33830)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drqLi-0001NA-8l\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:55:55 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drqLh-00024Z-GR\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:55:54 -0400","from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:43825)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1drqLh-00024D-9B\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:55:53 -0400","by mail-wm0-x22f.google.com with SMTP id a137so2007795wma.0\n\tfor ; Tue, 12 Sep 2017 11:55:53 -0700 (PDT)","by 10.223.139.215 with HTTP; Tue, 12 Sep 2017 11:55:31 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=2eibT98OIhH7dTFnOPPp8kaZKFU+5kyQJqbo9BtNuco=;\n\tb=WUYcDkiNftgmOyb9OqI19JNR0XaAXK8IwO4Q6rmHgo7+5L1c1fpPB0mIDOSA06r6Gr\n\tVFqRnVmHV64sgHUC98NIfByeCdA7XIUCkONqW4bhuQIte+msjNKDmDI82Thd3IoJgWNC\n\ttplTzN5E+7iEpX8ydlE5qZ/Fhhc+ZQ4LmylDQ=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=2eibT98OIhH7dTFnOPPp8kaZKFU+5kyQJqbo9BtNuco=;\n\tb=htyZefT1LYcdXAsHlbDW1syFJ0ypKJqxh5wIdeqrIEZvMm/nKGN3C6TT0tpXjGSnXm\n\t+X85B8g9oV7HN22q2zVDgwMNifFGbWEqm2f2IeYYMH9dv4DUW3vVM/Wl4T9nsTA1D2cT\n\tPw5PubLLzaTx89jkCgn5Wz7wJ9O85hcbFLQBGLWZ7IhIb7imCB8wZBMi3PXDeJ1n40D5\n\tqxCDbhiguAYrbant+jQAofUp1+WscvJqMldk9QfBaycamrUOnMHaSn9jsMOrNz3IbJ36\n\tM9TtAFi/2LgU2xjJmj8oDgb+OdukRiOsnU5CV1z1pctKVcKeTAqKZ+WAhgkdIWBx5IqB\n\t9Gpg==","X-Gm-Message-State":"AHPjjUh8vyMBXMuUT4SoQMoDVeLK5cJaYs9orxPBu3CHO7MAtU7AVUOj\n\tI5N/7CNqGmcP+ZH/gHFAuHdexAfpz655R6/rThJchQ==","X-Google-Smtp-Source":"AOwi7QCot6VAt5QpD/CuZJvGRkv4yIfB+FQgvjN6vavZQRrEdF0rGENkDliskroxs+hk0uDwGkHkR71F4xd41naH1PY=","X-Received":"by 10.28.102.213 with SMTP id a204mr360041wmc.151.1505242551731; \n\tTue, 12 Sep 2017 11:55:51 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170912162513.21694-8-richard.henderson@linaro.org>","References":"<20170912162513.21694-1-richard.henderson@linaro.org>\n\t<20170912162513.21694-8-richard.henderson@linaro.org>","From":"Peter Maydell ","Date":"Tue, 12 Sep 2017 19:55:31 +0100","Message-ID":"","To":"Richard Henderson ","Content-Type":"text/plain; charset=\"UTF-8\"","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22f","Subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Alex_Benn=C3=A9e?= ,\n\tQEMU Developers , =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?b?YXVkw6k=?= ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767312,"web_url":"http://patchwork.ozlabs.org/comment/1767312/","msgid":"","list_archive_url":null,"date":"2017-09-12T20:17:51","subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/12/2017 03:55 PM, Peter Maydell wrote:\n> I notice we have a QEMU_ALIGNED() macro to wrap the __attribute__,\n> though we use it less often than not at the moment...\n\nAesthetic aside, I find it useful to deal with the 80 characters style \nlimit.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"aGqU3Mel\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsGMS3JRqz9s7f\n\tfor ;\n\tWed, 13 Sep 2017 06:18:27 +1000 (AEST)","from localhost ([::1]:38385 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drrdY-0006TM-Ph\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 16:18:24 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:34296)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from )\n\tid 1drrd8-0006T4-Tw\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:17:59 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from )\n\tid 1drrd5-0006gK-Ih\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:17:58 -0400","from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:34596)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1drrd5-0006fa-DA\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:17:55 -0400","by mail-qk0-x242.google.com with SMTP id d70so7831677qkc.1\n\tfor ; Tue, 12 Sep 2017 13:17:55 -0700 (PDT)","from [192.168.1.10] ([181.93.89.178])\n\tby smtp.gmail.com with ESMTPSA id\n\tl89sm8694453qkh.69.2017.09.12.13.17.52\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 13:17:54 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=xZOggodeYBC/aoDhY7tNREkpNVvPS5WJ1yCb6NRaYo0=;\n\tb=aGqU3MelBEuCRkWRZlCwmfnC3S1FlM/3rdbRuPDH0eV7HVGQHy+Z22DH2usNc/kMCc\n\t1F26ZcHc4u0rOt2q0QzrutX8vcje2o7qUCFw2b8Crq6JjVFeIuRJZ2XFB6bCq33f02MH\n\tq4kVYd/CGqWoHI2IJk2gR6tfZL5PSNVcNprHY7Gw8/1JdqWQxJ/R/v0Q3EpGZ8VSvXmM\n\tlKMZuu7rkeREb/HBHNa+CGN7c6lkiR7MmvJcCuQNM7uYxkycjkCuFnhm/bpznT4Jk7Ib\n\txLeR9QxcRBmxmwdCQxh8Ijrdkdn9qCWu8DL14I6AJsDWdoKQNbrFcSzHONfShH23e8xh\n\t550g==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:subject:to:cc:references:from:message-id\n\t:date:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=xZOggodeYBC/aoDhY7tNREkpNVvPS5WJ1yCb6NRaYo0=;\n\tb=NfW1ca/ejy16cNKY015lfCy/cDZRmtAcrQ+iTOK6+97x6+O6QhrVibZPBtRZ/STdDY\n\tJ2qte697BsluBcMTGdyoOD0TmisuKtadU4aAhzcN90mtLUbv93oPHid9wHnqUC4IcLMP\n\tyZV5HzJjUz/aMrVbLMYa1UfhJ17HaQR8HkBRPEsILRN4ybow0ktU0jAzAldvt02slXhN\n\tCwLhurRGIXjmKPQeNxl9w1qg+cylFrFtIEamaw1/puoa8H8jv2pRMm0Fz9ibLezvz8v8\n\tbAcFw5fcYSjbZDUKgOzYwU5ORsgF3OEjdSzFM0xzf4oza66ysNkvf9DiYRC1QhoS90K4\n\tPjbQ==","X-Gm-Message-State":"AHPjjUicszfVl1Hr6GYcNjkf2Q1Bd4jxkRacIBG/csHudmfp8W8mzrJe\n\t/gXYaBRL4jKZYg==","X-Google-Smtp-Source":"ADKCNb7aut0FmNIr8As8y2yM2nVoL5sUe/Z2TnFcIOHJbCeLcLommuXuSYFLUXqaBtfzcLW71L5P8g==","X-Received":"by 10.55.111.1 with SMTP id k1mr18191912qkc.15.1505247474742;\n\tTue, 12 Sep 2017 13:17:54 -0700 (PDT)","To":"Peter Maydell ","References":"<20170912162513.21694-1-richard.henderson@linaro.org>\n\t<20170912162513.21694-8-richard.henderson@linaro.org>\n\t","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"","Date":"Tue, 12 Sep 2017 17:17:51 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::242","Subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson\n\t, QEMU Developers ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767316,"web_url":"http://patchwork.ozlabs.org/comment/1767316/","msgid":"","list_archive_url":null,"date":"2017-09-12T20:20:09","subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 12 September 2017 at 21:17, Philippe Mathieu-Daudé wrote:\n> On 09/12/2017 03:55 PM, Peter Maydell wrote:\n>>\n>> I notice we have a QEMU_ALIGNED() macro to wrap the __attribute__,\n>> though we use it less often than not at the moment...\n>\n>\n> Aesthetic aside, I find it useful to deal with the 80 characters style\n> limit.\n\nThey do say that constraints are vital for art :-)\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"LaaZILOX\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsGQM0NVQz9ryr\n\tfor ;\n\tWed, 13 Sep 2017 06:20:59 +1000 (AEST)","from localhost ([::1]:38396 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drrg1-0007Yp-7t\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 16:20:57 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:35172)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1drrfc-0007Yg-QK\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:20:33 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1drrfc-0000wk-1w\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:20:32 -0400","from mail-wr0-x235.google.com ([2a00:1450:400c:c0c::235]:33732)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1drrfb-0000vh-Rb\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:20:31 -0400","by mail-wr0-x235.google.com with SMTP id a43so24968194wrc.0\n\tfor ; Tue, 12 Sep 2017 13:20:31 -0700 (PDT)","by 10.223.130.73 with HTTP; Tue, 12 Sep 2017 13:20:09 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=SPEhGcfWV1hPKBgg8LouJia1jKDOnf4Kje3mcw/bqvs=;\n\tb=LaaZILOX8eHoKabbJgAIjl1NLExJF5BvBrTwfN/lUKQG3yLpOGti5xlghoBJndKcLM\n\ti3y1iUzdoig9jAu1RgeLC5l9+lMxASwK8/aUWu7a9iEFUz9GjjF1RFK8U+BLk0Dpx4/x\n\tW7XVo1PdKpWXJje/kBELSqNuXveFQuSGeuJV4=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=SPEhGcfWV1hPKBgg8LouJia1jKDOnf4Kje3mcw/bqvs=;\n\tb=NXZgnBCsjD+i54Uuyu6ycrhvGsnfWOGLrM08em+8uMkMUv8iNlk7Nu/r/Lapavs+GX\n\ta4tFefVwI2/yzdX71fEgGo0ZIMyXcPwzbOvP/81lqAOOpxatVUPQLLLKgewPvKsHwkfK\n\tgjsXNpyC33xTDBcmXxxK50IOU/fBYRuxpNi7m/oOOxZ3OacV/7qgWnW5DoZ76clnbTTL\n\tpQRSr+6ieE1bRzhYEjQMIfGEkiM/nBjT8Sl3O1UhBJXgB/bE35CT3o9hpPRKtjG1Jyid\n\t8X6i0G5Tsry4UnKr5o6eB73RgSMqn7M3I8nbdHwjoo/5aCkjiBky/lcfgnZdPUzVzQHO\n\tK9QA==","X-Gm-Message-State":"AHPjjUgYCKRN2Xf/0O39nIomRRqlzKQECW++9rJS64QVBrx7z3Ov8uQQ\n\t3vsXgyzPIM0b/AhSuxT4JUoMfJxb/exmocZPv3BvDQ==","X-Google-Smtp-Source":"ADKCNb5lfsWbu5MSTxVq45u6x+Aj3/iNIdxW/P04lq3QiRiRVoLWMIJi5e4OLOWr4xEFUNSSL6A+S6uF/zydvg/IKqY=","X-Received":"by 10.223.198.202 with SMTP id\n\tc10mr13329286wrh.230.1505247630763; \n\tTue, 12 Sep 2017 13:20:30 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<20170912162513.21694-1-richard.henderson@linaro.org>\n\t<20170912162513.21694-8-richard.henderson@linaro.org>\n\t\n\t","From":"Peter Maydell ","Date":"Tue, 12 Sep 2017 21:20:09 +0100","Message-ID":"","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::235","Subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"=?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson\n\t, QEMU Developers ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767327,"web_url":"http://patchwork.ozlabs.org/comment/1767327/","msgid":"","list_archive_url":null,"date":"2017-09-12T20:44:43","subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":">> -        float64 regs[64];\n>> +        float64 regs[64] __attribute__((aligned(16)));\n> \n> I understand this should be aligned to the biggest vector register the \n> host support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it \n> correct?\n> \n\nchecking datashits:\n\n\"INTEL® ADVANCED VECTOR EXTENSIONS\"\n\n2.5 MEMORY ALIGNMENT\n\nWith the exception of explicitly aligned 16 or 32 byte SIMD load/store \ninstructions, most VEX-encoded, arithmetic and data processing \ninstructions operate in a flexible environment regarding memory address \nalignment, i.e. VEX-encoded instruction with 32-byte or 16-byte load \nsemantics will support unaligned load operation by default. Memory \narguments for most instructions with VEX prefix operate normally without \ncausing #GP(0) on any byte-granularity alignment (unlike Legacy SSE \ninstructions). The instructions that require explicit memory alignment \nrequirements are listed in Table 2-4.\n\nTable 2-4. Instructions Requiring Explicitly Aligned Memory\n\nRequire 32-byte alignment:\n VMOVDQA ymm, m256\n VMOVDQA m256, ymm\n VMOVAPS ymm, m256\n VMOVAPS m256, ymm\n VMOVAPD ymm, m256\n VMOVAPD m256, ymm\n VMOVNTPS m256, ymm\n VMOVNTPD m256, ymm\n VMOVNTDQ m256, ymm\n VMOVNTDQA ymm, m256\n\nGeneral Protection, #GP(0):\n VEX.256: Memory operand is not 32-byte aligned\n VEX.128: Memory operand is not 16-byte aligned\n Legacy SSE: Memory operand is not 16-byte aligned\n\n--\n\n\"Intel® Architecture Instruction Set Extensions Programming Reference\"\n\n2.6 MEMORY ALIGNMENT\n\nMemory alignment requirements on EVEX-encoded SIMD instructions are \nsimilar to VEX-encoded SIMD instructions. Memory alignment applies to \nEVEX-encoded SIMD instructions in three categories:\n• Explicitly-aligned SIMD load and store instructions accessing 64 bytes \nof memory with EVEX prefix encoded vector length of 512 bits (e.g., \nVMOVAPD, VMOVAPS, VMOVDQA, etc.). These instructions always require\nmemory address to be aligned on 64-byte boundary.\n• Explicitly-unaligned SIMD load and store instructions accessing 64 \nbytes or less of data from memory (e.g. VMOVUPD, VMOVUPS, VMOVDQU, \nVMOVQ, VMOVD, etc.). These instructions do not require memory address\nto be aligned on natural vector-length byte boundary.\n• Most arithmetic and data processing instructions encoded using EVEX \nsupport memory access semantics. When these instructions access from \nmemory, there are no alignment restrictions.\n[...]\nAVX-512 instructions may generate an #AC(0) fault on misaligned 4 or \n8-byte memory references in Ring-3 when CR0.AM=1. 16, 32 and 64-byte \nmemory references will not generate #AC(0) fault. See Table 2-7 for details.\nCertain AVX-512 Foundation instructions always require 64-byte alignment \n(see the complete list of VEX and EVEX encoded instructions in Table \n2-6). These instructions will #GP(0) if not aligned to 64-byte boundaries.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"Tz0whL4B\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsH6h1lKQz9s4s\n\tfor ;\n\tWed, 13 Sep 2017 06:52:28 +1000 (AEST)","from localhost ([::1]:38555 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1drsAU-0004qA-DM\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 16:52:26 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:45044)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from )\n\tid 1drs3A-0007Yu-5d\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:44:53 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from )\n\tid 1drs35-0004FX-U6\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:44:52 -0400","from mail-qt0-x229.google.com ([2607:f8b0:400d:c0d::229]:33185)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1drs35-0004Ex-Qe\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 16:44:47 -0400","by mail-qt0-x229.google.com with SMTP id i50so28406363qtf.0\n\tfor ; Tue, 12 Sep 2017 13:44:47 -0700 (PDT)","from [192.168.1.10] ([181.93.89.178])\n\tby smtp.gmail.com with ESMTPSA id\n\tc38sm8618136qtc.18.2017.09.12.13.44.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 13:44:46 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:subject:from:to:cc:references:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=gVwWcIEDDp37i1OUT6op3fhJVMDJ01VcBRs8ajgCPco=;\n\tb=Tz0whL4BgwoAfSLt1R2KDxiB+R5HbY5wLoJA4eRGgGcCaT6Ff8hhAzAJ3QS5NrWpz7\n\tSJQhqtjY9sp9nBRpFsT/xzMnvXOfVZf2Bobb0z9s6KCZFYceTj+BV9aW5+VQIa06aPJ9\n\twKKSTfA0R+xWce1eF75+WH5Gr3bWVbe+jBGrndmUaYC93xURyaFq02EaSfXC2UjC5me1\n\tpx0Lnf8WQb6Vf84CVCfBFcyAWlSZC/REDGy33vl3vWiA2Oe8NnAFZCQqIlSh87rIb5sd\n\tZN1ZHR2hsynAXe/UyfnyxqsXcAUSKLmWIo2bI1nRW3hZNr6gkTzdnTJ6gIfDW614SsWl\n\tQ+yQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:subject:from:to:cc:references:message-id\n\t:date:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=gVwWcIEDDp37i1OUT6op3fhJVMDJ01VcBRs8ajgCPco=;\n\tb=IktUvxaPvozOs3dJ17BgdhSP4lXX18t3Kwbq3Ei8G7HcnAOtK/HzM0WnjR4iJYLVDC\n\tQYsbe3LLbnPG3VT8yuEsWM7JB5kTLscxXD4gsnFDqExnXS4daqehaeU06knJIwFpPGb3\n\tOiG5KR/zK2Gzyr1m/A1zWLa3q905qTjb6CoumKk3MMOMqg8iE/YoIdz7oWXLzPGv4WVa\n\tOgDzQGDCmBQDteYGn4ukrgqnUh3stbmXZCRkk8N9BIGmVbwdXcAQQHfgMnngVIe2kXMR\n\t+E5FElRwsyWlEsBK1KBUu1d3J4SUBlwFVjOg/es4ctptqIdyf0mwLVGe81T3Ez/cK5ev\n\tCCXg==","X-Gm-Message-State":"AHPjjUiCA2LJeC8FBySInKGS4YZg9JELCOkQoRFTNe1/Q55JeYP2Q4vL\n\tZIPXdv30Qtzpqw==","X-Google-Smtp-Source":"AOwi7QDJEtqhi4Myqe8Ayr5EpfNHpOSdCg/0LC68Zujhh+IzPT1T7HinUHfRMcjouBkTx7xaJ1Ym+w==","X-Received":"by 10.200.53.67 with SMTP id z3mr24252319qtb.145.1505249087162; \n\tTue, 12 Sep 2017 13:44:47 -0700 (PDT)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"Richard Henderson , qemu-devel@nongnu.org","References":"<20170912162513.21694-1-richard.henderson@linaro.org>\n\t<20170912162513.21694-8-richard.henderson@linaro.org>\n\t","Message-ID":"","Date":"Tue, 12 Sep 2017 17:44:43 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::229","Subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alex.bennee@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1767970,"web_url":"http://patchwork.ozlabs.org/comment/1767970/","msgid":"<4262b16c-fd18-b551-a510-30833df414ad@linaro.org>","list_archive_url":null,"date":"2017-09-13T15:28:28","subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/12/2017 11:50 AM, Philippe Mathieu-Daudé wrote:\n>>\n>> -        float64 regs[64];\n>> +        float64 regs[64] __attribute__((aligned(16)));\n> \n> I understand this should be aligned to the biggest vector register the host\n> support, i.e. for AVX-512 this would be QEMU_ALIGNED(64), is it correct?\n\nNo.\n\nAlignment of 16 is sufficient for \"older\" vector extensions, like altivec,\nwhich require alignment in load/store insns. But (so far at least) newer\nvector extensions with larger vector sizes (AVX2, AVX512, ARM SVE) handle\nunaligned load/store operations just fine.\n\nWhich means we need not require excessive alignment within the cpu struct.\n\nThe rule for this is documented in tcg/tcg-op-gvec.h, iirc.\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"T2KkJbiH\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xslv873JJz9s7v\n\tfor ;\n\tThu, 14 Sep 2017 01:29:07 +1000 (AEST)","from localhost ([::1]:43064 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1ds9b7-0005lK-8E\n\tfor incoming@patchwork.ozlabs.org; Wed, 13 Sep 2017 11:29:05 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:33057)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1ds9ae-0005k8-RX\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 11:28:37 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1ds9aZ-0001rt-UE\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 11:28:36 -0400","from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]:46876)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1ds9aZ-0001rV-NI\n\tfor qemu-devel@nongnu.org; Wed, 13 Sep 2017 11:28:31 -0400","by mail-pf0-x229.google.com with SMTP id e199so789018pfh.3\n\tfor ; Wed, 13 Sep 2017 08:28:31 -0700 (PDT)","from bigtime.twiddle.net (97-126-103-167.tukw.qwest.net.\n\t[97.126.103.167]) by smtp.gmail.com with ESMTPSA id\n\tj68sm23315188pfa.93.2017.09.13.08.28.29\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tWed, 13 Sep 2017 08:28:29 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=07XpeYvZ0QGIsqCfUmBvAXfw0cqhyv76TOJn/2cfI+k=;\n\tb=T2KkJbiHCZ9zthranfmNsvWMKW22QVG1hRffRFbU51JeB6khEt+HJWX4JtGRUhnIr1\n\tb3U4QkmSYffGpaiOEK8Yg3Wz7KgV0qAVUdLbbd/r2IGliZWxINw5zQETGQirfIftxZUw\n\t79eqqXYtrtG9wjzy/uy7KR3iPzi8o7SoalRbU=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=07XpeYvZ0QGIsqCfUmBvAXfw0cqhyv76TOJn/2cfI+k=;\n\tb=OCL9IQMcGHdWu4kl/ASGjlUSSQBRWcuij1OQzYturRW85YhfrXXDgTHHVy8Z+WlrT9\n\t7rUkA2rh8ZyHIT1cOP9NBnI0VBaLYAieyB6UGOXJmpihqtSevpwLJI+dsmQqR3sJ/KlU\n\tWG8a5tnffiOKiq9ih370heMzdtkntMtTTV4iNHLn15EhjFG7UeY+Q6knny8RIC8BEja5\n\tI+KZzVN4aqdsBWBjWTZ7H78vKAolbj3Y3yeAR2eb4DkFS5CSWE9VabnJwB4caX4hHoPp\n\tPlNGJGeQImhamQ9P1Rn1cqExjg4hOftKT1egneKoyWCsaloeR1OkeevPqZ5bcwxRZopO\n\tYX8w==","X-Gm-Message-State":"AHPjjUjrivSH6hKoS5vnXgKHdU5Oha4P/6wklSaXoNqVoQ/lx24Ad2f7\n\t0qVEP4rvqSa6KqAp","X-Google-Smtp-Source":"ADKCNb5DXkvYRQHIp9si/myDdaiFF+di06UC01uDTRShDS4YrPvDMID6uXbffCVuN3wyIkyPeO2koQ==","X-Received":"by 10.84.232.11 with SMTP id h11mr20321391plk.65.1505316510798; \n\tWed, 13 Sep 2017 08:28:30 -0700 (PDT)","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tqemu-devel@nongnu.org","References":"<20170912162513.21694-1-richard.henderson@linaro.org>\n\t<20170912162513.21694-8-richard.henderson@linaro.org>\n\t","From":"Richard Henderson ","Message-ID":"<4262b16c-fd18-b551-a510-30833df414ad@linaro.org>","Date":"Wed, 13 Sep 2017 08:28:28 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::229","Subject":"Re: [Qemu-devel] [PATCH v2 07/16] target/arm: Align vector registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alex.bennee@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]