[{"id":1767689,"web_url":"http://patchwork.ozlabs.org/comment/1767689/","msgid":"<59B8F42A.3050906@foss.arm.com>","list_archive_url":null,"date":"2017-09-13T09:02:34","subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","submitter":{"id":66284,"url":"http://patchwork.ozlabs.org/api/people/66284/","name":"Kyrill Tkachov","email":"kyrylo.tkachov@foss.arm.com"},"content":"Hi Charles,\n\nOn 12/09/17 09:34, charles.baylis@linaro.org wrote:\n> From: Charles Baylis \n>\n> Add bus widths. These use the approximation that v7 and later cores have\n> 64bit data bus width, and earlier cores have 32 bit bus width, with the\n> exception of v7m.\n>\n\nGiven the way this field is used in patch 2 does it affect the \naddressing mode generation\nin the tests you added depending on the -mtune option given?\nIf so, we'll get testsuite failures when people test with particular \ndefault CPU configurations.\n\nCould you expand on the benefits we get from this extra bus_width \ninformation?\nI get that we increase the cost of memory accesses if the size of the \nmode we load is larger than the\nbus width, but it's not as if there is ever an alternative in this \nregard, such as loading less memory,\nso what pass can make different decisions thanks to this field?\n\nThanks,\nKyrill\n\n> Charles Baylis \n>\n> * config/arm/arm-protos.h (struct tune_params): New field\n> bus_width.\n> * config/arm/arm.c (arm_slowmul_tune): Initialise bus_width field.\n> (arm_fastmul_tune): Likewise.\n> (arm_strongarm_tune): Likewise.\n> (arm_xscale_tune): Likewise.\n> (arm_9e_tune): Likewise.\n> (arm_marvell_pj4_tune): Likewise.\n> (arm_v6t2_tune): Likewise.\n> (arm_cortex_tune): Likewise.\n> (arm_cortex_a8_tune): Likewise.\n> (arm_cortex_a7_tune): Likewise.\n> (arm_cortex_a15_tune): Likewise.\n> (arm_cortex_a35_tune): Likewise.\n> (arm_cortex_a53_tune): Likewise.\n> (arm_cortex_a57_tune): Likewise.\n> (arm_exynosm1_tune): Likewise.\n> (arm_xgene1_tune): Likewise.\n> (arm_cortex_a5_tune): Likewise.\n> (arm_cortex_a9_tune): Likewise.\n> (arm_cortex_a12_tune): Likewise.\n> (arm_cortex_a73_tune): Likewise.\n> (arm_v7m_tune): Likewise.\n> (arm_cortex_m7_tune): Likewise.\n> (arm_v6m_tune): Likewise.\n> (arm_fa726te_tune): Likewise.\n>\n> Change-Id: I613e876db93ffd6f8c1e72ba483be2efc0b56d66\n> ---\n> gcc/config/arm/arm-protos.h | 2 ++\n> gcc/config/arm/arm.c | 24 ++++++++++++++++++++++++\n> 2 files changed, 26 insertions(+)\n>\n> diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\n> index 4538078..47a85cc 100644\n> --- a/gcc/config/arm/arm-protos.h\n> +++ b/gcc/config/arm/arm-protos.h\n> @@ -278,6 +278,8 @@ struct tune_params\n> int max_insns_inline_memset;\n> /* Issue rate of the processor. */\n> unsigned int issue_rate;\n> + /* Bus width (bits). */\n> + unsigned int bus_width;\n> /* Explicit prefetch data. */\n> struct\n> {\n> diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\n> index bca8a34..32001e5 100644\n> --- a/gcc/config/arm/arm.c\n> +++ b/gcc/config/arm/arm.c\n> @@ -1761,6 +1761,7 @@ const struct tune_params arm_slowmul_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1783,6 +1784,7 @@ const struct tune_params arm_fastmul_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1808,6 +1810,7 @@ const struct tune_params arm_strongarm_tune =\n> 3, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1830,6 +1833,7 @@ const struct tune_params arm_xscale_tune =\n> 3, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1852,6 +1856,7 @@ const struct tune_params arm_9e_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1874,6 +1879,7 @@ const struct tune_params arm_marvell_pj4_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1896,6 +1902,7 @@ const struct tune_params arm_v6t2_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1920,6 +1927,7 @@ const struct tune_params arm_cortex_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1942,6 +1950,7 @@ const struct tune_params arm_cortex_a8_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1964,6 +1973,7 @@ const struct tune_params arm_cortex_a7_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -1986,6 +1996,7 @@ const struct tune_params arm_cortex_a15_tune =\n> 2, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 3, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_TRUE,\n> @@ -2008,6 +2019,7 @@ const struct tune_params arm_cortex_a35_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2030,6 +2042,7 @@ const struct tune_params arm_cortex_a53_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2052,6 +2065,7 @@ const struct tune_params arm_cortex_a57_tune =\n> 2, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 3, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_TRUE,\n> @@ -2074,6 +2088,7 @@ const struct tune_params arm_exynosm1_tune =\n> 2, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 3, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_TRUE,\n> @@ -2096,6 +2111,7 @@ const struct tune_params arm_xgene1_tune =\n> 2, /* Max cond insns. */\n> 32, /* Memset max inline. */\n> 4, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_TRUE,\n> @@ -2121,6 +2137,7 @@ const struct tune_params arm_cortex_a5_tune =\n> 1, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2143,6 +2160,7 @@ const struct tune_params arm_cortex_a9_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_BENEFICIAL(4,32,32),\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2165,6 +2183,7 @@ const struct tune_params arm_cortex_a12_tune =\n> 2, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_TRUE,\n> @@ -2187,6 +2206,7 @@ const struct tune_params arm_cortex_a73_tune =\n> 2, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_TRUE,\n> @@ -2216,6 +2236,7 @@ const struct tune_params arm_v7m_tune =\n> 2, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2240,6 +2261,7 @@ const struct tune_params arm_cortex_m7_tune =\n> 1, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 64, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2265,6 +2287,7 @@ const struct tune_params arm_v6m_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 1, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_FALSE,\n> tune_params::PREF_LDRD_FALSE,\n> @@ -2287,6 +2310,7 @@ const struct tune_params arm_fa726te_tune =\n> 5, /* Max cond insns. */\n> 8, /* Memset max inline. */\n> 2, /* Issue rate. */\n> + 32, /* Bus width. */\n> ARM_PREFETCH_NOT_BENEFICIAL,\n> tune_params::PREF_CONST_POOL_TRUE,\n> tune_params::PREF_LDRD_FALSE,\n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462003-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"oL8+FdBu\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsbKb6RN5z9sMN\n\tfor ;\n\tWed, 13 Sep 2017 19:02:59 +1000 (AEST)","(qmail 17070 invoked by alias); 13 Sep 2017 09:02:46 -0000","(qmail 16986 invoked by uid 89); 13 Sep 2017 09:02:41 -0000","from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tWed, 13 Sep 2017 09:02:39 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\t1B4151529; Wed, 13 Sep 2017 02:02:37 -0700 (PDT)","from [10.2.207.77] (e100706-lin.cambridge.arm.com\n\t[10.2.207.77])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id EC5583F483; Wed, 13 Sep 2017 02:02:35 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:message-id:date:from:mime-version:to:cc:subject:references\n\t:in-reply-to:content-type:content-transfer-encoding; q=dns; s=\n\tdefault; b=AfAw6NlfFxatGKh1Za88j2GX4Ru7QdQ3lqSdJPOr4Hcjb7vbHqVd/\n\tTe2LtNdhRAx3ulRqhPWTISISpMmwXZGV1UJKCOVr7vevjlX2ssavHi6vjoQlT0Tz\n\tcFcG5HB63cwyzl+g+6Gq7JswlnBtK8pgI0lZR+wWvrIUgC0meGx5A8=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:message-id:date:from:mime-version:to:cc:subject:references\n\t:in-reply-to:content-type:content-transfer-encoding; s=default;\n\tbh=4d2JHxcYQlL4FlnA8URWgK4FhWE=; b=oL8+FdBuKOziV2SajABs8L7j7izq\n\t/lE7R6z9Ee4EPutg7w+FdexTwp8f7j0UXZ6pQM9xLTbf9dggmFMW65lBNiWPUHIU\n\t+dlIcNlSE7jiqojRibkFmnug5spCpuhTZV6UXVC1EvqfBg1KcXM4BkiCR64Smxv+\n\tA1yEeprBouSMolg=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-25.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","Message-ID":"<59B8F42A.3050906@foss.arm.com>","Date":"Wed, 13 Sep 2017 10:02:34 +0100","From":"Kyrill Tkachov ","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:31.0) Gecko/20100101 Thunderbird/31.2.0","MIME-Version":"1.0","To":"\"charles.baylis@linaro.org\" ,\n\tRichard Earnshaw ,\n\tRamana Radhakrishnan ,\n\t\"pinskia@gmail.com\" ","CC":"\"gcc-patches@gcc.gnu.org\" ","Subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>\n\t<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>","In-Reply-To":"<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":1769258,"web_url":"http://patchwork.ozlabs.org/comment/1769258/","msgid":"","list_archive_url":null,"date":"2017-09-15T15:38:25","subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","submitter":{"id":35578,"url":"http://patchwork.ozlabs.org/api/people/35578/","name":"Charles Baylis","email":"charles.baylis@linaro.org"},"content":"On 13 September 2017 at 10:02, Kyrill Tkachov\n wrote:\n> Hi Charles,\n>\n> On 12/09/17 09:34, charles.baylis@linaro.org wrote:\n>>\n>> From: Charles Baylis \n>>\n>> Add bus widths. These use the approximation that v7 and later cores have\n>> 64bit data bus width, and earlier cores have 32 bit bus width, with the\n>> exception of v7m.\n>>\n>\n> Given the way this field is used in patch 2 does it affect the addressing\n> mode generation\n> in the tests you added depending on the -mtune option given?\n> If so, we'll get testsuite failures when people test with particular default\n> CPU configurations.\n\nNo, because the auto_inc_dec phase compares the cost of two different\nMEMs which differ only by addressing mode. The part of the calculation\nwhich depends on the bus_width is the same both times, so it is\ncancelled out.\n\n> Could you expand on the benefits we get from this extra bus_width\n> information?\n> I get that we increase the cost of memory accesses if the size of the mode\n> we load is larger than the\n> bus width, but it's not as if there is ever an alternative in this regard,\n> such as loading less memory,\n> so what pass can make different decisions thanks to this field?\n\nAs far as this patch series is concerned, it doesn't matter. It is\nthere to encapsulate the notion that a larger transfer results in\nrtx_costs() returning a larger cost, but I don't know of any part of\nthe compiler which is sensitive to that difference. It's done this way\nbecause Ramana and Richard wanted it done that way\n(https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00652.html).\nFrom b7bec2e4f7ca0335e0e5bd84c297215a3a7fb8c7 Mon Sep 17 00:00:00 2001\nFrom: Charles Baylis \nDate: Fri, 8 Sep 2017 12:53:50 +0100\nSubject: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params\n\nAdd bus widths. These use the approximation that v7 and later cores have\n64bit data bus width, and earlier cores have 32 bit bus width, with the\nexception of v7m.\n\n Charles Baylis \n\n\t* config/arm/arm-protos.h (struct tune_params): New field\n\tbus_width.\n\t* config/arm/arm.c (arm_slowmul_tune): Initialise bus_width field.\n\t(arm_fastmul_tune): Likewise.\n\t(arm_strongarm_tune): Likewise.\n\t(arm_xscale_tune): Likewise.\n\t(arm_9e_tune): Likewise.\n\t(arm_marvell_pj4_tune): Likewise.\n\t(arm_v6t2_tune): Likewise.\n\t(arm_cortex_tune): Likewise.\n\t(arm_cortex_a8_tune): Likewise.\n\t(arm_cortex_a7_tune): Likewise.\n\t(arm_cortex_a15_tune): Likewise.\n\t(arm_cortex_a35_tune): Likewise.\n\t(arm_cortex_a53_tune): Likewise.\n\t(arm_cortex_a57_tune): Likewise.\n\t(arm_exynosm1_tune): Likewise.\n\t(arm_xgene1_tune): Likewise.\n\t(arm_cortex_a5_tune): Likewise.\n\t(arm_cortex_a9_tune): Likewise.\n\t(arm_cortex_a12_tune): Likewise.\n\t(arm_cortex_a73_tune): Likewise.\n\t(arm_v7m_tune): Likewise.\n\t(arm_cortex_m7_tune): Likewise.\n\t(arm_v6m_tune): Likewise.\n\t(arm_fa726te_tune): Likewise.\n\nChange-Id: I613e876db93ffd6f8c1e72ba483be2efc0b56d66\n---\n gcc/config/arm/arm-protos.h | 2 ++\n gcc/config/arm/arm.c | 24 ++++++++++++++++++++++++\n 2 files changed, 26 insertions(+)\n\ndiff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h\nindex 4538078..47a85cc 100644\n--- a/gcc/config/arm/arm-protos.h\n+++ b/gcc/config/arm/arm-protos.h\n@@ -278,6 +278,8 @@ struct tune_params\n int max_insns_inline_memset;\n /* Issue rate of the processor. */\n unsigned int issue_rate;\n+ /* Bus width (bits). */\n+ unsigned int bus_width;\n /* Explicit prefetch data. */\n struct\n {\ndiff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c\nindex bca8a34..32001e5 100644\n--- a/gcc/config/arm/arm.c\n+++ b/gcc/config/arm/arm.c\n@@ -1761,6 +1761,7 @@ const struct tune_params arm_slowmul_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1783,6 +1784,7 @@ const struct tune_params arm_fastmul_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1808,6 +1810,7 @@ const struct tune_params arm_strongarm_tune =\n 3,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1830,6 +1833,7 @@ const struct tune_params arm_xscale_tune =\n 3,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1852,6 +1856,7 @@ const struct tune_params arm_9e_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1874,6 +1879,7 @@ const struct tune_params arm_marvell_pj4_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1896,6 +1902,7 @@ const struct tune_params arm_v6t2_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1920,6 +1927,7 @@ const struct tune_params arm_cortex_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1942,6 +1950,7 @@ const struct tune_params arm_cortex_a8_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1964,6 +1973,7 @@ const struct tune_params arm_cortex_a7_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -1986,6 +1996,7 @@ const struct tune_params arm_cortex_a15_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 3,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2008,6 +2019,7 @@ const struct tune_params arm_cortex_a35_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2030,6 +2042,7 @@ const struct tune_params arm_cortex_a53_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2052,6 +2065,7 @@ const struct tune_params arm_cortex_a57_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 3,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2074,6 +2088,7 @@ const struct tune_params arm_exynosm1_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 3,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2096,6 +2111,7 @@ const struct tune_params arm_xgene1_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 32,\t\t\t\t\t\t/* Memset max inline. */\n 4,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2121,6 +2137,7 @@ const struct tune_params arm_cortex_a5_tune =\n 1,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2143,6 +2160,7 @@ const struct tune_params arm_cortex_a9_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_BENEFICIAL(4,32,32),\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2165,6 +2183,7 @@ const struct tune_params arm_cortex_a12_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2187,6 +2206,7 @@ const struct tune_params arm_cortex_a73_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_TRUE,\n@@ -2216,6 +2236,7 @@ const struct tune_params arm_v7m_tune =\n 2,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2240,6 +2261,7 @@ const struct tune_params arm_cortex_m7_tune =\n 1,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 64,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2265,6 +2287,7 @@ const struct tune_params arm_v6m_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 1,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_FALSE,\n tune_params::PREF_LDRD_FALSE,\n@@ -2287,6 +2310,7 @@ const struct tune_params arm_fa726te_tune =\n 5,\t\t\t\t\t\t/* Max cond insns. */\n 8,\t\t\t\t\t\t/* Memset max inline. */\n 2,\t\t\t\t\t\t/* Issue rate. */\n+ 32,\t\t\t\t\t\t/* Bus width. */\n ARM_PREFETCH_NOT_BENEFICIAL,\n tune_params::PREF_CONST_POOL_TRUE,\n tune_params::PREF_LDRD_FALSE,","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462260-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"WHjrr5YM\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xv01T2pQPz9sPr\n\tfor ;\n\tSat, 16 Sep 2017 01:38:53 +1000 (AEST)","(qmail 7774 invoked by alias); 15 Sep 2017 15:38:32 -0000","(qmail 7028 invoked by uid 89); 15 Sep 2017 15:38:31 -0000","from mail-io0-f176.google.com (HELO mail-io0-f176.google.com)\n\t(209.85.223.176) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tFri, 15 Sep 2017 15:38:28 +0000","by mail-io0-f176.google.com with SMTP id e189so9436348ioa.4 for\n\t; Fri, 15 Sep 2017 08:38:28 -0700 (PDT)","by 10.2.96.106 with HTTP; Fri, 15 Sep 2017 08:38:25 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; q=dns; s=default; b=fZSxUrRuh0T6FhO\n\tRGx1PqLMOGwQ7aanH5/lRreWi0MMAHtRcFNVasumUGTBOOWYjRqvhm2WIWE6Vhex\n\tT6EnBTExBJYtHwVO9CYyi7znClNkoGYjgYJ1bkPf6H/IkxqAY5D7DDjc8w6t3d/L\n\t/sXmHddpoTTWbPmUDJt3SzKkL/mE=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; s=default; bh=kpMxqhsWE+CEava17rUxr\n\tT8E+Y4=; b=WHjrr5YMH92JGNKmAuMw8NBSetoaeU5VWzHA5b5MsP8TKp+cn2+e6\n\tz3Uhp9F4hAse8oNLPGBf3qqMBahBIac8PamxkuUro12EOm/ep/ATLgZHJEojGlLf\n\tkEuHf5f4aKDymeLGJxxWA2J10MXFGsAdb98xD39taNdT8CPavcd2XI=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-23.9 required=5.0 tests=AWL, BAYES_00,\n\tGIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"mail-io0-f176.google.com","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=XKjtvZ8mXfZWG680ST8Xb0/svISPEZTVGmUK7TNfSTo=;\n\tb=Wb8IlZxqiz3QE0e/lAdkugHFAd1AV+JIP2uwK4UqqlYT57GX62/kR7tERgfpTbqepv\n\tc3YsZtCJLiPWtspvddrKaSZ8kzZKAy1JTWbC5tCoHb1uB3/hqQUDm0oKkw4tdMOXrXNX\n\tBi/QG60JNG8qBoxnvtIuZztvs5WeiFKe3U3/xh11FIK5451EzAZz/iQc8ihqA8CH57PQ\n\tl8g2x1aP/FVsVwxO12FV8f5+c3pYjdjDhatvlk+zWXCWB8Y68Rrc/aeYi0r2vnFW3cr4\n\tDvfs+ECxOytgwqnLPuMZFaryT8jkpDwG7GdicZuQnaQO4GdA3IiJ8f1r9slpRm1dxRRk\n\th8ew==","X-Gm-Message-State":"AHPjjUio4TnLUfWzuZy44Eg4Yv2pFGXW53MT1sZJ1SoZ0rlD7uYeqL2c\tWu46/ngeuK0bTW+QquMtncqUWwizWcEXHYS5u2Y+oA==","X-Google-Smtp-Source":"AOwi7QDoauSfvW2/neSQ1HNAxO/nM3R8VDGODP6mREy51rc43qWz2gNFy+ytfZDqkYha9GCEkkUdNGDyWZz2fisiCBE=","X-Received":"by 10.107.163.9 with SMTP id m9mr8059871ioe.230.1505489906475;\n\tFri, 15 Sep 2017 08:38:26 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<59B8F42A.3050906@foss.arm.com>","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>\n\t<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>\n\t<59B8F42A.3050906@foss.arm.com>","From":"Charles Baylis ","Date":"Fri, 15 Sep 2017 16:38:25 +0100","Message-ID":"","Subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","To":"Kyrill Tkachov ","Cc":"Richard Earnshaw ,\n\tRamana Radhakrishnan ,\n\t\"pinskia@gmail.com\" ,\n\t\"gcc-patches@gcc.gnu.org\" ","Content-Type":"multipart/mixed; boundary=\"001a1140ff9a173e6a05593c2fb0\"","X-IsSubscribed":"yes"}},{"id":1769307,"web_url":"http://patchwork.ozlabs.org/comment/1769307/","msgid":"<59BC0755.9050205@foss.arm.com>","list_archive_url":null,"date":"2017-09-15T17:01:09","subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","submitter":{"id":66284,"url":"http://patchwork.ozlabs.org/api/people/66284/","name":"Kyrill Tkachov","email":"kyrylo.tkachov@foss.arm.com"},"content":"On 15/09/17 16:38, Charles Baylis wrote:\n> On 13 September 2017 at 10:02, Kyrill Tkachov\n> wrote:\n>> Hi Charles,\n>>\n>> On 12/09/17 09:34, charles.baylis@linaro.org wrote:\n>>> From: Charles Baylis \n>>>\n>>> Add bus widths. These use the approximation that v7 and later cores have\n>>> 64bit data bus width, and earlier cores have 32 bit bus width, with the\n>>> exception of v7m.\n>>>\n>> Given the way this field is used in patch 2 does it affect the addressing\n>> mode generation\n>> in the tests you added depending on the -mtune option given?\n>> If so, we'll get testsuite failures when people test with particular default\n>> CPU configurations.\n> No, because the auto_inc_dec phase compares the cost of two different\n> MEMs which differ only by addressing mode. The part of the calculation\n> which depends on the bus_width is the same both times, so it is\n> cancelled out.\n>\n>> Could you expand on the benefits we get from this extra bus_width\n>> information?\n>> I get that we increase the cost of memory accesses if the size of the mode\n>> we load is larger than the\n>> bus width, but it's not as if there is ever an alternative in this regard,\n>> such as loading less memory,\n>> so what pass can make different decisions thanks to this field?\n> As far as this patch series is concerned, it doesn't matter. It is\n> there to encapsulate the notion that a larger transfer results in\n> rtx_costs() returning a larger cost, but I don't know of any part of\n> the compiler which is sensitive to that difference. It's done this way\n> because Ramana and Richard wanted it done that way\n> (https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00652.html).\n\n From what I can tell Ramana and Richard preferred to encode this \nattribute as\na tuning struct property rather than an inline conditional based on \narm_arch7.\nI agree that if we want to use that information, it should be encoded \nthis way.\nWhat I'm not convinced about is whether we do want this parameter in the \nfirst place.\n\nThe cost tables already encode information about the costs of different \nsized loads/stores.\nIn patch 2, for example, you add the cost for extra_cost->ldst.load \nwhich is nominally just\nthe cost of a normal 32-bit ldr. But we also have costs for ldst.ldrd \nwhich is the 64-bit two-register load\nwhich should reflect any extra cost due to a narrower bus in it. We also \nhave costs for ldst.loadf (for 32-bit\nVFP loads) and ldst.loadd (for 64-bit VFP D-register loads). So I think \nwe should use those cost fields\ndepending on the mode class and size instead of using ldst.load \nunconditionally and adding a new bus_size parameter.\n\nSo I think the way forward is to drop this patch and modify patch 2/3 to \nuse the extra_cost->ldst fields as described above.\n\nSorry for the back-and-forth. I think this is the best approach because \nit uses the existing fields more naturally and\ndoesn't add new parameters that partly duplicate the information encoded \nin the existing fields.\nRamana, Richard: if you prefer the bus_width approach I won't block it, \nbut could you clarify your preference?\nIf we do end up adding the bus_width parameter then this patch and patch \n2/3 look ok.\nThanks,\nKyrill\n\nP.S. I'm going on a 4-week holiday from today, so I won't be able to do \nany further review in that timeframe.\nAs I said, if we go with the bus_size approach then these patches are \nok. If we go with my suggestion, this would\nbe dropped and patch 2 would be extended to select the appropriate \nextra_cost->ldst field depending on mode.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-462287-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"RupCAvCe\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xv1rf3x2Mz9s7m\n\tfor ;\n\tSat, 16 Sep 2017 03:01:22 +1000 (AEST)","(qmail 57012 invoked by alias); 15 Sep 2017 17:01:15 -0000","(qmail 57002 invoked by uid 89); 15 Sep 2017 17:01:14 -0000","from usa-sjc-mx-foss1.foss.arm.com (HELO foss.arm.com)\n\t(217.140.101.70) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tFri, 15 Sep 2017 17:01:13 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\tby\n\tusa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id\n\t3A9011529; Fri, 15 Sep 2017 10:01:12 -0700 (PDT)","from [10.2.207.77] (e100706-lin.cambridge.arm.com\n\t[10.2.207.77])\tby usa-sjc-imap-foss1.foss.arm.com (Postfix)\n\twith ESMTPSA id 44D763F3E1; Fri, 15 Sep 2017 10:01:11 -0700 (PDT)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:message-id:date:from:mime-version:to:cc:subject:references\n\t:in-reply-to:content-type:content-transfer-encoding; q=dns; s=\n\tdefault; b=XbTJo48W3mwHQa3w4iDi5CtZFBxtGG+Gkgu3sgz210RetLxkCaGDp\n\t0NirYIG0MdUT5rJmzOueeJ+uaUTC21nxXqnxQDz5f1hK6RQ1rsnQcwO8ffDIIGfc\n\tSddtq4qAInXRQL8DzkbbzQwI42cMbSoXvWw84ydD0et2fngflUeFoA=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:message-id:date:from:mime-version:to:cc:subject:references\n\t:in-reply-to:content-type:content-transfer-encoding; s=default;\n\tbh=G9ZekRMIv73gIeAm4ULvzUNDb1w=; b=RupCAvCeImX/tu0SvNz2SCMZOGoK\n\t5zbXeg1pc5LyAXhMzdSXyF/HQnviAGzqXRHORWF10rQlZlgiN8AREZvKQsHI3C7R\n\t/tLlYAS+coClYt6NdpnTkOoMFzZVFSmYgumQ+dohuy7mKzyyDLL+aYLrDypLLnaH\n\tK++MHHF+If4hCPo=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-0.9 required=5.0 tests=BAYES_00,\n\tKAM_LAZY_DOMAIN_SECURITY,\n\tRP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=holiday,\n\tconvinced, Hx-languages-length:3592","X-HELO":"foss.arm.com","Message-ID":"<59BC0755.9050205@foss.arm.com>","Date":"Fri, 15 Sep 2017 18:01:09 +0100","From":"Kyrill Tkachov ","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:31.0) Gecko/20100101 Thunderbird/31.2.0","MIME-Version":"1.0","To":"Charles Baylis ","CC":"Richard Earnshaw ,\n\tRamana Radhakrishnan ,\n\t\"pinskia@gmail.com\" ,\n\t\"gcc-patches@gcc.gnu.org\" ","Subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>\n\t<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>\n\t<59B8F42A.3050906@foss.arm.com>\n\t","In-Reply-To":"","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit"}},{"id":1807707,"web_url":"http://patchwork.ozlabs.org/comment/1807707/","msgid":"","list_archive_url":null,"date":"2017-11-20T21:10:04","subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","submitter":{"id":35578,"url":"http://patchwork.ozlabs.org/api/people/35578/","name":"Charles Baylis","email":"charles.baylis@linaro.org"},"content":"On 15 September 2017 at 18:01, Kyrill Tkachov\n wrote:\n\n> From what I can tell Ramana and Richard preferred to encode this attribute\n> as\n> a tuning struct property rather than an inline conditional based on\n> arm_arch7.\n> I agree that if we want to use that information, it should be encoded this\n> way.\n> What I'm not convinced about is whether we do want this parameter in the\n> first place.\n>\n> The cost tables already encode information about the costs of different\n> sized loads/stores.\n> In patch 2, for example, you add the cost for extra_cost->ldst.load which is\n> nominally just\n> the cost of a normal 32-bit ldr. But we also have costs for ldst.ldrd which\n> is the 64-bit two-register load\n> which should reflect any extra cost due to a narrower bus in it. We also\n> have costs for ldst.loadf (for 32-bit\n> VFP loads) and ldst.loadd (for 64-bit VFP D-register loads). So I think we\n> should use those cost fields\n> depending on the mode class and size instead of using ldst.load\n> unconditionally and adding a new bus_size parameter.\n>\n> So I think the way forward is to drop this patch and modify patch 2/3 to use\n> the extra_cost->ldst fields as described above.\n>\n> Sorry for the back-and-forth. I think this is the best approach because it\n> uses the existing fields more naturally and\n> doesn't add new parameters that partly duplicate the information encoded in\n> the existing fields.\n> Ramana, Richard: if you prefer the bus_width approach I won't block it, but\n> could you clarify your preference?\n> If we do end up adding the bus_width parameter then this patch and patch 2/3\n> look ok.\n> Thanks,\n> Kyrill\n>\n> P.S. I'm going on a 4-week holiday from today, so I won't be able to do any\n> further review in that timeframe.\n> As I said, if we go with the bus_size approach then these patches are ok. If\n> we go with my suggestion, this would\n> be dropped and patch 2 would be extended to select the appropriate\n> extra_cost->ldst field depending on mode.\n\nOK, I agree with dropping this patch. I have posted an updated patch 2\nwhich does not require it.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-467481-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"PD4gP7ny\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yghFN6WDxz9sRW\n\tfor ;\n\tTue, 21 Nov 2017 08:10:16 +1100 (AEDT)","(qmail 75661 invoked by alias); 20 Nov 2017 21:10:08 -0000","(qmail 75630 invoked by uid 89); 20 Nov 2017 21:10:07 -0000","from mail-yw0-f170.google.com (HELO mail-yw0-f170.google.com)\n\t(209.85.161.170) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tMon, 20 Nov 2017 21:10:06 +0000","by mail-yw0-f170.google.com with SMTP id t4so3234280ywf.7 for\n\t; Mon, 20 Nov 2017 13:10:06 -0800 (PST)","by 10.129.182.1 with HTTP; Mon, 20 Nov 2017 13:10:04 -0800 (PST)"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; q=dns; s=default; b=xYEJZ+CK+acDQgp\n\tbxHP5yC1Ttti+hH3T4ICkvbGmVnFSMaB2gBvg2HJi/sFasGlfe1aibj5gEF6dyc5\n\t4b4vuz/93HBkRWbH+lrd18m62zBcEdFGqlZoTEZJbfQsfHLAHHqXtWyqftA5bPSp\n\tVGg2BSKNC4qkJhYFEUCwAJC3av4Q=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id\n\t:list-unsubscribe:list-archive:list-post:list-help:sender\n\t:mime-version:in-reply-to:references:from:date:message-id\n\t:subject:to:cc:content-type; s=default; bh=T4i3pup9Rwi/T4r1lR95b\n\tinF7HQ=; b=PD4gP7ny7pQ+RxFj5pmbDX8YE31Zd9GIWNoFLxK8H5ol7cPwiFnSn\n\tOw91Gp1/oThs97uRFasY7mMT9s9y8IsIDA4Y1haU6RMmDYsPXp/S7pga2RpQXy8F\n\tG+9XJXw9c3YpDFUe04RTTZb+o3YYmKz/MHFjYhy5/mXebk+Mbr0FqQ=","Mailing-List":"contact gcc-patches-help@gcc.gnu.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Archive":"","List-Post":"","List-Help":"","Sender":"gcc-patches-owner@gcc.gnu.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-3.4 required=5.0 tests=AWL, BAYES_00,\n\tKB_WAM_FROM_NAME_SINGLEWORD, RCVD_IN_DNSWL_NONE,\n\tSPF_PASS autolearn=no version=3.3.2 spammy=holiday, nominally,\n\tconvinced","X-HELO":"mail-yw0-f170.google.com","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net;\n\ts=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=nnq1tpy+y3pqABjBgq3BvPlMS2Fg03HBgyk43tRrGEc=;\n\tb=nuiBMT5jPQKastkH/aHTcK6m4HHlxIqIUIpuMnkUp4lWj6hsCfKNS0rp+Mp/C53jx7\n\tbCkqs0osk1gCFu+L00p+covadT/JFu8HctfCEiaxsTZ6+mge1gl5xaeMOvUodyP+BPvp\n\tBWP1lLP2JxCW3Sfp6hb5cp+oWSa2OqWmJResC1fSvnpv/pV3BwDu548gQ0YC/Q+D8V51\n\tQSu72flvfFwrOuW0IXHdTwQPaJW8oekpWT1JxRbINwPfEtqSf8Qkw8z6piBffpMNc9xe\n\tTaJrEnbkRCGN72NnJYZ1vBb4f7kEduUbOlo/xx6LFwCVZvwn2/4l6AKhT6w3KJJbA01+\n\tLWHw==","X-Gm-Message-State":"AJaThX4BMpwoZ+LpZbqDdEVHApi/rAjyXsYgqM9EVf875hGbNk4RPTxy\thEXPO8tO8zooICdcPd/k+Ohzv3NIkqW3wJ0BUbGebQ8v","X-Google-Smtp-Source":"AGs4zMZ9zeNGoJqFT3CdaVrJq8gudBa6nXN+L1EIo8ijHB1ZZpLt0xOAZ09DFJ9HkbCGFCYC2ybgKi/NiAulFaFqyp4=","X-Received":"by 10.129.182.13 with SMTP id u13mr9376057ywh.354.1511212204738;\n\tMon, 20 Nov 2017 13:10:04 -0800 (PST)","MIME-Version":"1.0","In-Reply-To":"<59BC0755.9050205@foss.arm.com>","References":"<1505205277-26276-1-git-send-email-charles.baylis@linaro.org>\n\t<1505205277-26276-2-git-send-email-charles.baylis@linaro.org>\n\t<59B8F42A.3050906@foss.arm.com>\n\t\n\t<59BC0755.9050205@foss.arm.com>","From":"Charles Baylis ","Date":"Mon, 20 Nov 2017 21:10:04 +0000","Message-ID":"","Subject":"Re: [PATCH 1/3] [ARM] Add bus_width_bits to tune_params","To":"Kyrill Tkachov ","Cc":"Richard Earnshaw ,\n\tRamana Radhakrishnan ,\n\t\"pinskia@gmail.com\" ,\n\t\"gcc-patches@gcc.gnu.org\" ","Content-Type":"text/plain; charset=\"UTF-8\"","X-IsSubscribed":"yes"}}]