[{"id":1770744,"web_url":"http://patchwork.ozlabs.org/comment/1770744/","msgid":"","list_archive_url":null,"date":"2017-09-19T08:20:39","subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Tue, Sep 12, 2017 at 2:32 AM, wrote:\n\n> From: Fenglin Wu \n>\n> GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is\n> configured. Update is_enabled flag in config_set() so that it can\n> reflect GPIO status correctly. Also modify EN_CTL register based on\n> is_enabled flag in config_set() to configure the GPIO properly.\n>\n> Signed-off-by: Fenglin Wu \n\nPending on Björn's review here.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"S/gwOnMP\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxG642mvmz9s7m\n\tfor ;\n\tTue, 19 Sep 2017 18:20:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751580AbdISIUn (ORCPT );\n\tTue, 19 Sep 2017 04:20:43 -0400","from mail-it0-f48.google.com ([209.85.214.48]:54906 \"EHLO\n\tmail-it0-f48.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751556AbdISIUl (ORCPT\n\t); Tue, 19 Sep 2017 04:20:41 -0400","by mail-it0-f48.google.com with SMTP id e134so1253311ite.3\n\tfor ;\n\tTue, 19 Sep 2017 01:20:40 -0700 (PDT)","by 10.79.164.78 with HTTP; Tue, 19 Sep 2017 01:20:39 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=CazOfGszWUUzCwtBGRmhLzHm73DxZ01SAtqq8ZFwsJ4=;\n\tb=S/gwOnMPmsZfaXm15qKL7fCkfeDM4L4heD4R6d421pcW9o4e47NtGgW3RHM2NjCuXL\n\tVAYZaimH+6E/gdin3jlIrd5imDdkKBccoVg8bv1UFB0l31nek1xExe9Ffiv+JzV/AhMq\n\tW9fIKPIsyiHxG/H86mHbUhLsnG3RnycOax4vQ=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=CazOfGszWUUzCwtBGRmhLzHm73DxZ01SAtqq8ZFwsJ4=;\n\tb=rau/ZOlUIPMNOnInh6Oonk/KiXs2ceogtxPRJDplIlJdi132SPPqseK4wpdMOH8uyp\n\tBNxjVzG32h3g+OxmRrFzo/4ccIjkvkBZJA+hce+IKwTfXx1awpHaMEQHvrBLAbVDTgXk\n\t9BfTFICT+WV+/heIOICWrowmWs/p/yH3duPObcR0pQOEGX+MNae/mIpmb2KCNdvxiM9I\n\t+5RaW3CMzvk07SOWgdo+ggx9M1sflkkryCawUv8CYnrLdIznzZAMN76ykfquRsPlooYX\n\t90DRSRQMmnCrBXlYoxzbBOb3rOL1jQdUwz3sm3apSXkZ+HVFSKYfnrA7gC3xS1VBRrqi\n\taVOA==","X-Gm-Message-State":"AHPjjUjn1A8YiPJBNFVDHpq6TPuIG+s/9L7g6Yz/yufhMPtO/f5ad7d7\n\t+A311Wu3G7g7uSBkHEayY3OPZTWRqSrxDed2qtO3Wg==","X-Google-Smtp-Source":"AOwi7QAenUtA3bI51JcdRU5ac+D8KTIpds9DWo5D1JntXv5SCHvY1YD+nIBt9/zwoysRIdAXiT3x8DczhYrseJLmfck=","X-Received":"by 10.36.123.200 with SMTP id q191mr372541itc.83.1505809240508; \n\tTue, 19 Sep 2017 01:20:40 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170912003331.3092-1-fenglinw@codeaurora.org>","References":"<20170912003331.3092-1-fenglinw@codeaurora.org>","From":"Linus Walleij ","Date":"Tue, 19 Sep 2017 10:20:39 +0200","Message-ID":"","Subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","To":"fenglinw@codeaurora.org, Bjorn Andersson ","Cc":"\"linux-arm-msm@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tDavid Collins ,\n\taghayal@codeaurora.org, wruan@codeaurora.org,\n\tsubbaram@codeaurora.org, kgunda@codeaurora.org,\n\tIvan Ivanov ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1780790,"web_url":"http://patchwork.ozlabs.org/comment/1780790/","msgid":"<20171005162750.GY1165@minitux>","list_archive_url":null,"date":"2017-10-05T16:27:50","subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Mon 11 Sep 17:32 PDT 2017, fenglinw@codeaurora.org wrote:\n\n> From: Fenglin Wu \n> \n> GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is\n> configured. Update is_enabled flag in config_set() so that it can\n> reflect GPIO status correctly. Also modify EN_CTL register based on\n> is_enabled flag in config_set() to configure the GPIO properly.\n> \n> Signed-off-by: Fenglin Wu \n> ---\n> drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 5 +++++\n> 1 file changed, 5 insertions(+)\n> \n> diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n> index c2c0bab..a0edaa8 100644\n> --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n> +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n> @@ -453,6 +453,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n> \n> \tpad = pctldev->desc->pins[pin].drv_data;\n> \n> +\tpad->is_enabled = true;\n> \tfor (i = 0; i < nconfs; i++) {\n> \t\tparam = pinconf_to_config_param(configs[i]);\n> \t\targ = pinconf_to_config_argument(configs[i]);\n> @@ -600,6 +601,10 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n> \t\t\treturn ret;\n> \t}\n> \n> +\tval = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;\n> +\n> +\tret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);\n> +\n\nThis looks good.\n\nAcked-by: Bjorn Andersson \n\n\nBut I spotted another issue while reviewing this; currently the initial\nstate of is_enabled is unconditionally set to enabled in\npmic_gpio_populate(), so reading the initial pinconf or configuring a\npinmux before setting a pinconf will operate on the potentially wrong\ninformation.\n\nSo I think the initial value should be read out from REG_EN_CTL rather\nthan being just \"true\".\n\nCan you please either submit another patch for this?\n\nRegards,\nBjorn\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"VQZT4jJH\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y7J8w1JbRz9sRm\n\tfor ;\n\tFri, 6 Oct 2017 03:28:00 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751408AbdJEQ16 (ORCPT );\n\tThu, 5 Oct 2017 12:27:58 -0400","from mail-pf0-f174.google.com ([209.85.192.174]:47659 \"EHLO\n\tmail-pf0-f174.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751323AbdJEQ1z (ORCPT\n\t); Thu, 5 Oct 2017 12:27:55 -0400","by mail-pf0-f174.google.com with SMTP id u12so8184362pfl.4\n\tfor ;\n\tThu, 05 Oct 2017 09:27:55 -0700 (PDT)","from minitux (ip68-111-217-79.sd.sd.cox.net. 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Update is_enabled flag in config_set() so that it can\n>> reflect GPIO status correctly. Also modify EN_CTL register based on\n>> is_enabled flag in config_set() to configure the GPIO properly.\n>>\n>> Signed-off-by: Fenglin Wu \n>> ---\n>> drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 5 +++++\n>> 1 file changed, 5 insertions(+)\n>>\n>> diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n>> index c2c0bab..a0edaa8 100644\n>> --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n>> +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n>> @@ -453,6 +453,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n>> \n>> \tpad = pctldev->desc->pins[pin].drv_data;\n>> \n>> +\tpad->is_enabled = true;\n>> \tfor (i = 0; i < nconfs; i++) {\n>> \t\tparam = pinconf_to_config_param(configs[i]);\n>> \t\targ = pinconf_to_config_argument(configs[i]);\n>> @@ -600,6 +601,10 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n>> \t\t\treturn ret;\n>> \t}\n>> \n>> +\tval = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;\n>> +\n>> +\tret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);\n>> +\n> \n> This looks good.\n> \n> Acked-by: Bjorn Andersson \n> \n> \n> But I spotted another issue while reviewing this; currently the initial\n> state of is_enabled is unconditionally set to enabled in\n> pmic_gpio_populate(), so reading the initial pinconf or configuring a\n> pinmux before setting a pinconf will operate on the potentially wrong\n> information.\n> \n> So I think the initial value should be read out from REG_EN_CTL rather\n> than being just \"true\".\n> \n> Can you please either submit another patch for this?\n\nHmm, considering a GPIO which is disabled by default in hardware\nsetting, what's its expected state if we only define \"function\" for it?\nI was thinking we need to enable it once it has any setting in pinmux or\npinconf. If you think that we need to keep its original state until we\nset pinconf for it, yes, I can submit a change to address this.\n\n\n> \n> Regards,\n> Bjorn\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"I6cwKkUM\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"h6OAE+Nq\"; dkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=fenglinw@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9TSm2b9Xz9tXx\n\tfor ;\n\tMon, 9 Oct 2017 16:34:15 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751647AbdJIFeN (ORCPT );\n\tMon, 9 Oct 2017 01:34:13 -0400","from smtp.codeaurora.org ([198.145.29.96]:50110 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751636AbdJIFeM (ORCPT\n\t); Mon, 9 Oct 2017 01:34:12 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid 04E6B607EF; Mon, 9 Oct 2017 05:34:12 +0000 (UTC)","from [10.231.204.207] (unknown [180.166.53.21])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\t(Authenticated sender: fenglinw@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id F0A76601CF;\n\tMon, 9 Oct 2017 05:34:08 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507527252;\n\tbh=QjD/eDZWK3emxFRsqW9/c6Gjw2muTFgib+z5A73pKCA=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=I6cwKkUMj33IJqtNO4o94hC4iIKXb+B679Ap8ZINY3AoX2K6lJy0qfM7UiZeY+ewz\n\tvQ/lAUJf0b/N5915XtilHOhUkyxeje/AZ3oJp6moAl3iOKduA9H7fgZ/7y7mcfoOEm\n\tsTmjdIjphWWT+m3ZtC7wp5R+tZKTExf7rBWr4bNo=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507527251;\n\tbh=QjD/eDZWK3emxFRsqW9/c6Gjw2muTFgib+z5A73pKCA=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=h6OAE+NqUiQyFY38G8VN87DPka0xPQx/fEOpA1qjXyfYu9sxw3yqGWmgYd8P4cRzG\n\tlpSVA5erO+AAoHZlmCr9BJMLqdcxLy3RaFHrjLu9agzxDpnDtIV3v0dF6Xmi6Qjx/W\n\tcT2u+LrSOA9q5O+WsYRdPOA0YyuBdvwM+9xPhkG0="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org F0A76601CF","Subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","To":"Bjorn Andersson ","Cc":"linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tLinus Walleij ,\n\tlinux-gpio@vger.kernel.org, collinsd@codeaurora.org,\n\taghayal@codeaurora.org, wruan@codeaurora.org,\n\tsubbaram@codeaurora.org, kgunda@codeaurora.org","References":"<20170912003331.3092-1-fenglinw@codeaurora.org>\n\t<20171005162750.GY1165@minitux>","From":"Fenglin Wu ","Message-ID":"","Date":"Mon, 9 Oct 2017 13:34:05 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171005162750.GY1165@minitux>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1782511,"web_url":"http://patchwork.ozlabs.org/comment/1782511/","msgid":"<20171009055643.GB1165@minitux>","list_archive_url":null,"date":"2017-10-09T05:56:43","subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Sun 08 Oct 22:34 PDT 2017, Fenglin Wu wrote:\n\n> On 10/6/2017 12:27 AM, Bjorn Andersson wrote:\n> > On Mon 11 Sep 17:32 PDT 2017, fenglinw@codeaurora.org wrote:\n> > \n> > > From: Fenglin Wu \n> > > \n> > > GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is\n> > > configured. Update is_enabled flag in config_set() so that it can\n> > > reflect GPIO status correctly. Also modify EN_CTL register based on\n> > > is_enabled flag in config_set() to configure the GPIO properly.\n> > > \n> > > Signed-off-by: Fenglin Wu \n> > > ---\n> > > drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 5 +++++\n> > > 1 file changed, 5 insertions(+)\n> > > \n> > > diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n> > > index c2c0bab..a0edaa8 100644\n> > > --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n> > > +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n> > > @@ -453,6 +453,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n> > > \tpad = pctldev->desc->pins[pin].drv_data;\n> > > +\tpad->is_enabled = true;\n> > > \tfor (i = 0; i < nconfs; i++) {\n> > > \t\tparam = pinconf_to_config_param(configs[i]);\n> > > \t\targ = pinconf_to_config_argument(configs[i]);\n> > > @@ -600,6 +601,10 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n> > > \t\t\treturn ret;\n> > > \t}\n> > > +\tval = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;\n> > > +\n> > > +\tret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);\n> > > +\n> > \n> > This looks good.\n> > \n> > Acked-by: Bjorn Andersson \n> > \n> > \n> > But I spotted another issue while reviewing this; currently the initial\n> > state of is_enabled is unconditionally set to enabled in\n> > pmic_gpio_populate(), so reading the initial pinconf or configuring a\n> > pinmux before setting a pinconf will operate on the potentially wrong\n> > information.\n> > \n> > So I think the initial value should be read out from REG_EN_CTL rather\n> > than being just \"true\".\n> > \n> > Can you please either submit another patch for this?\n> \n> Hmm, considering a GPIO which is disabled by default in hardware\n> setting, what's its expected state if we only define \"function\" for it?\n> I was thinking we need to enable it once it has any setting in pinmux or\n> pinconf. If you think that we need to keep its original state until we\n> set pinconf for it, yes, I can submit a change to address this.\n> \n\nAre there valid cases where only function should be selected and no\nother configuration is used? If so it makes sense to make\npmic_gpio_set_mux() enable the block.\n\n\nRegardless of this, if there are disabled pins that are not mentioned in\nDT they will still appear as enabled in the debugfs interface; and this\nI consider an error worth fixing.\n\nRegards,\nBjorn\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"I+Qvu9W9\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9TzM3LSmz9tXv\n\tfor ;\n\tMon, 9 Oct 2017 16:57:19 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753856AbdJIF4t (ORCPT );\n\tMon, 9 Oct 2017 01:56:49 -0400","from mail-pf0-f171.google.com ([209.85.192.171]:46542 \"EHLO\n\tmail-pf0-f171.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751706AbdJIF4r (ORCPT\n\t); Mon, 9 Oct 2017 01:56:47 -0400","by mail-pf0-f171.google.com with SMTP id p87so3705478pfj.3\n\tfor ;\n\tSun, 08 Oct 2017 22:56:47 -0700 (PDT)","from minitux (ip68-111-217-79.sd.sd.cox.net. [68.111.217.79])\n\tby smtp.gmail.com with ESMTPSA id\n\tl6sm13736514pfc.112.2017.10.08.22.56.44\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tSun, 08 Oct 2017 22:56:45 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=4v18/I3nGNoV34k4JJUsR9T1dvr3LjQavof6Z4Ez66g=;\n\tb=I+Qvu9W9Ajr4W+GuUsdurkOn/ssbY4vbsQZhkkSC+tLSgHalRTyRwU7yQbEWPZXvik\n\t6/asHHGLs+ocjDw+WycTYm7EIPU71G7HtvDTh72yGFMjZC3K/fV6SIQY+VXtYrkDCzhc\n\t8wIOx940ivKg8zMPB6W7Qr3Aezr9NQw+WGlp0=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=4v18/I3nGNoV34k4JJUsR9T1dvr3LjQavof6Z4Ez66g=;\n\tb=N4u/0X60D7kadf+IMhR13DHuyhLWW548/hypm+MKd/444jQprm0vs4YF/2WfDukiUq\n\tuJg6p7CiczbzNLJcWIfC9AwbfyIu8DcQcq+2h5MlSAWbebjfIQThH9iyD+FOV78OEj0z\n\t3W19nGgEdLRAmrI3AcVv43VqOG/sQHXWi4HSCPvB4VMD94Gyl/B0p/BCoIpwD2YZ6Yc3\n\t/PoajMH0flX4rlFVWS8ry0zwwxldQDqrb2PqEGuOVc04DZ3sLLEx/5GYJukL5DvrmqD/\n\tDhTaX9bQvAy1ILBByLhPsuqKDE8LsctJhgtlSmJkpC3RZy3aCbXBnhHCKDtHea/arALJ\n\tJXrg==","X-Gm-Message-State":"AMCzsaXoJdYEM7jvi1MF9GQhrU6i3DlP6iCGPBEaaqsnwtndwXdpQSwB\n\tIFIRGl7irSyibL7L+B5ELM2ECw==","X-Google-Smtp-Source":"AOwi7QCB9HW25WRnpfnO7X7+47JtwbJiP+PR2lnjBatiYL/D3k3N4Ghp6xzTMjBjWZtPSlr5BlZ2DA==","X-Received":"by 10.101.86.5 with SMTP id l5mr8080181pgs.16.1507528606494;\n\tSun, 08 Oct 2017 22:56:46 -0700 (PDT)","Date":"Sun, 8 Oct 2017 22:56:43 -0700","From":"Bjorn Andersson ","To":"Fenglin Wu ","Cc":"linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tLinus Walleij ,\n\tlinux-gpio@vger.kernel.org, collinsd@codeaurora.org,\n\taghayal@codeaurora.org, wruan@codeaurora.org,\n\tsubbaram@codeaurora.org, kgunda@codeaurora.org","Subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","Message-ID":"<20171009055643.GB1165@minitux>","References":"<20170912003331.3092-1-fenglinw@codeaurora.org>\n\t<20171005162750.GY1165@minitux>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1783328,"web_url":"http://patchwork.ozlabs.org/comment/1783328/","msgid":"<35aec5d7-8808-9930-8d6d-e0399df12a9e@codeaurora.org>","list_archive_url":null,"date":"2017-10-10T00:17:52","subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","submitter":{"id":71715,"url":"http://patchwork.ozlabs.org/api/people/71715/","name":"Fenglin Wu","email":"fenglinw@codeaurora.org"},"content":"On 10/9/2017 1:56 PM, Bjorn Andersson wrote:\n> On Sun 08 Oct 22:34 PDT 2017, Fenglin Wu wrote:\n> \n>> On 10/6/2017 12:27 AM, Bjorn Andersson wrote:\n>>> On Mon 11 Sep 17:32 PDT 2017, fenglinw@codeaurora.org wrote:\n>>>\n>>>> From: Fenglin Wu \n>>>>\n>>>> GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is\n>>>> configured. Update is_enabled flag in config_set() so that it can\n>>>> reflect GPIO status correctly. Also modify EN_CTL register based on\n>>>> is_enabled flag in config_set() to configure the GPIO properly.\n>>>>\n>>>> Signed-off-by: Fenglin Wu \n>>>> ---\n>>>> drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 5 +++++\n>>>> 1 file changed, 5 insertions(+)\n>>>>\n>>>> diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n>>>> index c2c0bab..a0edaa8 100644\n>>>> --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n>>>> +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c\n>>>> @@ -453,6 +453,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n>>>> \tpad = pctldev->desc->pins[pin].drv_data;\n>>>> +\tpad->is_enabled = true;\n>>>> \tfor (i = 0; i < nconfs; i++) {\n>>>> \t\tparam = pinconf_to_config_param(configs[i]);\n>>>> \t\targ = pinconf_to_config_argument(configs[i]);\n>>>> @@ -600,6 +601,10 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,\n>>>> \t\t\treturn ret;\n>>>> \t}\n>>>> +\tval = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;\n>>>> +\n>>>> +\tret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);\n>>>> +\n>>>\n>>> This looks good.\n>>>\n>>> Acked-by: Bjorn Andersson \n>>>\n>>>\n>>> But I spotted another issue while reviewing this; currently the initial\n>>> state of is_enabled is unconditionally set to enabled in\n>>> pmic_gpio_populate(), so reading the initial pinconf or configuring a\n>>> pinmux before setting a pinconf will operate on the potentially wrong\n>>> information.\n>>>\n>>> So I think the initial value should be read out from REG_EN_CTL rather\n>>> than being just \"true\".\n>>>\n>>> Can you please either submit another patch for this?\n>>\n>> Hmm, considering a GPIO which is disabled by default in hardware\n>> setting, what's its expected state if we only define \"function\" for it?\n>> I was thinking we need to enable it once it has any setting in pinmux or\n>> pinconf. If you think that we need to keep its original state until we\n>> set pinconf for it, yes, I can submit a change to address this.\n>>\n> \n> Are there valid cases where only function should be selected and no\n> other configuration is used? If so it makes sense to make\n> pmic_gpio_set_mux() enable the block.\n> \n> \n> Regardless of this, if there are disabled pins that are not mentioned in\n> DT they will still appear as enabled in the debugfs interface; and this\n> I consider an error worth fixing.\nHow about we do both: read the HW initial state in pmic_gpio_populate(),\nand also enable the GPIO block in pmic_gpio_set_mux()?\n\n> \n> Regards,\n> Bjorn\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"bd3+LEts\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"BvlLk3Jw\"; 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a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507594678;\n\tbh=RgU2DaW+MprVzzyLGxUXUy1Oxn7hAKzTuOqvSekUbiA=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=bd3+LEtsAckzHP5NQjAuRc7JVPk9alOj4dsjb34RENhXk9UAfb3hXkhDHgqMISLCe\n\tZy4Ypw+iB7kBhi/VWVmKi+YiF5mYopqCb0IBqSaHZ1+tF0VJkYA7QFqVqBX5mEOXxW\n\t0BN+PBnkKq/m1qR2FxR5EX/h7G6oey3NxXXEi0CI=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1507594677;\n\tbh=RgU2DaW+MprVzzyLGxUXUy1Oxn7hAKzTuOqvSekUbiA=;\n\th=Subject:To:Cc:References:From:Date:In-Reply-To:From;\n\tb=BvlLk3Jwrz2uTLqxPvqJF6vh7N3qZYGDwIa4O1HD7pk+Z8SLa/lAiY6dOE50QmZ1o\n\tZxPZYliWWfv9HVat/ORo00k8jckh9luQ7qUV3PQmvH+VsNWiwX7JtsXP9+jCAMTsNq\n\tFrjDTSW9B72HkyExH3j042eLDm7Y2T5lTYg03QMc="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2C74D60392","Subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","To":"Bjorn Andersson ","Cc":"linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tLinus Walleij ,\n\tlinux-gpio@vger.kernel.org, collinsd@codeaurora.org,\n\taghayal@codeaurora.org, wruan@codeaurora.org,\n\tsubbaram@codeaurora.org, kgunda@codeaurora.org","References":"<20170912003331.3092-1-fenglinw@codeaurora.org>\n\t<20171005162750.GY1165@minitux>\n\t\n\t<20171009055643.GB1165@minitux>","From":"Fenglin Wu ","Message-ID":"<35aec5d7-8808-9930-8d6d-e0399df12a9e@codeaurora.org>","Date":"Tue, 10 Oct 2017 08:17:52 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20171009055643.GB1165@minitux>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1784302,"web_url":"http://patchwork.ozlabs.org/comment/1784302/","msgid":"<20171011054852.GH1165@minitux>","list_archive_url":null,"date":"2017-10-11T05:48:52","subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Mon 09 Oct 17:17 PDT 2017, Fenglin Wu wrote:\n\n> On 10/9/2017 1:56 PM, Bjorn Andersson wrote:\n> > On Sun 08 Oct 22:34 PDT 2017, Fenglin Wu wrote:\n> > \n> > > On 10/6/2017 12:27 AM, Bjorn Andersson wrote:\n[..]\n> > > > But I spotted another issue while reviewing this; currently the initial\n> > > > state of is_enabled is unconditionally set to enabled in\n> > > > pmic_gpio_populate(), so reading the initial pinconf or configuring a\n> > > > pinmux before setting a pinconf will operate on the potentially wrong\n> > > > information.\n> > > > \n> > > > So I think the initial value should be read out from REG_EN_CTL rather\n> > > > than being just \"true\".\n> > > > \n> > > > Can you please either submit another patch for this?\n> > > \n> > > Hmm, considering a GPIO which is disabled by default in hardware\n> > > setting, what's its expected state if we only define \"function\" for it?\n> > > I was thinking we need to enable it once it has any setting in pinmux or\n> > > pinconf. If you think that we need to keep its original state until we\n> > > set pinconf for it, yes, I can submit a change to address this.\n> > > \n> > \n> > Are there valid cases where only function should be selected and no\n> > other configuration is used? If so it makes sense to make\n> > pmic_gpio_set_mux() enable the block.\n> > \n> > \n> > Regardless of this, if there are disabled pins that are not mentioned in\n> > DT they will still appear as enabled in the debugfs interface; and this\n> > I consider an error worth fixing.\n> How about we do both: read the HW initial state in pmic_gpio_populate(),\n> and also enable the GPIO block in pmic_gpio_set_mux()?\n> \n\nThat sounds good.\n\nPlease do this as two separate patches, with the commit message clearly\ndescribing a case where the pinconf does not affect the function of the\npin, so a pinmux is the only thing needed.\n\nRegards,\nBjorn\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"SUw4pAfi\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yBjhq2RwWz9t3B\n\tfor ;\n\tWed, 11 Oct 2017 16:48:59 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754285AbdJKFs5 (ORCPT );\n\tWed, 11 Oct 2017 01:48:57 -0400","from mail-pf0-f170.google.com ([209.85.192.170]:52656 \"EHLO\n\tmail-pf0-f170.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752099AbdJKFs4 (ORCPT\n\t); Wed, 11 Oct 2017 01:48:56 -0400","by mail-pf0-f170.google.com with SMTP id e64so584280pfk.9\n\tfor ;\n\tTue, 10 Oct 2017 22:48:56 -0700 (PDT)","from minitux (ip68-111-217-79.sd.sd.cox.net. [68.111.217.79])\n\tby smtp.gmail.com with ESMTPSA id\n\ty30sm20715272pge.27.2017.10.10.22.48.54\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 10 Oct 2017 22:48:54 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=0ZEvzqMu9u0Cy9LhsHq4pL7nmNBndfZ/+49k+Fqvpjs=;\n\tb=SUw4pAfiYbskTxH+MG1BAOOvOB5JM2RVdTg+8vWXSyc776LGo1AoIjm5daUa0PqlU3\n\tedFsgjNbs7Kpvy+9akKcn1zQYg2Gw/THunzJJJAn8EbHmEIfM0KlbaYkJJ3DSY3OILHw\n\tNAa1Ya/dMuo8e7EimJkcZwhvnTpBoC3waDplE=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=0ZEvzqMu9u0Cy9LhsHq4pL7nmNBndfZ/+49k+Fqvpjs=;\n\tb=NvZGXxolvCUJsaRNLSdkPjiN94QKIHdwbZ2h/5oePDbQLGL348UCy9ywBabYMSbh8A\n\t1oJO/7UtKZJXZGEEkgdggUE6NlKYmQOGa6g/yg51mbBjXnA+QlQXB88dMH114q99xja2\n\tDuyDuWdcDPVB8HlhAko6rruS8aa5slKMZSywovcCHNIgnql1s907cdIqYApbTD+Ei8Nr\n\txk76CvLoeptHQZ71Y5oC9gqPIsfOYons1ZjcZIygJMSFuOYE3C2AHqTRwrMxtVnaJ3p+\n\tf/v304uyuc1w7rapikYotA822ioIV5Pv7BdaCk3Q9GvLLX+RPEjhdo0cEfwI6bRKrHPP\n\tTNbg==","X-Gm-Message-State":"AMCzsaXawYmIE7BXYi5tTxYxczuk0Rey4nQXItofHNAOgQtnnsMe7shR\n\tn+vZ8cCCvlBG9/B9Pmh5vld/Tg==","X-Google-Smtp-Source":"AOwi7QAdb53ybKbz9Pv33m0aDiVH/9C88lSTRyrOKGBsbJJvez53XnCD0m6f7ilIt6FcxfGS/3AFNA==","X-Received":"by 10.84.240.204 with SMTP id l12mr14225101plt.360.1507700935590;\n\tTue, 10 Oct 2017 22:48:55 -0700 (PDT)","Date":"Tue, 10 Oct 2017 22:48:52 -0700","From":"Bjorn Andersson ","To":"Fenglin Wu ","Cc":"linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tLinus Walleij ,\n\tlinux-gpio@vger.kernel.org, collinsd@codeaurora.org,\n\taghayal@codeaurora.org, wruan@codeaurora.org,\n\tsubbaram@codeaurora.org, kgunda@codeaurora.org","Subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","Message-ID":"<20171011054852.GH1165@minitux>","References":"<20170912003331.3092-1-fenglinw@codeaurora.org>\n\t<20171005162750.GY1165@minitux>\n\t\n\t<20171009055643.GB1165@minitux>\n\t<35aec5d7-8808-9930-8d6d-e0399df12a9e@codeaurora.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<35aec5d7-8808-9930-8d6d-e0399df12a9e@codeaurora.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":1784390,"web_url":"http://patchwork.ozlabs.org/comment/1784390/","msgid":"","list_archive_url":null,"date":"2017-10-11T08:24:50","subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Tue, Sep 12, 2017 at 2:32 AM, wrote:\n\n> From: Fenglin Wu \n>\n> GPIO is expected to be disabled iff PIN_CONFIG_BIAS_HIGH_IMPEDANCE is\n> configured. Update is_enabled flag in config_set() so that it can\n> reflect GPIO status correctly. Also modify EN_CTL register based on\n> is_enabled flag in config_set() to configure the GPIO properly.\n>\n> Signed-off-by: Fenglin Wu \n\nPatch applied with Björn's ACK.\n\nExpecting follow-up fixes as discussed in this thread.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-gpio\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"AyTSirvn\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yBn8k6W0Dz9t3Z\n\tfor ;\n\tWed, 11 Oct 2017 19:24:54 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1757235AbdJKIYx (ORCPT );\n\tWed, 11 Oct 2017 04:24:53 -0400","from mail-it0-f44.google.com ([209.85.214.44]:52977 \"EHLO\n\tmail-it0-f44.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1756661AbdJKIYv (ORCPT\n\t); Wed, 11 Oct 2017 04:24:51 -0400","by mail-it0-f44.google.com with SMTP id j140so1890313itj.1\n\tfor ;\n\tWed, 11 Oct 2017 01:24:51 -0700 (PDT)","by 10.79.14.140 with HTTP; Wed, 11 Oct 2017 01:24:50 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=25f/UiKKh31wmcwHDFMID8HglIlsXr/9Dw8ZqIcetf8=;\n\tb=AyTSirvn7NgHBo8UJFRJlBn4jBVFj1u98GyEJu9JVa6dVwX/ZojQUT1HKRsPEUrEWQ\n\tYhJCCfbd0z6WD+L/4e3HWnF8MOX86DOXM+tLqiq4lyKThfSIyOp7kLugKFGYoVNh5HR0\n\tPfF9aa7FYHMaP+Tvsv2f8oP9EL6rc9LWUaXDs=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=25f/UiKKh31wmcwHDFMID8HglIlsXr/9Dw8ZqIcetf8=;\n\tb=sRe637arbmIdF44DaartCqVuDohIuqL8a3jkAe2oemmIWVu8qh2cm74Mfru07tG8RS\n\tYUWv1+zKNFLOsdrx2wuHYhxaFEKeFunBqciuQjJS4GtVVgYWYWrsVD7qApcIc57754x6\n\tR2TJvyU0jLkWsBxZ3L8vQNeQMKLtu5hfSZQtaLQaHeOKqraApcFbGlLtRs6eWxN4G/EE\n\tGSligXlbjweY6GC25OTZd6mUDNzFG+emnrTnEo9WMaBoe+WoO9p0Gmvs3JjyLvZroh7e\n\tcb4/TsTy0CtajijIzPdzZY/gcQPnqLXsr/ZoqLbFmedYf6dNFE+aluBNeFODPIs3r2VE\n\tJY+g==","X-Gm-Message-State":"AMCzsaUozpiA3F3U6MpGn5Mhs3nSWM0oL5axvBghj4a7wnpdnjm+dNud\n\tY7PNu3ubm95eCpvn77fmUDSsTpZx8ILXHZ47bbJBMA==","X-Google-Smtp-Source":"AOwi7QA5o4bjf3qH2PWT0/gGlJQn0q8iy/HbU4YyDCLPckjqxRIQHNNVjZxcl7wQz1+mrAaVDX4MdcynswIRFdZ3pUw=","X-Received":"by 10.36.92.193 with SMTP id q184mr4076217itb.83.1507710291020; \n\tWed, 11 Oct 2017 01:24:51 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170912003331.3092-1-fenglinw@codeaurora.org>","References":"<20170912003331.3092-1-fenglinw@codeaurora.org>","From":"Linus Walleij ","Date":"Wed, 11 Oct 2017 10:24:50 +0200","Message-ID":"","Subject":"Re: [PATCH V1] pinctrl: qcom: spmi-gpio: Update GPIO EN_CTL when\n\tsetting pin config","To":"fenglinw@codeaurora.org","Cc":"\"linux-arm-msm@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tBjorn Andersson ,\n\t\"linux-gpio@vger.kernel.org\" ,\n\tDavid Collins ,\n\taghayal@codeaurora.org, wruan@codeaurora.org,\n\tsubbaram@codeaurora.org, kgunda@codeaurora.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}}]