[{"id":1770838,"web_url":"http://patchwork.ozlabs.org/comment/1770838/","msgid":"<20170919074556.GO27153@umbus>","list_archive_url":null,"date":"2017-09-19T07:45:57","subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Mon, Sep 11, 2017 at 07:12:25PM +0200, Cédric Le Goater wrote:\n> If a triggered event is let through, the Event Queue data defined in\n> the associated IVE is pushed in the in-memory event queue. The latter\n> is a circular buffer provided by the OS using the H_INT_SET_QUEUE_CONFIG\n> hcall, one per target and priority couple. It is composed of Event\n> Queue entries which are 4 bytes long, the first bit being a\n> 'generation' bit and the 31 following bits the EQ Data field.\n> \n> The EQ Data field provides a way to set an invariant logical event\n> source number for an IRQ. It is set with the H_INT_SET_SOURCE_CONFIG\n> hcall.\n> \n> Notification of the CPU will be done in the following patch.\n> \n> Signed-off-by: Cédric Le Goater <clg@kaod.org>\n> ---\n>  hw/intc/spapr_xive.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n>  1 file changed, 67 insertions(+)\n> \n> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n> index 557a7e2535b5..4bc61cfda67a 100644\n> --- a/hw/intc/spapr_xive.c\n> +++ b/hw/intc/spapr_xive.c\n> @@ -175,9 +175,76 @@ static const MemoryRegionOps spapr_xive_tm_ops = {\n>      },\n>  };\n>  \n> +static void spapr_xive_eq_push(XiveEQ *eq, uint32_t data)\n> +{\n> +    uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;\n> +    uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);\n> +    uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);\n> +    uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);\n> +\n> +    uint64_t qaddr = qaddr_base + (qindex << 2);\n> +    uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));\n> +    uint32_t qentries = 1 << (qsize + 10);\n> +\n> +    if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) {\n> +        qemu_log_mask(LOG_GUEST_ERROR, \"%s: failed to write EQ data @0x%\"\n> +                      HWADDR_PRIx \"\\n\", __func__, qaddr);\n> +        return;\n> +    }\n> +\n> +    qindex = (qindex + 1) % qentries;\n> +    if (qindex == 0) {\n> +        qgen ^= 1;\n> +        eq->w1 = SETFIELD(EQ_W1_GENERATION, eq->w1, qgen);\n> +    }\n> +    eq->w1 = SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex);\n> +}\n> +\n>  static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n>  {\n> +    XiveIVE *ive;\n> +    XiveEQ *eq;\n> +    uint32_t eq_idx;\n> +    uint32_t priority;\n> +\n> +    ive = spapr_xive_get_ive(xive, srcno);\n> +    if (!ive || !(ive->w & IVE_VALID)) {\n> +        qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid LISN %d\\n\", srcno);\n> +        return;\n> +    }\n> +\n> +    if (ive->w & IVE_MASKED) {\n> +        return;\n> +    }\n> +\n> +    /* Find our XiveEQ */\n> +    eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);\n> +    eq = spapr_xive_get_eq(xive, eq_idx);\n> +    if (!eq) {\n> +        qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No EQ for LISN %d\\n\", srcno);\n> +        return;\n> +    }\n> +\n> +    if (eq->w0 & EQ_W0_ENQUEUE) {\n> +        spapr_xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w));\n> +    } else {\n> +        qemu_log_mask(LOG_UNIMP, \"XIVE: !ENQUEUE not implemented\\n\");\n> +    }\n> +\n> +    if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) {\n> +        qemu_log_mask(LOG_UNIMP, \"XIVE: !UCOND_NOTIFY not implemented\\n\");\n> +    }\n> +\n> +    if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n> +        priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n>  \n> +        /* The EQ is masked. Can this happen ?  */\n> +        if (priority == 0xff) {\n> +            return;\n\nHow does the 8-bit priority field here interact with the 3-bit\npriority which selects which EQ to use?\n\n> +        }\n> +    } else {\n> +        qemu_log_mask(LOG_UNIMP, \"XIVE: w7 format1 not implemented\\n\");\n> +    }\n>  }\n>  \n>  /*","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"U0FUMuab\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxKCL41Tjz9s82\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 20:40:30 +1000 (AEST)","from localhost ([::1]:41370 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1duFx6-0003nt-KR\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 06:40:28 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:51183)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1duFtW-0001G0-Dy\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 06:36:50 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1duFtT-0002tF-Un\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 06:36:46 -0400","from ozlabs.org ([103.22.144.67]:42307)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <dgibson@ozlabs.org>)\n\tid 1duFtS-0002nW-E7; Tue, 19 Sep 2017 06:36:43 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xxK6p6j7xz9t4R; Tue, 19 Sep 2017 20:36:34 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1505817394;\n\tbh=qEJAtoTk8Qi0nu83OAoSQxEG4sIoCCwu0ShSkrJ33TI=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=U0FUMuabAs7bFy8iCuwEBJq/4l56EMiFlY9weJM498Dm5GXahaPKFxeXFDYL94qY5\n\thihcTA0onKKTrlfyiD/g6oISkP5NmWRi7fUv9Bg09UXMo1jY70lJUV8eIGic9uSsvo\n\tGvzQV8mMplbe+RRkpvULVcQruNhwSc8HQsf/m07g=","Date":"Tue, 19 Sep 2017 17:45:57 +1000","From":"David Gibson <david@gibson.dropbear.id.au>","To":"=?iso-8859-1?q?C=E9dric?= Le Goater <clg@kaod.org>","Message-ID":"<20170919074556.GO27153@umbus>","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-12-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"i7KxW38SoMauyveo\"","Content-Disposition":"inline","In-Reply-To":"<20170911171235.29331-12-clg@kaod.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"103.22.144.67","Subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"Alexey Kardashevskiy <aik@ozlabs.ru>, qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"}},{"id":1771320,"web_url":"http://patchwork.ozlabs.org/comment/1771320/","msgid":"<2d91c586-ff31-ceb8-bee6-6d4531d1b5c0@kaod.org>","list_archive_url":null,"date":"2017-09-19T19:36:08","subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/","name":"Cédric Le Goater","email":"clg@kaod.org"},"content":"On 09/19/2017 09:45 AM, David Gibson wrote:\n> On Mon, Sep 11, 2017 at 07:12:25PM +0200, Cédric Le Goater wrote:\n>> If a triggered event is let through, the Event Queue data defined in\n>> the associated IVE is pushed in the in-memory event queue. The latter\n>> is a circular buffer provided by the OS using the H_INT_SET_QUEUE_CONFIG\n>> hcall, one per target and priority couple. It is composed of Event\n>> Queue entries which are 4 bytes long, the first bit being a\n>> 'generation' bit and the 31 following bits the EQ Data field.\n>>\n>> The EQ Data field provides a way to set an invariant logical event\n>> source number for an IRQ. It is set with the H_INT_SET_SOURCE_CONFIG\n>> hcall.\n>>\n>> Notification of the CPU will be done in the following patch.\n>>\n>> Signed-off-by: Cédric Le Goater <clg@kaod.org>\n>> ---\n>>  hw/intc/spapr_xive.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n>>  1 file changed, 67 insertions(+)\n>>\n>> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n>> index 557a7e2535b5..4bc61cfda67a 100644\n>> --- a/hw/intc/spapr_xive.c\n>> +++ b/hw/intc/spapr_xive.c\n>> @@ -175,9 +175,76 @@ static const MemoryRegionOps spapr_xive_tm_ops = {\n>>      },\n>>  };\n>>  \n>> +static void spapr_xive_eq_push(XiveEQ *eq, uint32_t data)\n>> +{\n>> +    uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;\n>> +    uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);\n>> +    uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);\n>> +    uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);\n>> +\n>> +    uint64_t qaddr = qaddr_base + (qindex << 2);\n>> +    uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));\n>> +    uint32_t qentries = 1 << (qsize + 10);\n>> +\n>> +    if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) {\n>> +        qemu_log_mask(LOG_GUEST_ERROR, \"%s: failed to write EQ data @0x%\"\n>> +                      HWADDR_PRIx \"\\n\", __func__, qaddr);\n>> +        return;\n>> +    }\n>> +\n>> +    qindex = (qindex + 1) % qentries;\n>> +    if (qindex == 0) {\n>> +        qgen ^= 1;\n>> +        eq->w1 = SETFIELD(EQ_W1_GENERATION, eq->w1, qgen);\n>> +    }\n>> +    eq->w1 = SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex);\n>> +}\n>> +\n>>  static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n>>  {\n>> +    XiveIVE *ive;\n>> +    XiveEQ *eq;\n>> +    uint32_t eq_idx;\n>> +    uint32_t priority;\n>> +\n>> +    ive = spapr_xive_get_ive(xive, srcno);\n>> +    if (!ive || !(ive->w & IVE_VALID)) {\n>> +        qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid LISN %d\\n\", srcno);\n>> +        return;\n>> +    }\n>> +\n>> +    if (ive->w & IVE_MASKED) {\n>> +        return;\n>> +    }\n>> +\n>> +    /* Find our XiveEQ */\n>> +    eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);\n>> +    eq = spapr_xive_get_eq(xive, eq_idx);\n>> +    if (!eq) {\n>> +        qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No EQ for LISN %d\\n\", srcno);\n>> +        return;\n>> +    }\n>> +\n>> +    if (eq->w0 & EQ_W0_ENQUEUE) {\n>> +        spapr_xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w));\n>> +    } else {\n>> +        qemu_log_mask(LOG_UNIMP, \"XIVE: !ENQUEUE not implemented\\n\");\n>> +    }\n>> +\n>> +    if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) {\n>> +        qemu_log_mask(LOG_UNIMP, \"XIVE: !UCOND_NOTIFY not implemented\\n\");\n>> +    }\n>> +\n>> +    if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n>> +        priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n>>  \n>> +        /* The EQ is masked. Can this happen ?  */\n>> +        if (priority == 0xff) {\n>> +            return;\n> \n> How does the 8-bit priority field here interact with the 3-bit\n> priority which selects which EQ to use?\n\npriority OxFF is a special case kept for masking, see the hcall \nh_int_set_source_config. It should never reach the EQ lookup \nroutines. So may be an assert would be better here.\n\nC. \n\n> \n>> +        }\n>> +    } else {\n>> +        qemu_log_mask(LOG_UNIMP, \"XIVE: w7 format1 not implemented\\n\");\n>> +    }\n>>  }\n>>  \n>>  /*\n>","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxY6M3g3Jz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 05:36:59 +1000 (AEST)","from localhost ([::1]:45044 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1duOKH-0003Qy-GU\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 15:36:57 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:41977)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1duOJh-0003Ns-Jq\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 15:36:24 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1duOJd-00065a-Fx\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 15:36:21 -0400","from 1.mo2.mail-out.ovh.net ([46.105.63.121]:49257)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <clg@kaod.org>) id 1duOJd-00062d-3v\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 15:36:17 -0400","from player157.ha.ovh.net (b9.ovh.net [213.186.33.59])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 907ECA9EC6\n\tfor <qemu-devel@nongnu.org>; Tue, 19 Sep 2017 21:36:14 +0200 (CEST)","from zorba.kaod.org (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: postmaster@kaod.org)\n\tby player157.ha.ovh.net (Postfix) with ESMTPSA id AF670500087;\n\tTue, 19 Sep 2017 21:36:08 +0200 (CEST)"],"To":"David Gibson <david@gibson.dropbear.id.au>","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-12-clg@kaod.org> <20170919074556.GO27153@umbus>","From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>","Message-ID":"<2d91c586-ff31-ceb8-bee6-6d4531d1b5c0@kaod.org>","Date":"Tue, 19 Sep 2017 21:36:08 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170919074556.GO27153@umbus>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","X-Ovh-Tracer-Id":"8191203297473497976","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrheejgddugeduucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"46.105.63.121","Subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"Alexey Kardashevskiy <aik@ozlabs.ru>, qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"}},{"id":1771630,"web_url":"http://patchwork.ozlabs.org/comment/1771630/","msgid":"<20170920063416.GM5520@umbus.fritz.box>","list_archive_url":null,"date":"2017-09-20T06:34:16","subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Tue, Sep 19, 2017 at 09:36:08PM +0200, Cédric Le Goater wrote:\n> On 09/19/2017 09:45 AM, David Gibson wrote:\n> > On Mon, Sep 11, 2017 at 07:12:25PM +0200, Cédric Le Goater wrote:\n> >> If a triggered event is let through, the Event Queue data defined in\n> >> the associated IVE is pushed in the in-memory event queue. The latter\n> >> is a circular buffer provided by the OS using the H_INT_SET_QUEUE_CONFIG\n> >> hcall, one per target and priority couple. It is composed of Event\n> >> Queue entries which are 4 bytes long, the first bit being a\n> >> 'generation' bit and the 31 following bits the EQ Data field.\n> >>\n> >> The EQ Data field provides a way to set an invariant logical event\n> >> source number for an IRQ. It is set with the H_INT_SET_SOURCE_CONFIG\n> >> hcall.\n> >>\n> >> Notification of the CPU will be done in the following patch.\n> >>\n> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>\n> >> ---\n> >>  hw/intc/spapr_xive.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n> >>  1 file changed, 67 insertions(+)\n> >>\n> >> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n> >> index 557a7e2535b5..4bc61cfda67a 100644\n> >> --- a/hw/intc/spapr_xive.c\n> >> +++ b/hw/intc/spapr_xive.c\n> >> @@ -175,9 +175,76 @@ static const MemoryRegionOps spapr_xive_tm_ops = {\n> >>      },\n> >>  };\n> >>  \n> >> +static void spapr_xive_eq_push(XiveEQ *eq, uint32_t data)\n> >> +{\n> >> +    uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;\n> >> +    uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);\n> >> +    uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);\n> >> +    uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);\n> >> +\n> >> +    uint64_t qaddr = qaddr_base + (qindex << 2);\n> >> +    uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));\n> >> +    uint32_t qentries = 1 << (qsize + 10);\n> >> +\n> >> +    if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) {\n> >> +        qemu_log_mask(LOG_GUEST_ERROR, \"%s: failed to write EQ data @0x%\"\n> >> +                      HWADDR_PRIx \"\\n\", __func__, qaddr);\n> >> +        return;\n> >> +    }\n> >> +\n> >> +    qindex = (qindex + 1) % qentries;\n> >> +    if (qindex == 0) {\n> >> +        qgen ^= 1;\n> >> +        eq->w1 = SETFIELD(EQ_W1_GENERATION, eq->w1, qgen);\n> >> +    }\n> >> +    eq->w1 = SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex);\n> >> +}\n> >> +\n> >>  static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n> >>  {\n> >> +    XiveIVE *ive;\n> >> +    XiveEQ *eq;\n> >> +    uint32_t eq_idx;\n> >> +    uint32_t priority;\n> >> +\n> >> +    ive = spapr_xive_get_ive(xive, srcno);\n> >> +    if (!ive || !(ive->w & IVE_VALID)) {\n> >> +        qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: invalid LISN %d\\n\", srcno);\n> >> +        return;\n> >> +    }\n> >> +\n> >> +    if (ive->w & IVE_MASKED) {\n> >> +        return;\n> >> +    }\n> >> +\n> >> +    /* Find our XiveEQ */\n> >> +    eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);\n> >> +    eq = spapr_xive_get_eq(xive, eq_idx);\n> >> +    if (!eq) {\n> >> +        qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No EQ for LISN %d\\n\", srcno);\n> >> +        return;\n> >> +    }\n> >> +\n> >> +    if (eq->w0 & EQ_W0_ENQUEUE) {\n> >> +        spapr_xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w));\n> >> +    } else {\n> >> +        qemu_log_mask(LOG_UNIMP, \"XIVE: !ENQUEUE not implemented\\n\");\n> >> +    }\n> >> +\n> >> +    if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) {\n> >> +        qemu_log_mask(LOG_UNIMP, \"XIVE: !UCOND_NOTIFY not implemented\\n\");\n> >> +    }\n> >> +\n> >> +    if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n> >> +        priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n> >>  \n> >> +        /* The EQ is masked. Can this happen ?  */\n> >> +        if (priority == 0xff) {\n> >> +            return;\n> > \n> > How does the 8-bit priority field here interact with the 3-bit\n> > priority which selects which EQ to use?\n> \n> priority OxFF is a special case kept for masking, see the hcall \n> h_int_set_source_config. It should never reach the EQ lookup \n> routines. So may be an assert would be better here.\n\nOk, if this situation can't be guest triggered, only by a bug in the\nrest of the XIVE code, then an assert() is better.\n\n> \n> C. \n> \n> > \n> >> +        }\n> >> +    } else {\n> >> +        qemu_log_mask(LOG_UNIMP, \"XIVE: w7 format1 not implemented\\n\");\n> >> +    }\n> >>  }\n> >>  \n> >>  /*\n> > \n>","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"CCCSADTy\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxrBW6pfkz9s7h\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 16:56:35 +1000 (AEST)","from localhost ([::1]:47073 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1duYvx-000169-Al\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Sep 2017 02:56:33 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:41194)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1duYvP-00013A-Of\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 02:56:01 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <dgibson@ozlabs.org>) id 1duYvL-0002VH-PL\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 02:55:59 -0400","from ozlabs.org ([103.22.144.67]:53599)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <dgibson@ozlabs.org>)\n\tid 1duYvL-0002Sj-DZ; Wed, 20 Sep 2017 02:55:55 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xxr9h5l6rz9s7h; Wed, 20 Sep 2017 16:55:52 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1505890552;\n\tbh=7+rLJIbBbRJObO9nT28vuBEhVpiB885ePzfH8KWtZ4s=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=CCCSADTyBIZf+nDqH1B8hZS8/KlgnGbmbnsXv+Dkc5FAapqkljgX38208C9jiU/Lg\n\tVBuumhzKnkDaFGtVpmTPm5dfdG4H3I9HwLvzeGamhqGIaOob5X4ddL00qcMUlMZFIe\n\tjFilXuttgIw39gXEWreuJ0JmQaTTJC59e5b28OH0=","Date":"Wed, 20 Sep 2017 16:34:16 +1000","From":"David Gibson <david@gibson.dropbear.id.au>","To":"=?iso-8859-1?q?C=E9dric?= Le Goater <clg@kaod.org>","Message-ID":"<20170920063416.GM5520@umbus.fritz.box>","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-12-clg@kaod.org>\n\t<20170919074556.GO27153@umbus>\n\t<2d91c586-ff31-ceb8-bee6-6d4531d1b5c0@kaod.org>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"oYAXToTM8kn9Ra/9\"","Content-Disposition":"inline","In-Reply-To":"<2d91c586-ff31-ceb8-bee6-6d4531d1b5c0@kaod.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"103.22.144.67","Subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"Alexey Kardashevskiy <aik@ozlabs.ru>, qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"}},{"id":1776851,"web_url":"http://patchwork.ozlabs.org/comment/1776851/","msgid":"<1506586359.25626.11.camel@kernel.crashing.org>","list_archive_url":null,"date":"2017-09-28T08:12:39","subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","submitter":{"id":38,"url":"http://patchwork.ozlabs.org/api/people/38/","name":"Benjamin Herrenschmidt","email":"benh@kernel.crashing.org"},"content":"On Wed, 2017-09-20 at 16:34 +1000, David Gibson wrote:\n> > >> +    if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n> > >> +        priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n> > >>  \n> > >> +        /* The EQ is masked. Can this happen ?  */\n> > >> +        if (priority == 0xff) {\n> > >> +            return;\n> > > \n> > > How does the 8-bit priority field here interact with the 3-bit\n> > > priority which selects which EQ to use?\n> > \n> > priority OxFF is a special case kept for masking, see the hcall \n> > h_int_set_source_config. It should never reach the EQ lookup \n> > routines. So may be an assert would be better here.\n> \n> Ok, if this situation can't be guest triggered, only by a bug in the\n> rest of the XIVE code, then an assert() is better.\n\nNote: this doesn't match HW. However there's a mask bit in the EAS.\n\nThe problem when masking that way of course is that you lose triggers,\nie P gets set, the interrupt lost, and nobody will clear P.\n\nCheers,\nBen.","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2nWZ6Cbxz9t5x\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 28 Sep 2017 18:13:30 +1000 (AEST)","from localhost ([::1]:57891 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dxTwm-0004U6-VL\n\tfor incoming@patchwork.ozlabs.org; Thu, 28 Sep 2017 04:13:29 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:43522)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <benh@kernel.crashing.org>) id 1dxTwP-0004U1-21\n\tfor qemu-devel@nongnu.org; Thu, 28 Sep 2017 04:13:06 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <benh@kernel.crashing.org>) id 1dxTwL-0004ei-2w\n\tfor qemu-devel@nongnu.org; Thu, 28 Sep 2017 04:13:05 -0400","from gate.crashing.org ([63.228.1.57]:54134)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <benh@kernel.crashing.org>)\n\tid 1dxTwK-0004dp-P3; Thu, 28 Sep 2017 04:13:01 -0400","from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8S8Cd6I028158;\n\tThu, 28 Sep 2017 03:12:41 -0500"],"Message-ID":"<1506586359.25626.11.camel@kernel.crashing.org>","From":"Benjamin Herrenschmidt <benh@kernel.crashing.org>","To":"David Gibson <david@gibson.dropbear.id.au>, =?iso-8859-1?q?C=E9dric?=\n\tLe Goater <clg@kaod.org>","Date":"Thu, 28 Sep 2017 10:12:39 +0200","In-Reply-To":"<20170920063416.GM5520@umbus.fritz.box>","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-12-clg@kaod.org> <20170919074556.GO27153@umbus>\n\t<2d91c586-ff31-ceb8-bee6-6d4531d1b5c0@kaod.org>\n\t<20170920063416.GM5520@umbus.fritz.box>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.24.5 (3.24.5-1.fc26) ","Mime-Version":"1.0","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy]","X-Received-From":"63.228.1.57","Subject":"Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in\n\tOS event queue","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"Alexey Kardashevskiy <aik@ozlabs.ru>, qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"}}]