[{"id":1770848,"web_url":"http://patchwork.ozlabs.org/comment/1770848/","msgid":"<20170919024849.GL27153@umbus>","list_archive_url":null,"date":"2017-09-19T02:48:49","subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Mon, Sep 11, 2017 at 07:12:20PM +0200, Cédric Le Goater wrote:\n> These are very similar to the XICS handlers in a simpler form. They\n> make use of the ICSIRQState array of the XICS interrupt source to\n> differentiate the MSI from the LSI interrupts. The spapr_xive_irq()\n> routine in charge of triggering the CPU interrupt line will be filled\n> later on.\n> \n> The next patch will introduce the MMIO handlers to interact with XIVE\n> interrupt sources.\n> \n> Signed-off-by: Cédric Le Goater \n> ---\n> hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++++++++++++++++++++\n> include/hw/ppc/spapr_xive.h | 1 +\n> 2 files changed, 47 insertions(+)\n> \n> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n> index 52c32f588d6d..1ed7b6a286e9 100644\n> --- a/hw/intc/spapr_xive.c\n> +++ b/hw/intc/spapr_xive.c\n> @@ -27,6 +27,50 @@\n> \n> #include \"xive-internal.h\"\n> \n> +static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n> +{\n> +\n> +}\n> +\n> +/*\n> + * XIVE Interrupt Source\n> + */\n> +static void spapr_xive_source_set_irq_msi(sPAPRXive *xive, int srcno, int val)\n> +{\n> + if (val) {\n> + spapr_xive_irq(xive, srcno);\n> + }\n> +}\n\nSo in XICS \"srcno\" (vs \"irq\") indicates an offset within a single ICS\nobject, as opposed to a global irq number. Does that concept even\nexist in XIVE?\n\n> +\n> +static void spapr_xive_source_set_irq_lsi(sPAPRXive *xive, int srcno, int val)\n> +{\n> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n> +\n> + if (val) {\n> + irq->status |= XICS_STATUS_ASSERTED;\n> + } else {\n> + irq->status &= ~XICS_STATUS_ASSERTED;\n\nMore mangling a XICS specific object for XIVE operations. Please\nstop.\n\n> + }\n> +\n> + if (irq->status & XICS_STATUS_ASSERTED\n> + && !(irq->status & XICS_STATUS_SENT)) {\n> + irq->status |= XICS_STATUS_SENT;\n> + spapr_xive_irq(xive, srcno);\n> + }\n> +}\n> +\n> +static void spapr_xive_source_set_irq(void *opaque, int srcno, int val)\n> +{\n> + sPAPRXive *xive = SPAPR_XIVE(opaque);\n> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n> +\n> + if (irq->flags & XICS_FLAGS_IRQ_LSI) {\n> + spapr_xive_source_set_irq_lsi(xive, srcno, val);\n> + } else {\n> + spapr_xive_source_set_irq_msi(xive, srcno, val);\n> + }\n> +}\n> +\n> /*\n> * Main XIVE object\n> */\n> @@ -80,6 +124,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)\n> }\n> \n> xive->ics = ICS_BASE(obj);\n> + xive->qirqs = qemu_allocate_irqs(spapr_xive_source_set_irq, xive,\n> + xive->nr_irqs);\n> \n> /* Allocate the last IRQ numbers for the IPIs */\n> for (i = xive->nr_irqs - xive->nr_targets; i < xive->nr_irqs; i++) {\n> diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h\n> index 29112589b37f..eab92c4c1bb8 100644\n> --- a/include/hw/ppc/spapr_xive.h\n> +++ b/include/hw/ppc/spapr_xive.h\n> @@ -38,6 +38,7 @@ struct sPAPRXive {\n> \n> /* IRQ */\n> ICSState *ics; /* XICS source inherited from the SPAPR machine */\n> + qemu_irq *qirqs;\n> \n> /* XIVE internal tables */\n> uint8_t *sbe;","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"AjxTdtcY\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxKM46H3cz9sBZ\n\tfor ;\n\tTue, 19 Sep 2017 20:47:12 +1000 (AEST)","from localhost ([::1]:41409 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duG3a-0001Ba-Rr\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 06:47:10 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:51332)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duFta-0001J4-QY\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 06:36:53 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duFtX-0002yR-3F\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 06:36:50 -0400","from ozlabs.org ([103.22.144.67]:53513)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1duFtW-0002sj-Hv; Tue, 19 Sep 2017 06:36:46 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xxK6q643Pz9t4V; Tue, 19 Sep 2017 20:36:34 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1505817395;\n\tbh=UOomysmhlnlxGi/sXaVwztd7dAYD1CZzSvKt3fUIcxk=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=AjxTdtcYFq+jAnXH+s+1BdqwivSZ/nBKTp3crB07OpKi0f/FWLGicOiNb4gm3+2wH\n\t/Q9fexKDSfrZYrZ5cxtMn1HoIRTgR0ZtouaRlMbcIXGOGreOnTGihs6O87UCcX+xPh\n\t7jt2Mllho4Qb8ZVe5U5XmLwRxNmBdHfpItTf0S6k=","Date":"Tue, 19 Sep 2017 12:48:49 +1000","From":"David Gibson ","To":"=?iso-8859-1?q?C=E9dric?= Le Goater ","Message-ID":"<20170919024849.GL27153@umbus>","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-7-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"z9sQuz+HmDh2hVO4\"","Content-Disposition":"inline","In-Reply-To":"<20170911171235.29331-7-clg@kaod.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"103.22.144.67","Subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alexey Kardashevskiy , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1771159,"web_url":"http://patchwork.ozlabs.org/comment/1771159/","msgid":"<7e43adba-0e65-df5f-b87a-e16115fb3c95@kaod.org>","list_archive_url":null,"date":"2017-09-19T15:08:21","subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/","name":"Cédric Le Goater","email":"clg@kaod.org"},"content":"On 09/19/2017 04:48 AM, David Gibson wrote:\n> On Mon, Sep 11, 2017 at 07:12:20PM +0200, Cédric Le Goater wrote:\n>> These are very similar to the XICS handlers in a simpler form. They\n>> make use of the ICSIRQState array of the XICS interrupt source to\n>> differentiate the MSI from the LSI interrupts. The spapr_xive_irq()\n>> routine in charge of triggering the CPU interrupt line will be filled\n>> later on.\n>>\n>> The next patch will introduce the MMIO handlers to interact with XIVE\n>> interrupt sources.\n>>\n>> Signed-off-by: Cédric Le Goater \n>> ---\n>> hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++++++++++++++++++++\n>> include/hw/ppc/spapr_xive.h | 1 +\n>> 2 files changed, 47 insertions(+)\n>>\n>> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n>> index 52c32f588d6d..1ed7b6a286e9 100644\n>> --- a/hw/intc/spapr_xive.c\n>> +++ b/hw/intc/spapr_xive.c\n>> @@ -27,6 +27,50 @@\n>> \n>> #include \"xive-internal.h\"\n>> \n>> +static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n>> +{\n>> +\n>> +}\n>> +\n>> +/*\n>> + * XIVE Interrupt Source\n>> + */\n>> +static void spapr_xive_source_set_irq_msi(sPAPRXive *xive, int srcno, int val)\n>> +{\n>> + if (val) {\n>> + spapr_xive_irq(xive, srcno);\n>> + }\n>> +}\n> \n> So in XICS \"srcno\" (vs \"irq\") indicates an offset within a single ICS\n> object, as opposed to a global irq number. Does that concept even\n> exist in XIVE?\n\nWe don't really care in the internals. 'srcno' is just an index in the \ntables, may be I should change the name. It could be the same in XICS \nbut the xirr is manipulated at low level and so we need to propagate \nthe source offset in a couple of places. \n\nThis to say that the 'irq' number is a guest level information which\nin the patchset should only be used at the hcall level to identify \na source.\n \n>> +\n>> +static void spapr_xive_source_set_irq_lsi(sPAPRXive *xive, int srcno, int val)\n>> +{\n>> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n>> +\n>> + if (val) {\n>> + irq->status |= XICS_STATUS_ASSERTED;\n>> + } else {\n>> + irq->status &= ~XICS_STATUS_ASSERTED;\n> \n> More mangling a XICS specific object for XIVE operations. Please\n> stop.\n\nah ! we will still need the same information and that means introducing \na common source object. The patchset today just uses the XICS ICSIRQState \narray as a common object.\n \n>> + }\n>> +\n>> + if (irq->status & XICS_STATUS_ASSERTED\n>> + && !(irq->status & XICS_STATUS_SENT)) {\n>> + irq->status |= XICS_STATUS_SENT;\n>> + spapr_xive_irq(xive, srcno);\n>> + }\n>> +}\n>> +\n>> +static void spapr_xive_source_set_irq(void *opaque, int srcno, int val)\n>> +{\n>> + sPAPRXive *xive = SPAPR_XIVE(opaque);\n>> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n>> +\n>> + if (irq->flags & XICS_FLAGS_IRQ_LSI) {\n>> + spapr_xive_source_set_irq_lsi(xive, srcno, val);\n>> + } else {\n>> + spapr_xive_source_set_irq_msi(xive, srcno, val);\n>> + }\n>> +}\n>> +\n>> /*\n>> * Main XIVE object\n>> */\n>> @@ -80,6 +124,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)\n>> }\n>> \n>> xive->ics = ICS_BASE(obj);\n>> + xive->qirqs = qemu_allocate_irqs(spapr_xive_source_set_irq, xive,\n>> + xive->nr_irqs);\n>> \n>> /* Allocate the last IRQ numbers for the IPIs */\n>> for (i = xive->nr_irqs - xive->nr_targets; i < xive->nr_irqs; i++) {\n>> diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h\n>> index 29112589b37f..eab92c4c1bb8 100644\n>> --- a/include/hw/ppc/spapr_xive.h\n>> +++ b/include/hw/ppc/spapr_xive.h\n>> @@ -38,6 +38,7 @@ struct sPAPRXive {\n>> \n>> /* IRQ */\n>> ICSState *ics; /* XICS source inherited from the SPAPR machine */\n>> + qemu_irq *qirqs;\n>> \n>> /* XIVE internal tables */\n>> uint8_t *sbe;\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxRsB1Hmlz9sBZ\n\tfor ;\n\tWed, 20 Sep 2017 01:40:14 +1000 (AEST)","from localhost ([::1]:43623 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duKdA-0006oN-7y\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 11:40:12 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:52605)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duK8W-0004FV-Ja\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 11:08:33 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duK8T-0007dW-Qe\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 11:08:32 -0400","from 20.mo3.mail-out.ovh.net ([178.33.47.94]:59009)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1duK8T-0007cc-L7\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 11:08:29 -0400","from player797.ha.ovh.net (b9.ovh.net [213.186.33.59])\n\tby mo3.mail-out.ovh.net (Postfix) with ESMTP id 5482A158D25\n\tfor ; Tue, 19 Sep 2017 17:08:28 +0200 (CEST)","from zorba.kaod.org (deibp9eh1--blueice1n4.emea.ibm.com\n\t[195.212.29.166]) (Authenticated sender: postmaster@kaod.org)\n\tby player797.ha.ovh.net (Postfix) with ESMTPSA id 3DF742E0080;\n\tTue, 19 Sep 2017 17:08:21 +0200 (CEST)"],"To":"David Gibson ","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-7-clg@kaod.org> <20170919024849.GL27153@umbus>","From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","Message-ID":"<7e43adba-0e65-df5f-b87a-e16115fb3c95@kaod.org>","Date":"Tue, 19 Sep 2017 17:08:21 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170919024849.GL27153@umbus>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","X-Ovh-Tracer-Id":"3669307796695059320","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrheejgdekiecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"178.33.47.94","Subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alexey Kardashevskiy , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1771558,"web_url":"http://patchwork.ozlabs.org/comment/1771558/","msgid":"<20170920043852.GG5520@umbus.fritz.box>","list_archive_url":null,"date":"2017-09-20T04:38:52","subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Tue, Sep 19, 2017 at 05:08:21PM +0200, Cédric Le Goater wrote:\n> On 09/19/2017 04:48 AM, David Gibson wrote:\n> > On Mon, Sep 11, 2017 at 07:12:20PM +0200, Cédric Le Goater wrote:\n> >> These are very similar to the XICS handlers in a simpler form. They\n> >> make use of the ICSIRQState array of the XICS interrupt source to\n> >> differentiate the MSI from the LSI interrupts. The spapr_xive_irq()\n> >> routine in charge of triggering the CPU interrupt line will be filled\n> >> later on.\n> >>\n> >> The next patch will introduce the MMIO handlers to interact with XIVE\n> >> interrupt sources.\n> >>\n> >> Signed-off-by: Cédric Le Goater \n> >> ---\n> >> hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++++++++++++++++++++\n> >> include/hw/ppc/spapr_xive.h | 1 +\n> >> 2 files changed, 47 insertions(+)\n> >>\n> >> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n> >> index 52c32f588d6d..1ed7b6a286e9 100644\n> >> --- a/hw/intc/spapr_xive.c\n> >> +++ b/hw/intc/spapr_xive.c\n> >> @@ -27,6 +27,50 @@\n> >> \n> >> #include \"xive-internal.h\"\n> >> \n> >> +static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n> >> +{\n> >> +\n> >> +}\n> >> +\n> >> +/*\n> >> + * XIVE Interrupt Source\n> >> + */\n> >> +static void spapr_xive_source_set_irq_msi(sPAPRXive *xive, int srcno, int val)\n> >> +{\n> >> + if (val) {\n> >> + spapr_xive_irq(xive, srcno);\n> >> + }\n> >> +}\n> > \n> > So in XICS \"srcno\" (vs \"irq\") indicates an offset within a single ICS\n> > object, as opposed to a global irq number. Does that concept even\n> > exist in XIVE?\n> \n> We don't really care in the internals. 'srcno' is just an index in the \n> tables, may be I should change the name. It could be the same in XICS \n> but the xirr is manipulated at low level and so we need to propagate \n> the source offset in a couple of places. \n\nRight. My point is that the XICS code deliberately uses srcno vs. irq\nnames to identify which space we're talking about. If we re-use the\nsrcno name in XIVE where it doesn't really apply that could be\nmisleading.\n\n> This to say that the 'irq' number is a guest level information which\n> in the patchset should only be used at the hcall level to identify \n> a source.\n\nRight, and if there's no need to introduce a number space other than\nthe guest one, we should keep using that everywhere - and give it a\nconsistent name to avoid confusion.\n\n> \n> >> +\n> >> +static void spapr_xive_source_set_irq_lsi(sPAPRXive *xive, int srcno, int val)\n> >> +{\n> >> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n> >> +\n> >> + if (val) {\n> >> + irq->status |= XICS_STATUS_ASSERTED;\n> >> + } else {\n> >> + irq->status &= ~XICS_STATUS_ASSERTED;\n> > \n> > More mangling a XICS specific object for XIVE operations. Please\n> > stop.\n> \n> ah ! we will still need the same information and that means introducing \n> a common source object. The patchset today just uses the XICS ICSIRQState \n> array as a common object.\n\nIt's not really the same information though. For XICS irq->status is\n*all* the information about the line's state, for XIVE, most of that\ninfo is in the PQ bits which are elsewhere. That makes at least some\nof the information in ICSIRQState redundant, and therefore confusing\nand misleading.\n\n> >> + }\n> >> +\n> >> + if (irq->status & XICS_STATUS_ASSERTED\n> >> + && !(irq->status & XICS_STATUS_SENT)) {\n> >> + irq->status |= XICS_STATUS_SENT;\n> >> + spapr_xive_irq(xive, srcno);\n> >> + }\n> >> +}\n> >> +\n> >> +static void spapr_xive_source_set_irq(void *opaque, int srcno, int val)\n> >> +{\n> >> + sPAPRXive *xive = SPAPR_XIVE(opaque);\n> >> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n> >> +\n> >> + if (irq->flags & XICS_FLAGS_IRQ_LSI) {\n> >> + spapr_xive_source_set_irq_lsi(xive, srcno, val);\n> >> + } else {\n> >> + spapr_xive_source_set_irq_msi(xive, srcno, val);\n> >> + }\n> >> +}\n> >> +\n> >> /*\n> >> * Main XIVE object\n> >> */\n> >> @@ -80,6 +124,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)\n> >> }\n> >> \n> >> xive->ics = ICS_BASE(obj);\n> >> + xive->qirqs = qemu_allocate_irqs(spapr_xive_source_set_irq, xive,\n> >> + xive->nr_irqs);\n> >> \n> >> /* Allocate the last IRQ numbers for the IPIs */\n> >> for (i = xive->nr_irqs - xive->nr_targets; i < xive->nr_irqs; i++) {\n> >> diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h\n> >> index 29112589b37f..eab92c4c1bb8 100644\n> >> --- a/include/hw/ppc/spapr_xive.h\n> >> +++ b/include/hw/ppc/spapr_xive.h\n> >> @@ -38,6 +38,7 @@ struct sPAPRXive {\n> >> \n> >> /* IRQ */\n> >> ICSState *ics; /* XICS source inherited from the SPAPR machine */\n> >> + qemu_irq *qirqs;\n> >> \n> >> /* XIVE internal tables */\n> >> uint8_t *sbe;\n> > \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"MWAEeBYW\"; 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boundary=\"WkfBGePaEyrk4zXB\"","Content-Disposition":"inline","In-Reply-To":"<7e43adba-0e65-df5f-b87a-e16115fb3c95@kaod.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"103.22.144.67","Subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alexey Kardashevskiy , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1772827,"web_url":"http://patchwork.ozlabs.org/comment/1772827/","msgid":"<3bd1590c-d58c-0590-3f34-c87936505b5e@kaod.org>","list_archive_url":null,"date":"2017-09-21T14:11:23","subject":"Re: [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers\n\tfor interrupt sources","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/","name":"Cédric Le Goater","email":"clg@kaod.org"},"content":"On 09/20/2017 06:38 AM, David Gibson wrote:\n> On Tue, Sep 19, 2017 at 05:08:21PM +0200, Cédric Le Goater wrote:\n>> On 09/19/2017 04:48 AM, David Gibson wrote:\n>>> On Mon, Sep 11, 2017 at 07:12:20PM +0200, Cédric Le Goater wrote:\n>>>> These are very similar to the XICS handlers in a simpler form. They\n>>>> make use of the ICSIRQState array of the XICS interrupt source to\n>>>> differentiate the MSI from the LSI interrupts. The spapr_xive_irq()\n>>>> routine in charge of triggering the CPU interrupt line will be filled\n>>>> later on.\n>>>>\n>>>> The next patch will introduce the MMIO handlers to interact with XIVE\n>>>> interrupt sources.\n>>>>\n>>>> Signed-off-by: Cédric Le Goater \n>>>> ---\n>>>> hw/intc/spapr_xive.c | 46 +++++++++++++++++++++++++++++++++++++++++++++\n>>>> include/hw/ppc/spapr_xive.h | 1 +\n>>>> 2 files changed, 47 insertions(+)\n>>>>\n>>>> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n>>>> index 52c32f588d6d..1ed7b6a286e9 100644\n>>>> --- a/hw/intc/spapr_xive.c\n>>>> +++ b/hw/intc/spapr_xive.c\n>>>> @@ -27,6 +27,50 @@\n>>>> \n>>>> #include \"xive-internal.h\"\n>>>> \n>>>> +static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n>>>> +{\n>>>> +\n>>>> +}\n>>>> +\n>>>> +/*\n>>>> + * XIVE Interrupt Source\n>>>> + */\n>>>> +static void spapr_xive_source_set_irq_msi(sPAPRXive *xive, int srcno, int val)\n>>>> +{\n>>>> + if (val) {\n>>>> + spapr_xive_irq(xive, srcno);\n>>>> + }\n>>>> +}\n>>>\n>>> So in XICS \"srcno\" (vs \"irq\") indicates an offset within a single ICS\n>>> object, as opposed to a global irq number. Does that concept even\n>>> exist in XIVE?\n>>\n>> We don't really care in the internals. 'srcno' is just an index in the \n>> tables, may be I should change the name. It could be the same in XICS \n>> but the xirr is manipulated at low level and so we need to propagate \n>> the source offset in a couple of places. \n> \n> Right. My point is that the XICS code deliberately uses srcno vs. irq\n> names to identify which space we're talking about. If we re-use the\n> srcno name in XIVE where it doesn't really apply that could be\n> misleading.\n\nyes. ok I will be careful with the naming. \n\n>> This to say that the 'irq' number is a guest level information which\n>> in the patchset should only be used at the hcall level to identify \n>> a source.\n> \n> Right, and if there's no need to introduce a number space other than\n> the guest one, we should keep using that everywhere - and give it a\n> consistent name to avoid confusion.\n\nyes. I agree. I think XICS could benefit from some cleanups.\n\n>>>> +\n>>>> +static void spapr_xive_source_set_irq_lsi(sPAPRXive *xive, int srcno, int val)\n>>>> +{\n>>>> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n>>>> +\n>>>> + if (val) {\n>>>> + irq->status |= XICS_STATUS_ASSERTED;\n>>>> + } else {\n>>>> + irq->status &= ~XICS_STATUS_ASSERTED;\n>>>\n>>> More mangling a XICS specific object for XIVE operations. Please\n>>> stop.\n>>\n>> ah ! we will still need the same information and that means introducing \n>> a common source object. The patchset today just uses the XICS ICSIRQState \n>> array as a common object.\n> \n> It's not really the same information though. For XICS irq->status is\n> *all* the information about the line's state, for XIVE, most of that\n> info is in the PQ bits which are elsewhere. \n\nThis is true.\n\n> That makes at least some of the information in ICSIRQState redundant,> and therefore confusing and misleading.\n\nI will respin the patchset in a different way to distinguish \nxive from xics clearly. I will keep CAS and migration for later. \nThe source should not be too complex to handle but I don't know \nfor the ICP. \n\nThanks,\n\nC.\n\n>>>> + }\n>>>> +\n>>>> + if (irq->status & XICS_STATUS_ASSERTED\n>>>> + && !(irq->status & XICS_STATUS_SENT)) {\n>>>> + irq->status |= XICS_STATUS_SENT;\n>>>> + spapr_xive_irq(xive, srcno);\n>>>> + }\n>>>> +}\n>>>> +\n>>>> +static void spapr_xive_source_set_irq(void *opaque, int srcno, int val)\n>>>> +{\n>>>> + sPAPRXive *xive = SPAPR_XIVE(opaque);\n>>>> + ICSIRQState *irq = &xive->ics->irqs[srcno];\n>>>> +\n>>>> + if (irq->flags & XICS_FLAGS_IRQ_LSI) {\n>>>> + spapr_xive_source_set_irq_lsi(xive, srcno, val);\n>>>> + } else {\n>>>> + spapr_xive_source_set_irq_msi(xive, srcno, val);\n>>>> + }\n>>>> +}\n>>>> +\n>>>> /*\n>>>> * Main XIVE object\n>>>> */\n>>>> @@ -80,6 +124,8 @@ static void spapr_xive_realize(DeviceState *dev, Error **errp)\n>>>> }\n>>>> \n>>>> xive->ics = ICS_BASE(obj);\n>>>> + xive->qirqs = qemu_allocate_irqs(spapr_xive_source_set_irq, xive,\n>>>> + xive->nr_irqs);\n>>>> \n>>>> /* Allocate the last IRQ numbers for the IPIs */\n>>>> for (i = xive->nr_irqs - xive->nr_targets; i < xive->nr_irqs; i++) {\n>>>> diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h\n>>>> index 29112589b37f..eab92c4c1bb8 100644\n>>>> --- a/include/hw/ppc/spapr_xive.h\n>>>> +++ b/include/hw/ppc/spapr_xive.h\n>>>> @@ -38,6 +38,7 @@ struct sPAPRXive {\n>>>> \n>>>> /* IRQ */\n>>>> ICSState *ics; /* XICS source inherited from the SPAPR machine */\n>>>> + qemu_irq *qirqs;\n>>>> \n>>>> /* XIVE internal tables */\n>>>> uint8_t *sbe;\n>>>\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xydq26XN4z9s7f\n\tfor ;\n\tFri, 22 Sep 2017 00:12:30 +1000 (AEST)","from localhost ([::1]:53922 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dv2DM-00075h-US\n\tfor incoming@patchwork.ozlabs.org; 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