[{"id":1766635,"web_url":"http://patchwork.ozlabs.org/comment/1766635/","msgid":"","list_archive_url":null,"date":"2017-09-12T00:39:37","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":66993,"url":"http://patchwork.ozlabs.org/api/people/66993/","name":"Shawn Lin","email":"shawn.lin@rock-chips.com"},"content":"On 2017/9/11 23:10, Jeffy Chen wrote:\n> Add support for PCIE_WAKE pin in rockchip pcie driver.\n> \n> Signed-off-by: Jeffy Chen \n> ---\n> \n\nLGTM,\n\nAcked-by: Shawn Lin \n\n> Changes in v5:\n> Rebase\n> \n> Changes in v3:\n> Fix error handling\n> \n> Changes in v2:\n> Use dev_pm_set_dedicated_wake_irq\n> -- Suggested by Brian Norris \n> \n> drivers/pci/host/pcie-rockchip.c | 19 +++++++++++++++++--\n> 1 file changed, 17 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c\n> index 9051c6c8fea4..a8b7272597a7 100644\n> --- a/drivers/pci/host/pcie-rockchip.c\n> +++ b/drivers/pci/host/pcie-rockchip.c\n> @@ -37,6 +37,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> \n> @@ -995,6 +996,15 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)\n> \t\treturn err;\n> \t}\n> \n> +\t/* Must init wakeup before setting dedicated wakeup irq. */\n> +\tdevice_init_wakeup(dev, true);\n> +\tirq = platform_get_irq_byname(pdev, \"wakeup\");\n> +\tif (irq >= 0) {\n> +\t\terr = dev_pm_set_dedicated_wake_irq(dev, irq);\n> +\t\tif (err)\n> +\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n> +\t}\n> +\n> \treturn 0;\n> }\n> \n> @@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> \n> \terr = rockchip_pcie_parse_dt(rockchip);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_disable_wake;\n> \n> \terr = rockchip_pcie_enable_clocks(rockchip);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_disable_wake;\n> \n> \terr = rockchip_pcie_set_vpcie(rockchip);\n> \tif (err) {\n> @@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> \t\tregulator_disable(rockchip->vpcie0v9);\n> err_set_vpcie:\n> \trockchip_pcie_disable_clocks(rockchip);\n> +err_disable_wake:\n> +\tdev_pm_clear_wake_irq(dev);\n> +\tdevice_init_wakeup(dev, false);\n> \treturn err;\n> }\n> \n> @@ -1682,6 +1695,8 @@ static int rockchip_pcie_remove(struct platform_device *pdev)\n> \tif (!IS_ERR(rockchip->vpcie0v9))\n> \t\tregulator_disable(rockchip->vpcie0v9);\n> \n> +\tdev_pm_clear_wake_irq(dev);\n> +\tdevice_init_wakeup(dev, false);\n> \treturn 0;\n> }\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170911151029.25185-2-jeffy.chen@rock-chips.com>","Content-Type":"text/plain; charset=gbk; format=flowed","Content-Transfer-Encoding":"7bit","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1785960,"web_url":"http://patchwork.ozlabs.org/comment/1785960/","msgid":"<20171013015620.GA94568@google.com>","list_archive_url":null,"date":"2017-10-13T01:56:22","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67074,"url":"http://patchwork.ozlabs.org/api/people/67074/","name":"Brian Norris","email":"briannorris@chromium.org"},"content":"Hi,\n\nOn Mon, Sep 11, 2017 at 11:10:27PM +0800, Jeffy Chen wrote:\n> Add support for PCIE_WAKE pin in rockchip pcie driver.\n> \n> Signed-off-by: Jeffy Chen \n> ---\n> \n> Changes in v5:\n> Rebase\n> \n> Changes in v3:\n> Fix error handling\n> \n> Changes in v2:\n> Use dev_pm_set_dedicated_wake_irq\n> -- Suggested by Brian Norris \n> \n> drivers/pci/host/pcie-rockchip.c | 19 +++++++++++++++++--\n> 1 file changed, 17 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c\n> index 9051c6c8fea4..a8b7272597a7 100644\n> --- a/drivers/pci/host/pcie-rockchip.c\n> +++ b/drivers/pci/host/pcie-rockchip.c\n> @@ -37,6 +37,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> \n> @@ -995,6 +996,15 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)\n> \t\treturn err;\n> \t}\n> \n> +\t/* Must init wakeup before setting dedicated wakeup irq. */\n> +\tdevice_init_wakeup(dev, true);\n\nAm I crazy, or should this go inside the 'irq >= 0' conditional?\nOtherwise, for the whole series:\n\nReviewed-by: Brian Norris \nTested-by: Brian Norris \n\nBjorn, were you planning to pick this up?\n\nAlso, the DT binding change conflicts (just simple context) with the\nPERST# series I just sent out. Would be good if we could land one or\nboth :)\n\nThanks,\nBrian\n\n> +\tirq = platform_get_irq_byname(pdev, \"wakeup\");\n> +\tif (irq >= 0) {\n> +\t\terr = dev_pm_set_dedicated_wake_irq(dev, irq);\n> +\t\tif (err)\n> +\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n> +\t}\n> +\n> \treturn 0;\n> }\n> \n> @@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> \n> \terr = rockchip_pcie_parse_dt(rockchip);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_disable_wake;\n> \n> \terr = rockchip_pcie_enable_clocks(rockchip);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_disable_wake;\n> \n> \terr = rockchip_pcie_set_vpcie(rockchip);\n> \tif (err) {\n> @@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> \t\tregulator_disable(rockchip->vpcie0v9);\n> err_set_vpcie:\n> \trockchip_pcie_disable_clocks(rockchip);\n> +err_disable_wake:\n> +\tdev_pm_clear_wake_irq(dev);\n> +\tdevice_init_wakeup(dev, false);\n> \treturn err;\n> }\n> \n> @@ -1682,6 +1695,8 @@ static int rockchip_pcie_remove(struct platform_device *pdev)\n> \tif (!IS_ERR(rockchip->vpcie0v9))\n> \t\tregulator_disable(rockchip->vpcie0v9);\n> \n> +\tdev_pm_clear_wake_irq(dev);\n> +\tdevice_init_wakeup(dev, false);\n> \treturn 0;\n> }\n> \n> -- \n> 2.11.0\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911151029.25185-2-jeffy.chen@rock-chips.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1785966,"web_url":"http://patchwork.ozlabs.org/comment/1785966/","msgid":"<20171013023246.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-13T02:32:47","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Thu, Oct 12, 2017 at 06:56:22PM -0700, Brian Norris wrote:\n> Hi,\n> \n> On Mon, Sep 11, 2017 at 11:10:27PM +0800, Jeffy Chen wrote:\n> > Add support for PCIE_WAKE pin in rockchip pcie driver.\n> > \n> > Signed-off-by: Jeffy Chen \n> > ---\n> > \n> > Changes in v5:\n> > Rebase\n> > \n> > Changes in v3:\n> > Fix error handling\n> > \n> > Changes in v2:\n> > Use dev_pm_set_dedicated_wake_irq\n> > -- Suggested by Brian Norris \n> > \n> > drivers/pci/host/pcie-rockchip.c | 19 +++++++++++++++++--\n> > 1 file changed, 17 insertions(+), 2 deletions(-)\n> > \n> > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c\n> > index 9051c6c8fea4..a8b7272597a7 100644\n> > --- a/drivers/pci/host/pcie-rockchip.c\n> > +++ b/drivers/pci/host/pcie-rockchip.c\n> > @@ -37,6 +37,7 @@\n> > #include \n> > #include \n> > #include \n> > +#include \n> > #include \n> > #include \n> > \n> > @@ -995,6 +996,15 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)\n> > \t\treturn err;\n> > \t}\n> > \n> > +\t/* Must init wakeup before setting dedicated wakeup irq. */\n> > +\tdevice_init_wakeup(dev, true);\n> \n> Am I crazy, or should this go inside the 'irq >= 0' conditional?\n> Otherwise, for the whole series:\n> \n> Reviewed-by: Brian Norris \n> Tested-by: Brian Norris \n> \n> Bjorn, were you planning to pick this up?\n\nI had already applied this to pci/host-rockchip, but I must have gotten\ninterrupted before sending the email.\n\nBut now that you mention it, I looked at this again and have some\nquestions. I'll respond to the original patch.\n\n> Also, the DT binding change conflicts (just simple context) with the\n> PERST# series I just sent out. Would be good if we could land one or\n> both :)\n> \n> Thanks,\n> Brian\n> \n> > +\tirq = platform_get_irq_byname(pdev, \"wakeup\");\n> > +\tif (irq >= 0) {\n> > +\t\terr = dev_pm_set_dedicated_wake_irq(dev, irq);\n> > +\t\tif (err)\n> > +\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n> > +\t}\n> > +\n> > \treturn 0;\n> > }\n> > \n> > @@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> > \n> > \terr = rockchip_pcie_parse_dt(rockchip);\n> > \tif (err)\n> > -\t\treturn err;\n> > +\t\tgoto err_disable_wake;\n> > \n> > \terr = rockchip_pcie_enable_clocks(rockchip);\n> > \tif (err)\n> > -\t\treturn err;\n> > +\t\tgoto err_disable_wake;\n> > \n> > \terr = rockchip_pcie_set_vpcie(rockchip);\n> > \tif (err) {\n> > @@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> > \t\tregulator_disable(rockchip->vpcie0v9);\n> > err_set_vpcie:\n> > \trockchip_pcie_disable_clocks(rockchip);\n> > +err_disable_wake:\n> > +\tdev_pm_clear_wake_irq(dev);\n> > +\tdevice_init_wakeup(dev, false);\n> > \treturn err;\n> > }\n> > \n> > @@ -1682,6 +1695,8 @@ static int rockchip_pcie_remove(struct platform_device *pdev)\n> > \tif (!IS_ERR(rockchip->vpcie0v9))\n> > \t\tregulator_disable(rockchip->vpcie0v9);\n> > \n> > +\tdev_pm_clear_wake_irq(dev);\n> > +\tdevice_init_wakeup(dev, false);\n> > \treturn 0;\n> > }\n> > \n> > -- \n> > 2.11.0\n> > \n> > \n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yCsFd0tW5z9sNV\n\tfor ;\n\tFri, 13 Oct 2017 13:32:53 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753378AbdJMCcv (ORCPT );\n\tThu, 12 Oct 2017 22:32:51 -0400","from mail.kernel.org ([198.145.29.99]:34158 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753367AbdJMCcu (ORCPT );\n\tThu, 12 Oct 2017 22:32:50 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id B6F5121903;\n\tFri, 13 Oct 2017 02:32:49 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org B6F5121903","Date":"Thu, 12 Oct 2017 21:32:47 -0500","From":"Bjorn Helgaas ","To":"Brian Norris ","Cc":"Jeffy Chen ,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, linux-kernel@vger.kernel.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tbhelgaas@google.com, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Message-ID":"<20171013023246.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013015620.GA94568@google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171013015620.GA94568@google.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1785970,"web_url":"http://patchwork.ozlabs.org/comment/1785970/","msgid":"<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-13T03:04:41","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"[+cc Rafael, linux-pm]\n\nOn Mon, Sep 11, 2017 at 11:10:27PM +0800, Jeffy Chen wrote:\n> Add support for PCIE_WAKE pin in rockchip pcie driver.\n> \n> Signed-off-by: Jeffy Chen \n> ---\n> \n> Changes in v5:\n> Rebase\n> \n> Changes in v3:\n> Fix error handling\n> \n> Changes in v2:\n> Use dev_pm_set_dedicated_wake_irq\n> -- Suggested by Brian Norris \n> \n> drivers/pci/host/pcie-rockchip.c | 19 +++++++++++++++++--\n> 1 file changed, 17 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c\n> index 9051c6c8fea4..a8b7272597a7 100644\n> --- a/drivers/pci/host/pcie-rockchip.c\n> +++ b/drivers/pci/host/pcie-rockchip.c\n> @@ -37,6 +37,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> \n> @@ -995,6 +996,15 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)\n> \t\treturn err;\n> \t}\n> \n> +\t/* Must init wakeup before setting dedicated wakeup irq. */\n> +\tdevice_init_wakeup(dev, true);\n> +\tirq = platform_get_irq_byname(pdev, \"wakeup\");\n> +\tif (irq >= 0) {\n> +\t\terr = dev_pm_set_dedicated_wake_irq(dev, irq);\n\nI'm a little skeptical about dev_pm_set_dedicated_wake_irq(), not\nbecause I know anything at all about it, but because there are only\nfive callers in the whole tree, three of which are in UART code, and\nnone in anything resembling PCI code.\n\nIs Rockchip really that special, or are we going about this the wrong\nway?\n\n> +\t\tif (err)\n> +\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n> +\t}\n> +\n> \treturn 0;\n\nThe above could be structured as:\n\n irq = platform_get_irq_byname(pdev, \"wakeup\");\n if (irq < 0)\n return 0;\n\n device_init_wakeup(dev, true);\n err = dev_pm_set_dedicated_wake_irq(dev, irq);\n if (err) {\n dev_pm_clear_wake_irq(dev);\n device_init_wakeup(dev, false);\n }\n\n return 0;\n\nto unindent the mainline non-error code.\n\n> }\n> \n> @@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> \n> \terr = rockchip_pcie_parse_dt(rockchip);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_disable_wake;\n> \n> \terr = rockchip_pcie_enable_clocks(rockchip);\n> \tif (err)\n> -\t\treturn err;\n> +\t\tgoto err_disable_wake;\n> \n> \terr = rockchip_pcie_set_vpcie(rockchip);\n> \tif (err) {\n> @@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> \t\tregulator_disable(rockchip->vpcie0v9);\n> err_set_vpcie:\n> \trockchip_pcie_disable_clocks(rockchip);\n> +err_disable_wake:\n> +\tdev_pm_clear_wake_irq(dev);\n> +\tdevice_init_wakeup(dev, false);\n\nI think this error cleanup should be done in rockchip_pcie_setup_irq()\nas shown above. There's no real connection between\nrockchip_pcie_probe() and the wake setup.\n\n> \treturn err;\n> }\n> \n> @@ -1682,6 +1695,8 @@ static int rockchip_pcie_remove(struct platform_device *pdev)\n> \tif (!IS_ERR(rockchip->vpcie0v9))\n> \t\tregulator_disable(rockchip->vpcie0v9);\n> \n> +\tdev_pm_clear_wake_irq(dev);\n> +\tdevice_init_wakeup(dev, false);\n> \treturn 0;\n> }\n> \n> -- \n> 2.11.0\n> \n> \n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yCsyb17YVz9s7h\n\tfor ;\n\tFri, 13 Oct 2017 14:04:54 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753291AbdJMDEr (ORCPT );\n\tThu, 12 Oct 2017 23:04:47 -0400","from mail.kernel.org ([198.145.29.99]:37918 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1753191AbdJMDEr (ORCPT );\n\tThu, 12 Oct 2017 23:04:47 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 45FE221908;\n\tFri, 13 Oct 2017 03:04:45 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 45FE221908","Date":"Thu, 12 Oct 2017 22:04:41 -0500","From":"Bjorn Helgaas ","To":"Jeffy Chen ","Cc":"linux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\t\"Rafael J. Wysocki\" , linux-pm@vger.kernel.org","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Message-ID":"<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170911151029.25185-2-jeffy.chen@rock-chips.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786020,"web_url":"http://patchwork.ozlabs.org/comment/1786020/","msgid":"<20171013063100.GB56763@google.com>","list_archive_url":null,"date":"2017-10-13T06:31:00","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67074,"url":"http://patchwork.ozlabs.org/api/people/67074/","name":"Brian Norris","email":"briannorris@chromium.org"},"content":"On Thu, Oct 12, 2017 at 09:32:47PM -0500, Bjorn Helgaas wrote:\n> On Thu, Oct 12, 2017 at 06:56:22PM -0700, Brian Norris wrote:\n> > Bjorn, were you planning to pick this up?\n> \n> I had already applied this to pci/host-rockchip, but I must have gotten\n> interrupted before sending the email.\n\nYou also hadn't merged it into your /next branch either, which is where\nI was looking (and basing my other patch set).\n\n> But now that you mention it, I looked at this again and have some\n> questions. I'll respond to the original patch.\n\nBrian","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=chromium.org header.i=@chromium.org\n\theader.b=\"aFYhJhtX\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yCyXV18YHz9sNr\n\tfor ;\n\tFri, 13 Oct 2017 17:31:06 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752468AbdJMGbE (ORCPT );\n\tFri, 13 Oct 2017 02:31:04 -0400","from mail-pf0-f177.google.com ([209.85.192.177]:55729 \"EHLO\n\tmail-pf0-f177.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751504AbdJMGbD (ORCPT\n\t); Fri, 13 Oct 2017 02:31:03 -0400","by mail-pf0-f177.google.com with SMTP id 17so8618965pfn.12\n\tfor ; Thu, 12 Oct 2017 23:31:03 -0700 (PDT)","from google.com ([2620:0:1000:1600:3454:68dc:8404:7e7b])\n\tby smtp.gmail.com with ESMTPSA id\n\ta25sm829202pfc.143.2017.10.12.23.31.02\n\t(version=TLS1_2 cipher=AES128-SHA bits=128/128);\n\tThu, 12 Oct 2017 23:31:02 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=chromium.org; s=google;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=hEmKaj2mrW3xap2c3JXoHhjQbqbJ0Vd1nMteZwavmdY=;\n\tb=aFYhJhtXvCic0rSZ2djP4dYJtqCVvgS4s6L1IM1A0s9w+5ZgNqUpqQi90cfmkOAVBE\n\tq8/Vpr0TRYQgYGhw6GzN0nXoE5z7j/4QAV8QuL0hiBRLogClRWlZkAyBnIcralpEBP98\n\tRRzfWnPX5CiEWuXCZa8pkxCfGrJzNR3ETudt8=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=hEmKaj2mrW3xap2c3JXoHhjQbqbJ0Vd1nMteZwavmdY=;\n\tb=L6nm/Do0A/w6DnO6YNsxSx0g6oncJM2fWykqlUCSvUh+XiNvP/HyDBT76owN48eiJe\n\tB37+ajzhu/Nd47jBYoyup8WCn9dfCTsvYyvhpiiKhPjlUfYS8j46QQseMX1BWG6Ou8Rv\n\tfCeiFY/IktF5PPD+SkzdwgXA20p2nfMLlgu+eypZkZuTKiMIPx2GagfoEqfUiUaFjiJu\n\tLuKgBeZ7a7OjHQYzEt2yRPuxcTtpn021+06HZlaXja2IQ7bNsQEINYcF/AsJnoQlvjEP\n\tV8k3xzR1DPrng2SslrHST6c2N++/WVvAT8I/Y5IlXSli5oy7o9qhQD7/QHzwGfJchnGq\n\tyPPQ==","X-Gm-Message-State":"AMCzsaUhpQave9l0sLH3EBxcO2Hw4SmGVFzQDc3OfBc6iv3g5ytSGwp3\n\tnX7tQy8f5kq4EAw7NlxQR64SwA==","X-Google-Smtp-Source":"AOwi7QC9oKnUEScWj0UYcj7IviMkxItfSMbDI2/l8/2mRdbkyJWLRBUIbpPv4I5g2U3Ce9D70/xrxQ==","X-Received":"by 10.98.33.80 with SMTP id h77mr464572pfh.18.1507876263207;\n\tThu, 12 Oct 2017 23:31:03 -0700 (PDT)","Date":"Thu, 12 Oct 2017 23:31:00 -0700","From":"Brian Norris ","To":"Bjorn Helgaas ","Cc":"Jeffy Chen ,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, linux-kernel@vger.kernel.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tbhelgaas@google.com, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Message-ID":"<20171013063100.GB56763@google.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013015620.GA94568@google.com>\n\t<20171013023246.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171013023246.GZ25517@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786273,"web_url":"http://patchwork.ozlabs.org/comment/1786273/","msgid":"<2453698.N4jfPaHx71@aspire.rjw.lan>","list_archive_url":null,"date":"2017-10-13T13:21:41","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":26536,"url":"http://patchwork.ozlabs.org/api/people/26536/","name":"Rafael J. Wysocki","email":"rjw@rjwysocki.net"},"content":"[+cc Tony]\n\nOn Friday, October 13, 2017 5:04:41 AM CEST Bjorn Helgaas wrote:\n> [+cc Rafael, linux-pm]\n> \n> On Mon, Sep 11, 2017 at 11:10:27PM +0800, Jeffy Chen wrote:\n> > Add support for PCIE_WAKE pin in rockchip pcie driver.\n> > \n> > Signed-off-by: Jeffy Chen \n> > ---\n> > \n> > Changes in v5:\n> > Rebase\n> > \n> > Changes in v3:\n> > Fix error handling\n> > \n> > Changes in v2:\n> > Use dev_pm_set_dedicated_wake_irq\n> > -- Suggested by Brian Norris \n> > \n> > drivers/pci/host/pcie-rockchip.c | 19 +++++++++++++++++--\n> > 1 file changed, 17 insertions(+), 2 deletions(-)\n> > \n> > diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c\n> > index 9051c6c8fea4..a8b7272597a7 100644\n> > --- a/drivers/pci/host/pcie-rockchip.c\n> > +++ b/drivers/pci/host/pcie-rockchip.c\n> > @@ -37,6 +37,7 @@\n> > #include \n> > #include \n> > #include \n> > +#include \n> > #include \n> > #include \n> > \n> > @@ -995,6 +996,15 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)\n> > \t\treturn err;\n> > \t}\n> > \n> > +\t/* Must init wakeup before setting dedicated wakeup irq. */\n> > +\tdevice_init_wakeup(dev, true);\n> > +\tirq = platform_get_irq_byname(pdev, \"wakeup\");\n> > +\tif (irq >= 0) {\n> > +\t\terr = dev_pm_set_dedicated_wake_irq(dev, irq);\n> \n> I'm a little skeptical about dev_pm_set_dedicated_wake_irq(), not\n> because I know anything at all about it, but because there are only\n> five callers in the whole tree, three of which are in UART code, and\n> none in anything resembling PCI code.\n> \n> Is Rockchip really that special, or are we going about this the wrong\n> way?\n> \n> > +\t\tif (err)\n> > +\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n> > +\t}\n> > +\n> > \treturn 0;\n> \n> The above could be structured as:\n> \n> irq = platform_get_irq_byname(pdev, \"wakeup\");\n> if (irq < 0)\n> return 0;\n> \n> device_init_wakeup(dev, true);\n> err = dev_pm_set_dedicated_wake_irq(dev, irq);\n> if (err) {\n> dev_pm_clear_wake_irq(dev);\n> device_init_wakeup(dev, false);\n> }\n> \n> return 0;\n> \n> to unindent the mainline non-error code.\n> \n> > }\n> > \n> > @@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> > \n> > \terr = rockchip_pcie_parse_dt(rockchip);\n> > \tif (err)\n> > -\t\treturn err;\n> > +\t\tgoto err_disable_wake;\n> > \n> > \terr = rockchip_pcie_enable_clocks(rockchip);\n> > \tif (err)\n> > -\t\treturn err;\n> > +\t\tgoto err_disable_wake;\n> > \n> > \terr = rockchip_pcie_set_vpcie(rockchip);\n> > \tif (err) {\n> > @@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> > \t\tregulator_disable(rockchip->vpcie0v9);\n> > err_set_vpcie:\n> > \trockchip_pcie_disable_clocks(rockchip);\n> > +err_disable_wake:\n> > +\tdev_pm_clear_wake_irq(dev);\n> > +\tdevice_init_wakeup(dev, false);\n> \n> I think this error cleanup should be done in rockchip_pcie_setup_irq()\n> as shown above. There's no real connection between\n> rockchip_pcie_probe() and the wake setup.\n> \n> > \treturn err;\n> > }\n> > \n> > @@ -1682,6 +1695,8 @@ static int rockchip_pcie_remove(struct platform_device *pdev)\n> > \tif (!IS_ERR(rockchip->vpcie0v9))\n> > \t\tregulator_disable(rockchip->vpcie0v9);\n> > \n> > +\tdev_pm_clear_wake_irq(dev);\n> > +\tdevice_init_wakeup(dev, false);\n> > \treturn 0;\n> > }\n> > \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yD7sX4gzfz9sNr\n\tfor ;\n\tSat, 14 Oct 2017 00:31:28 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1757969AbdJMNbO (ORCPT );\n\tFri, 13 Oct 2017 09:31:14 -0400","from cloudserver094114.home.net.pl ([79.96.170.134]:50542 \"EHLO\n\tcloudserver094114.home.net.pl\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1753258AbdJMNbN (ORCPT\n\t); Fri, 13 Oct 2017 09:31:13 -0400","from 79.184.255.244.ipv4.supernova.orange.pl (79.184.255.244)\n\t(HELO aspire.rjw.lan)\n\tby serwer1319399.home.pl (79.96.170.134) with SMTP (IdeaSmtpServer\n\t0.82) id aeb4bcbf3d47d997; Fri, 13 Oct 2017 15:31:11 +0200"],"From":"\"Rafael J. Wysocki\" ","To":"Bjorn Helgaas ","Cc":"Jeffy Chen ,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org,\n\tTony Lindgren ","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Date":"Fri, 13 Oct 2017 15:21:41 +0200","Message-ID":"<2453698.N4jfPaHx71@aspire.rjw.lan>","In-Reply-To":"<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"7Bit","Content-Type":"text/plain; charset=\"us-ascii\"","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786506,"web_url":"http://patchwork.ozlabs.org/comment/1786506/","msgid":"<20171013175825.GR4394@atomide.com>","list_archive_url":null,"date":"2017-10-13T17:58:26","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":365,"url":"http://patchwork.ozlabs.org/api/people/365/","name":"Tony Lindgren","email":"tony@atomide.com"},"content":"* Rafael J. Wysocki [171013 06:32]:\n> [+cc Tony]\n> \n> On Friday, October 13, 2017 5:04:41 AM CEST Bjorn Helgaas wrote:\n> > [+cc Rafael, linux-pm]\n> > On Mon, Sep 11, 2017 at 11:10:27PM +0800, Jeffy Chen wrote:\n> > > Add support for PCIE_WAKE pin in rockchip pcie driver.\n...\n> > > @@ -995,6 +996,15 @@ static int rockchip_pcie_setup_irq(struct rockchip_pcie *rockchip)\n> > > \t\treturn err;\n> > > \t}\n> > > \n> > > +\t/* Must init wakeup before setting dedicated wakeup irq. */\n> > > +\tdevice_init_wakeup(dev, true);\n> > > +\tirq = platform_get_irq_byname(pdev, \"wakeup\");\n> > > +\tif (irq >= 0) {\n> > > +\t\terr = dev_pm_set_dedicated_wake_irq(dev, irq);\n> > \n> > I'm a little skeptical about dev_pm_set_dedicated_wake_irq(), not\n> > because I know anything at all about it, but because there are only\n> > five callers in the whole tree, three of which are in UART code, and\n> > none in anything resembling PCI code.\n\nWell it should work for any device that can provide an out of band wakeup\ninterrupt such as a dedicated GPIO line.\n\n> > Is Rockchip really that special, or are we going about this the wrong\n> > way?\n\nMaybe this can be set up in a generic way somewhere similar to what\nthe I2C bus is doing?\n\nSee i2c_device_probe() for dev_pm_set_dedicated_wake_irq() in\ndrivers/i2c/i2c-core-base.c.\n\nRegards,\n\nTony","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDFnj56fDz9s82\n\tfor ;\n\tSat, 14 Oct 2017 04:58:33 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751901AbdJMR6b (ORCPT );\n\tFri, 13 Oct 2017 13:58:31 -0400","from muru.com ([72.249.23.125]:44178 \"EHLO muru.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751612AbdJMR6a (ORCPT );\n\tFri, 13 Oct 2017 13:58:30 -0400","from atomide.com (localhost [127.0.0.1])\n\tby muru.com (Postfix) with ESMTPS id F3E198167;\n\tFri, 13 Oct 2017 17:59:41 +0000 (UTC)"],"Date":"Fri, 13 Oct 2017 10:58:26 -0700","From":"Tony Lindgren ","To":"\"Rafael J. Wysocki\" ","Cc":"Bjorn Helgaas ,\n\tJeffy Chen ,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Message-ID":"<20171013175825.GR4394@atomide.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>\n\t<2453698.N4jfPaHx71@aspire.rjw.lan>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<2453698.N4jfPaHx71@aspire.rjw.lan>","User-Agent":"Mutt/1.9.0 (2017-09-02)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786534,"web_url":"http://patchwork.ozlabs.org/comment/1786534/","msgid":"<59E10709.4020300@rock-chips.com>","list_archive_url":null,"date":"2017-10-13T18:33:45","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67754,"url":"http://patchwork.ozlabs.org/api/people/67754/","name":"Jeffy Chen","email":"jeffy.chen@rock-chips.com"},"content":"Hi Rafael,\n\nOn 10/13/2017 09:21 PM, Rafael J. Wysocki wrote:\n>>\n>>I'm a little skeptical about dev_pm_set_dedicated_wake_irq(), not\n>>because I know anything at all about it, but because there are only\n>>five callers in the whole tree, three of which are in UART code, and\n>>none in anything resembling PCI code.\n>>\n>>Is Rockchip really that special, or are we going about this the wrong\n>>way?\n\nwe used to put these codes in the wifi driver, but another wifi vendor \nsuggests these should go into the pcie driver.\n\nand as tony said, it could go into pcie common code :)\n>>\n>> > >+\t\tif (err)\n>> > >+\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n>> > >+\t}\n>> > >+\n>> > > \treturn 0;\n>>\n>>The above could be structured as:\n>>\n>> irq = platform_get_irq_byname(pdev, \"wakeup\");\n>> if (irq < 0)\n>> return 0;\n>>\n>> device_init_wakeup(dev, true);\n>> err = dev_pm_set_dedicated_wake_irq(dev, irq);\n>> if (err) {\n>> dev_pm_clear_wake_irq(dev);\n>> device_init_wakeup(dev, false);\n>> }\n>>\nthere's no need to call dev_pm_clear_wake_irq when \ndev_pm_set_dedicated_wake_irq failed...and i agree the \ndevice_init_wakeup part, i'll add that in the next version(with brian's \ncomment too)\n>> return 0;\n>>\n>>to unindent the mainline non-error code.\n>>\n>> > > }\n>> > >\n>> > >@@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n>> > >\n>> > > \terr = rockchip_pcie_parse_dt(rockchip);\n>> > > \tif (err)\n>> > >-\t\treturn err;\n>> > >+\t\tgoto err_disable_wake;\n>> > >\n>> > > \terr = rockchip_pcie_enable_clocks(rockchip);\n>> > > \tif (err)\n>> > >-\t\treturn err;\n>> > >+\t\tgoto err_disable_wake;\n>> > >\n>> > > \terr = rockchip_pcie_set_vpcie(rockchip);\n>> > > \tif (err) {\n>> > >@@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n>> > > \t\tregulator_disable(rockchip->vpcie0v9);\n>> > > err_set_vpcie:\n>> > > \trockchip_pcie_disable_clocks(rockchip);\n>> > >+err_disable_wake:\n>> > >+\tdev_pm_clear_wake_irq(dev);\n>> > >+\tdevice_init_wakeup(dev, false);\n>>\n>>I think this error cleanup should be done in rockchip_pcie_setup_irq()\n>>as shown above. There's no real connection between\n>>rockchip_pcie_probe() and the wake setup.\n\nthis error handling is like inline \"rockchip_pcie_cleanup_irq()\", and \nthey are harmless to be called even if we don't have the wakeup irq :)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDGZX70LXz9s1h\n\tfor ;\n\tSat, 14 Oct 2017 05:33:56 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751279AbdJMSdy (ORCPT );\n\tFri, 13 Oct 2017 14:33:54 -0400","from regular1.263xmail.com ([211.150.99.131]:50464 \"EHLO\n\tregular1.263xmail.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751081AbdJMSdx (ORCPT\n\t); Fri, 13 Oct 2017 14:33:53 -0400","from jeffy.chen?rock-chips.com (unknown [192.168.167.76])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 2B98661EB;\n\tSat, 14 Oct 2017 02:33:48 +0800 (CST)","from [172.16.22.86] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 6B08938B;\n\tSat, 14 Oct 2017 02:33:47 +0800 (CST)","from [172.16.22.86] (unknown [103.29.142.67])\n\tby smtp.263.net (Postfix) whith ESMTP id 13677W6LXDP;\n\tSat, 14 Oct 2017 02:33:50 +0800 (CST)"],"X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"jeffy.chen@rock-chips.com","X-FST-TO":"rjw@rjwysocki.net","X-SENDER-IP":"103.29.142.67","X-LOGIN-NAME":"jeffy.chen@rock-chips.com","X-UNIQUE-TAG":"<1a0bde58e3282179d6881f6db236e29f>","X-ATTACHMENT-NUM":"0","X-SENDER":"cjf@rock-chips.com","X-DNS-TYPE":"0","Message-ID":"<59E10709.4020300@rock-chips.com>","Date":"Sat, 14 Oct 2017 02:33:45 +0800","From":"jeffy ","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:19.0) Gecko/20130126 Thunderbird/19.0","MIME-Version":"1.0","To":"\"Rafael J. Wysocki\" ,\n\tBjorn Helgaas ","CC":"linux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org,\n\tTony Lindgren ","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>\n\t<2453698.N4jfPaHx71@aspire.rjw.lan>","In-Reply-To":"<2453698.N4jfPaHx71@aspire.rjw.lan>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786585,"web_url":"http://patchwork.ozlabs.org/comment/1786585/","msgid":"<20171013191906.GF25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-13T19:19:06","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Sat, Oct 14, 2017 at 02:33:45AM +0800, jeffy wrote:\n> Hi Rafael,\n> \n> On 10/13/2017 09:21 PM, Rafael J. Wysocki wrote:\n> >>\n> >>I'm a little skeptical about dev_pm_set_dedicated_wake_irq(), not\n> >>because I know anything at all about it, but because there are only\n> >>five callers in the whole tree, three of which are in UART code, and\n> >>none in anything resembling PCI code.\n> >>\n> >>Is Rockchip really that special, or are we going about this the wrong\n> >>way?\n> \n> we used to put these codes in the wifi driver, but another wifi\n> vendor suggests these should go into the pcie driver.\n> \n> and as tony said, it could go into pcie common code :)\n\nI guess the implication (I'm speculating here) is that in most\nexisting cases, the WAKE# signal is fielded by an ACPI BIOS, which\nknows how it's connected. I suppose that would end up being turned\ninto an SCI that Linux already knows how to handle generically.\n\nAnd further, that the non-ACPI drivers are relatively new and you're\nthe first attempt to use WAKE# with a non-ACPI PCI host driver?\n\nIf this setup could be done somewhere in PCIe common code, that would\nbe great. We have so much copy and pasted code already, it'd be nice\nto avoid adding more. I don't know if this would fit in\npci_scan_root_bus_bridge(), doing something like dma_configure() does\nto get hold of a struct platform_device * or a struct device * so you\ncould lookup the IRQ?\n\n> >>> >+\t\tif (err)\n> >>> >+\t\t\tdev_err(dev, \"failed to setup PCIe wakeup IRQ\\n\");\n> >>> >+\t}\n> >>> >+\n> >>> > \treturn 0;\n> >>\n> >>The above could be structured as:\n> >>\n> >> irq = platform_get_irq_byname(pdev, \"wakeup\");\n> >> if (irq < 0)\n> >> return 0;\n> >>\n> >> device_init_wakeup(dev, true);\n> >> err = dev_pm_set_dedicated_wake_irq(dev, irq);\n> >> if (err) {\n> >> dev_pm_clear_wake_irq(dev);\n> >> device_init_wakeup(dev, false);\n> >> }\n> >>\n> there's no need to call dev_pm_clear_wake_irq when\n> dev_pm_set_dedicated_wake_irq failed...and i agree the\n> device_init_wakeup part, i'll add that in the next version(with\n> brian's comment too)\n> >> return 0;\n> >>\n> >>to unindent the mainline non-error code.\n> >>\n> >>> > }\n> >>> >\n> >>> >@@ -1542,11 +1552,11 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> >>> >\n> >>> > \terr = rockchip_pcie_parse_dt(rockchip);\n> >>> > \tif (err)\n> >>> >-\t\treturn err;\n> >>> >+\t\tgoto err_disable_wake;\n> >>> >\n> >>> > \terr = rockchip_pcie_enable_clocks(rockchip);\n> >>> > \tif (err)\n> >>> >-\t\treturn err;\n> >>> >+\t\tgoto err_disable_wake;\n> >>> >\n> >>> > \terr = rockchip_pcie_set_vpcie(rockchip);\n> >>> > \tif (err) {\n> >>> >@@ -1656,6 +1666,9 @@ static int rockchip_pcie_probe(struct platform_device *pdev)\n> >>> > \t\tregulator_disable(rockchip->vpcie0v9);\n> >>> > err_set_vpcie:\n> >>> > \trockchip_pcie_disable_clocks(rockchip);\n> >>> >+err_disable_wake:\n> >>> >+\tdev_pm_clear_wake_irq(dev);\n> >>> >+\tdevice_init_wakeup(dev, false);\n> >>\n> >>I think this error cleanup should be done in rockchip_pcie_setup_irq()\n> >>as shown above. There's no real connection between\n> >>rockchip_pcie_probe() and the wake setup.\n> \n> this error handling is like inline \"rockchip_pcie_cleanup_irq()\",\n> and they are harmless to be called even if we don't have the wakeup\n> irq :)\n\nI'm sure they're harmless. The point is that the cleanup should be\ndone near the failure, not in the caller of the caller of the function\nwhere the failure was detected. You have:\n\n rockchip_pcie_probe\n rockchip_pcie_parse_dt\n rockchip_pcie_setup_irq\n err = dev_pm_set_dedicated_wake_irq\n if (err)\n dev_err(...)\n\nSo you detect the error in rockchip_pcie_setup_irq(), but you clean up\nfrom it in rockchip_pcie_probe(), which doesn't make sense because\nrockchip_pcie_probe() doesn't do anything related to wakeup interupts.\n\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDHZm6bNqz9sDB\n\tfor ;\n\tSat, 14 Oct 2017 06:19:12 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751165AbdJMTTK (ORCPT );\n\tFri, 13 Oct 2017 15:19:10 -0400","from mail.kernel.org ([198.145.29.99]:43830 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751138AbdJMTTJ (ORCPT );\n\tFri, 13 Oct 2017 15:19:09 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id A6D9D219DC;\n\tFri, 13 Oct 2017 19:19:08 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org A6D9D219DC","Date":"Fri, 13 Oct 2017 14:19:06 -0500","From":"Bjorn Helgaas ","To":"jeffy ","Cc":"\"Rafael J. Wysocki\" ,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org,\n\tTony Lindgren ","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Message-ID":"<20171013191906.GF25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>\n\t<2453698.N4jfPaHx71@aspire.rjw.lan>\n\t<59E10709.4020300@rock-chips.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<59E10709.4020300@rock-chips.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786597,"web_url":"http://patchwork.ozlabs.org/comment/1786597/","msgid":"<59E11358.3090409@rock-chips.com>","list_archive_url":null,"date":"2017-10-13T19:26:16","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67754,"url":"http://patchwork.ozlabs.org/api/people/67754/","name":"Jeffy Chen","email":"jeffy.chen@rock-chips.com"},"content":"Hi Bjorn,\n\nOn 10/14/2017 03:19 AM, Bjorn Helgaas wrote:\n> I'm sure they're harmless. The point is that the cleanup should be\n> done near the failure, not in the caller of the caller of the function\n> where the failure was detected. You have:\n>\n> rockchip_pcie_probe\n> rockchip_pcie_parse_dt\n> rockchip_pcie_setup_irq\n> err = dev_pm_set_dedicated_wake_irq\n> if (err)\n> dev_err(...)\n>\n> So you detect the error in rockchip_pcie_setup_irq(), but you clean up\n> from it in rockchip_pcie_probe(), which doesn't make sense because\n> rockchip_pcie_probe() doesn't do anything related to wakeup interupts.\n>\nright, but if something wrong happens in rockchip_pcie_probe() later \nthan rockchip_pcie_setup_irq(), we may still need to clean it up ;)\n\ni think the error handling is a little like what we do in the remove \ncallback\n> Bjorn\n>\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDHlP5bXRz9sRW\n\tfor ;\n\tSat, 14 Oct 2017 06:26:41 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751623AbdJMT01 (ORCPT );\n\tFri, 13 Oct 2017 15:26:27 -0400","from regular1.263xmail.com ([211.150.99.137]:45544 \"EHLO\n\tregular1.263xmail.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751138AbdJMT00 (ORCPT\n\t); Fri, 13 Oct 2017 15:26:26 -0400","from jeffy.chen?rock-chips.com (unknown [192.168.167.183])\n\tby regular1.263xmail.com (Postfix) with ESMTP id 6504EDB38;\n\tSat, 14 Oct 2017 03:26:18 +0800 (CST)","from [172.16.22.86] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id CD5EC345;\n\tSat, 14 Oct 2017 03:26:17 +0800 (CST)","from [172.16.22.86] (unknown [103.29.142.67])\n\tby smtp.263.net (Postfix) whith ESMTP id 27725X0IOX2;\n\tSat, 14 Oct 2017 03:26:21 +0800 (CST)"],"X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"jeffy.chen@rock-chips.com","X-FST-TO":"helgaas@kernel.org","X-SENDER-IP":"103.29.142.67","X-LOGIN-NAME":"jeffy.chen@rock-chips.com","X-UNIQUE-TAG":"<646ab2bd8ffb7015988cbae18509aeb7>","X-ATTACHMENT-NUM":"0","X-SENDER":"cjf@rock-chips.com","X-DNS-TYPE":"0","Message-ID":"<59E11358.3090409@rock-chips.com>","Date":"Sat, 14 Oct 2017 03:26:16 +0800","From":"jeffy ","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:19.0) Gecko/20130126 Thunderbird/19.0","MIME-Version":"1.0","To":"Bjorn Helgaas ","CC":"\"Rafael J. Wysocki\" ,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, linux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org,\n\tTony Lindgren ","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>\n\t<2453698.N4jfPaHx71@aspire.rjw.lan>\n\t<59E10709.4020300@rock-chips.com>\n\t<20171013191906.GF25517@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20171013191906.GF25517@bhelgaas-glaptop.roam.corp.google.com>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1786657,"web_url":"http://patchwork.ozlabs.org/comment/1786657/","msgid":"<20171013204358.GA3585@google.com>","list_archive_url":null,"date":"2017-10-13T20:44:00","subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","submitter":{"id":67074,"url":"http://patchwork.ozlabs.org/api/people/67074/","name":"Brian Norris","email":"briannorris@chromium.org"},"content":"Hi,\n\nOn Fri, Oct 13, 2017 at 02:19:06PM -0500, Bjorn Helgaas wrote:\n> On Sat, Oct 14, 2017 at 02:33:45AM +0800, jeffy wrote:\n> > Hi Rafael,\n> > \n> > On 10/13/2017 09:21 PM, Rafael J. Wysocki wrote:\n> > >>\n> > >>I'm a little skeptical about dev_pm_set_dedicated_wake_irq(), not\n> > >>because I know anything at all about it, but because there are only\n> > >>five callers in the whole tree, three of which are in UART code, and\n> > >>none in anything resembling PCI code.\n> > >>\n> > >>Is Rockchip really that special, or are we going about this the wrong\n> > >>way?\n> > \n> > we used to put these codes in the wifi driver, but another wifi\n> > vendor suggests these should go into the pcie driver.\n> > \n> > and as tony said, it could go into pcie common code :)\n> \n> I guess the implication (I'm speculating here) is that in most\n> existing cases, the WAKE# signal is fielded by an ACPI BIOS, which\n> knows how it's connected. I suppose that would end up being turned\n> into an SCI that Linux already knows how to handle generically.\n\nI wasn't sure how ACPI did this when I first suggested Rockchip take\nthis approach, but since then I believe have figured it out. We have:\n\npci_prepare_to_sleep() -> pci_enable_wake()\n\nwhere pci_enable_wake() will configure PME wakeup and/or \"platform\" wake\n(which presumably is the WAKE# signal). pci-acpi.c has registered hooks\nfor the latter via pci_set_platform_pm().\n\nThis doesn't really make it any more generic for discovering this\nplatform-specific detail. We'd have to set up some kind of platform ops\nthat could be shared for any DT-based platforms.\n\nBut that *does* answer the question I had about conditionality: should\nwe always enable WAKE# for platforms that have the pin hooked up to the\nhost? Or is this configured on a per-device basis? IIUC, the intention\nis that there's only a single open-drain WAKE# pin for the whole system,\nand it's just pulled high for EPs that don't implement it.\n\n> And further, that the non-ACPI drivers are relatively new and you're\n> the first attempt to use WAKE# with a non-ACPI PCI host driver?\n\nQuite possibly. Or everyone just sidestepped this an configured the pin\nelsewhere (e.g., you could stick a GPIO like this into a gpio-keys\ndevice and it would mostly work).\n\n> If this setup could be done somewhere in PCIe common code, that would\n> be great. We have so much copy and pasted code already, it'd be nice\n> to avoid adding more. I don't know if this would fit in\n> pci_scan_root_bus_bridge(), doing something like dma_configure() does\n> to get hold of a struct platform_device * or a struct device * so you\n> could lookup the IRQ?\n\nIt looks like the infrastructure is in pci_set_platform_pm(), sort of.\nBut that still doesn't help you for the repetition; you're just lucky\nyou only have 2 controller drivers that call this right now :)\n\nSide note: there's some dissonance between this statement, in\nDocumentation/driver-api/pm/devices.rst:\n\n\"Device drivers, however, are not expected to call\n:c:func:`device_set_wakeup_enable()` directly in any case.\"\n\nYet:\n\n$ git grep -l device_set_wakeup_enable drivers/ | wc -l\n69\n\nAnd particularly, I believe that was necessary for Wifi drivers like\ndrivers/net/wireless/ath/ath10k/wow.c.\n\nBrian","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=chromium.org header.i=@chromium.org\n\theader.b=\"TEmShPQd\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDKSl0Fmpz9sRm\n\tfor ;\n\tSat, 14 Oct 2017 07:44:07 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751680AbdJMUoE (ORCPT );\n\tFri, 13 Oct 2017 16:44:04 -0400","from mail-pf0-f181.google.com ([209.85.192.181]:47063 \"EHLO\n\tmail-pf0-f181.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751420AbdJMUoD (ORCPT\n\t); Fri, 13 Oct 2017 16:44:03 -0400","by mail-pf0-f181.google.com with SMTP id p87so11266692pfj.3\n\tfor ; Fri, 13 Oct 2017 13:44:03 -0700 (PDT)","from google.com ([2620:0:1000:1600:55ef:4ed7:1a34:623c])\n\tby smtp.gmail.com with ESMTPSA id\n\td76sm4181851pfk.69.2017.10.13.13.44.01\n\t(version=TLS1_2 cipher=AES128-SHA bits=128/128);\n\tFri, 13 Oct 2017 13:44:02 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=chromium.org; s=google;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=5n6/PRpFHsfaeG25+AwAJUP8g3/UHWf5K7kb1DJZ4RU=;\n\tb=TEmShPQdOVIikqYy/jW93GuXJv+zLfInryNnQ5/6DRq8jZAYYFGMlZBV2/Pz6i/h4K\n\t4luawcRDpnavH2KLuJCuGihbWdZ+HUtBnLdJGFbpHng1GqvqbXTd8TECyqJFE5VEGW3Z\n\txBI/Ah2SpGLK1ZjZ86IxX7+E9Jix6+HXv6bD0=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=5n6/PRpFHsfaeG25+AwAJUP8g3/UHWf5K7kb1DJZ4RU=;\n\tb=fIrBEnY4HknoD549mparj+xDHjGlEvbMkvoqMFIwREYlrZ90yPrx3tLAz+5k5On2g0\n\tMvcC+kAzF4sm3aa4ApBwhqSJqKeKzlpY+kAkwuGhYSUmZNgcSLWWne1Len6jxtPY0ony\n\tINwRBzf5h0TeaPlr5IJGalulMT80S+1lArhuRS3+m0uAMD7vgHFmrXaLRdnHbiJRMV7z\n\t0TeBTvXhb7vZJIj4GSSuWSfkccKnb6nmwJpz4nqGD3WC8nW0p4zwkawxiTk51yyeAypE\n\tZFZ6Mhg5nwbu4GixOyjKlp0tCu8Bq85F7y1kOsDRGOkxZCVj9iTFk/mdkQ4N7s/zIcRd\n\tFKXA==","X-Gm-Message-State":"AMCzsaXmQ05q2yGABTo7H8LppSfH2b+dj6X8ToCz+a0+Shq/64+IFQni\n\tq/i5Kg3d5KjjfQJDe8zXf+CICA==","X-Google-Smtp-Source":"AOwi7QBO9nhRv/nZ7oRLrXr0gxfI8rvWIONTzDuDgWBxXQIJ6O79Izpps11SZDfGXPg8C0gg6NAqxg==","X-Received":"by 10.99.110.7 with SMTP id j7mr720175pgc.241.1507927442950;\n\tFri, 13 Oct 2017 13:44:02 -0700 (PDT)","Date":"Fri, 13 Oct 2017 13:44:00 -0700","From":"Brian Norris ","To":"Bjorn Helgaas ","Cc":"jeffy ,\n\t\"Rafael J. Wysocki\" ,\n\tlinux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tHeiko Stuebner , linux-pci@vger.kernel.org,\n\tshawn.lin@rock-chips.com, dianders@chromium.org,\n\tlinux-rockchip@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org,\n\tTony Lindgren ","Subject":"Re: [PATCH v5 1/3] PCI: rockchip: Add support for pcie wake irq","Message-ID":"<20171013204358.GA3585@google.com>","References":"<20170911151029.25185-1-jeffy.chen@rock-chips.com>\n\t<20170911151029.25185-2-jeffy.chen@rock-chips.com>\n\t<20171013030441.GA25517@bhelgaas-glaptop.roam.corp.google.com>\n\t<2453698.N4jfPaHx71@aspire.rjw.lan>\n\t<59E10709.4020300@rock-chips.com>\n\t<20171013191906.GF25517@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171013191906.GF25517@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]