[{"id":1770449,"web_url":"http://patchwork.ozlabs.org/comment/1770449/","msgid":"<20170918194625.xz5y7tkemjnbwunh@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-18T19:46:25","subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Fri, Sep 08, 2017 at 06:53:07PM -0700, Brendan Higgins wrote:\n> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n> specific device tree for the NPCM750 (Poleg) evaluation board.\n> \n> Signed-off-by: Brendan Higgins \n> Reviewed-by: Tomer Maimon \n> Reviewed-by: Avi Fishman \n> Reviewed-by: Joel Stanley \n> Tested-by: Tomer Maimon \n> Tested-by: Avi Fishman \n> ---\n> .../arm/cpu-enable-method/nuvoton,npcm7xx-smp | 42 +++++\n> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +\n> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 57 +++++++\n> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 177 +++++++++++++++++++++\n> include/dt-bindings/clock/nuvoton,npcm7xx-clks.h | 39 +++++\n> 5 files changed, 321 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> create mode 100644 include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> \n> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> new file mode 100644\n> index 000000000000..e81f85b400cf\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm7xx-smp\n> @@ -0,0 +1,42 @@\n> +=========================================================\n> +Secondary CPU enable-method \"nuvoton,npcm7xx-smp\" binding\n> +=========================================================\n> +\n> +To apply to all CPUs, a single \"nuvoton,npcm7xx-smp\" enable method should be\n> +defined in the \"cpus\" node.\n> +\n> +Enable method name:\t\"nuvoton,npcm7xx-smp\"\n> +Compatible machines:\t\"nuvoton,npcm750\"\n> +Compatible CPUs:\t\"arm,cortex-a9\"\n> +Related properties:\t(none)\n> +\n> +Note:\n> +This enable method needs valid nodes compatible with \"arm,cortex-a9-scu\" and\n> +\"nuvoton,npcm750-gcr\".\n> +\n> +Example:\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n> +\n> +\t\tcpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <0>;\n> +\t\t\tnext-level-cache = <&L2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <1>;\n> +\t\t\tnext-level-cache = <&L2>;\n> +\t\t};\n> +\t};\n> +\n> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> new file mode 100644\n> index 000000000000..2d87d9ecea85\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt\n> @@ -0,0 +1,6 @@\n> +NPCM Platforms Device Tree Bindings\n> +-----------------------------------\n> +NPCM750 SoC\n> +Required root node properties:\n> +\t- compatible = \"nuvoton,npcm750\";\n> +\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> new file mode 100644\n> index 000000000000..e54a870d3ee0\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts\n> @@ -0,0 +1,57 @@\n> +/*\n> + * DTS file for all NPCM750 SoCs\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +/dts-v1/;\n> +#include \"nuvoton-npcm750.dtsi\"\n> +\n> +/ {\n> +\tmodel = \"Nuvoton npcm750 Development Board (Device Tree)\";\n> +\tcompatible = \"nuvoton,npcm750\";\n> +\n> +\tchosen {\n> +\t\tstdout-path = &serial3;\n\nstdout-path is a path string, not a phandle.\n\n> +\t\tbootargs = \"earlyprintk=serial,serial3,115200\";\n\nThat's not valid bootargs with mainline.\n\n> +\t};\n> +\n> +\tmemory {\n> +\t\treg = <0 0x40000000>;\n> +\t};\n> +\n> +\tcpus {\n> +\t\tenable-method = \"nuvoton,npcm7xx-smp\";\n\nThis is not a board specific property. Belongs in the SoC dtsi.\n\n> +\t};\n> +};\n> +\n> +&clk {\n> +\tstatus = \"okay\";\n\nPretty sure you'd always want the clock controller enabled.\n\n> +};\n> +\n> +&watchdog1 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial0 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial1 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial2 {\n> +\tstatus = \"okay\";\n> +};\n> +\n> +&serial3 {\n> +\tstatus = \"okay\";\n> +};\n> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> new file mode 100644\n> index 000000000000..bca96b3ae9d3\n> --- /dev/null\n> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi\n> @@ -0,0 +1,177 @@\n> +/*\n> + * DTSi file for the NPCM750 SoC\n> + *\n> + * Copyright 2012 Tomer Maimon \n> + *\n> + * The code contained herein is licensed under the GNU General Public\n> + * License. You may obtain a copy of the GNU General Public License\n> + * Version 2 or later at the following locations:\n> + *\n> + * http://www.opensource.org/licenses/gpl-license.html\n> + * http://www.gnu.org/copyleft/gpl.html\n> + */\n> +\n> +#include \"skeleton.dtsi\"\n\nDon't use skeleton.dtsi. We want to remove it.\n\n> +#include \n> +#include \n> +\n> +/ {\n> +\t#address-cells = <1>;\n> +\t#size-cells = <1>;\n> +\tinterrupt-parent = <&gic>;\n> +\n> +\tcpus {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\tcpu@0 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <0>;\n> +\t\t\tnext-level-cache = <&l2>;\n> +\t\t};\n> +\n> +\t\tcpu@1 {\n> +\t\t\tdevice_type = \"cpu\";\n> +\t\t\tcompatible = \"arm,cortex-a9\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_CPU>;\n> +\t\t\tclock-names = \"clk_cpu\";\n> +\t\t\treg = <1>;\n> +\t\t\tnext-level-cache = <&l2>;\n> +\t\t};\n> +\t};\n> +\n> +\tgcr: gcr@f0800000 {\n> +\t\tcompatible = \"nuvoton,npcm750-gcr\", \"syscon\",\n> +\t\t\t\"simple-mfd\";\n> +\t\treg = <0xf0800000 0x1000>;\n> +\t};\n> +\n> +\tscu: scu@f03fe000 {\n> +\t\tcompatible = \"arm,cortex-a9-scu\";\n> +\t\treg = <0xf03fe000 0x1000>;\n> +\t};\n> +\n> +\tl2: l2-cache@f03fc000 {\n\ncache-controller@...\n\n> +\t\tcompatible = \"arm,pl310-cache\";\n> +\t\treg = <0xf03fc000 0x1000>;\n> +\t\tinterrupts = <0 21 4>;\n> +\t\tcache-unified;\n> +\t\tcache-level = <2>;\n> +\t\tclocks = <&clk NPCM7XX_CLK_AXI>;\n> +\t};\n> +\n> +\tgic: interrupt-controller@f03ff000 {\n> +\t\tcompatible = \"arm,cortex-a9-gic\";\n> +\t\tinterrupt-controller;\n> +\t\t#interrupt-cells = <3>;\n> +\t\treg = <0xf03ff000 0x1000>,\n> +\t\t <0xf03fe100 0x100>;\n> +\t};\n> +\n> +\tclk: clock-controller@f0801000 {\n> +\t\tcompatible = \"nuvoton,npcm750-clk\";\n> +\t\t#clock-cells = <1>;\n> +\t\treg = <0xf0801000 0x1000>;\n> +\t};\n\nAll these memory mapped peripherals should be under a bus/soc node\n\n> +\n> +\t/* external clock signal rg1refck, supplied by the phy */\n> +\tclk-rg1refck {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <125000000>;\n> +\t};\n> +\n> +\t/* external clock signal rg2refck, supplied by the phy */\n> +\tclk-rg2refck {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <125000000>;\n> +\t};\n> +\n> +\tclk-xin {\n> +\t\tcompatible = \"fixed-clock\";\n> +\t\t#clock-cells = <0>;\n> +\t\tclock-frequency = <50000000>;\n> +\t};\n> +\n> +\ttimer@f03fe600 {\n> +\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n> +\t\treg = <0xf03fe600 0x20>;\n> +\t\tinterrupts = <1 13 0x304>;\n> +\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t};\n> +\n> +\tapb {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <1>;\n> +\t\tcompatible = \"simple-bus\";\n> +\t\tinterrupt-parent = <&gic>;\n> +\t\tranges;\n\nIt's preferred to have actual values here and limit the address range of \nthe bus.\n\n> +\n> +\t\ttimer0: timer@f0000000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-timer\";\n> +\t\t\tinterrupts = <0 32 4>;\n> +\t\t\treg = <0xf0000000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\twatchdog0: watchdog@f0008000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\tinterrupts = <0 47 4>;\n> +\t\t\treg = <0xf0008000 0x1000>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\twatchdog1: watchdog@f0009000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\tinterrupts = <0 48 4>;\n> +\t\t\treg = <0xf0009000 0x1000>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\twatchdog2: watchdog@f000a000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-wdt\";\n> +\t\t\tinterrupts = <0 49 4>;\n> +\t\t\treg = <0xf000a000 0x1000>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_TIMER>;\n> +\t\t};\n> +\n> +\t\tserial0: serial0@f0001000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0001000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 2 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tserial1: serial1@f0002000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0002000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 3 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tserial2: serial2@f0003000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0003000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 4 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\n> +\t\tserial3: serial3@f0004000 {\n> +\t\t\tcompatible = \"nuvoton,npcm750-uart\";\n> +\t\t\treg = <0xf0004000 0x1000>;\n> +\t\t\tclocks = <&clk NPCM7XX_CLK_UART_CORE>;\n> +\t\t\tinterrupts = <0 5 4>;\n> +\t\t\tstatus = \"disabled\";\n> +\t\t};\n> +\t};\n> +};\n> diff --git a/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> new file mode 100644\n> index 000000000000..c69d3bbf7e42\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/nuvoton,npcm7xx-clks.h\n> @@ -0,0 +1,39 @@\n> +/*\n> + * Copyright (C) 2016 Nuvoton Technologies, tali.perry@nuvoton.com\n> + *\n> + * This software is licensed under the terms of the GNU General Public\n> + * License version 2, as published by the Free Software Foundation, and\n> + * may be copied, distributed, and modified under those terms.\n> + */\n> +\n> +#ifndef _DT_BINDINGS_CLK_NPCM7XX_H\n> +#define _DT_BINDINGS_CLK_NPCM7XX_H\n> +\n> +#define NPCM7XX_CLK_PLL0\t0\n> +#define NPCM7XX_CLK_PLL1\t1\n> +#define NPCM7XX_CLK_PLL2\t2\n> +#define NPCM7XX_CLK_GFX\t\t3\n> +#define NPCM7XX_CLK_APB1\t4\n> +#define NPCM7XX_CLK_APB2\t5\n> +#define NPCM7XX_CLK_APB3\t6\n> +#define NPCM7XX_CLK_APB4\t7\n> +#define NPCM7XX_CLK_APB5\t8\n> +#define NPCM7XX_CLK_MC\t\t9\n> +#define NPCM7XX_CLK_CPU\t\t10\n> +#define NPCM7XX_CLK_SPI0\t11\n> +#define NPCM7XX_CLK_SPI3\t12\n> +#define NPCM7XX_CLK_SPIX\t13\n> +#define NPCM7XX_CLK_UART_CORE\t14\n> +#define NPCM7XX_CLK_TIMER\t15\n> +#define NPCM7XX_CLK_HOST_UART\t16\n> +#define NPCM7XX_CLK_MMC\t\t17\n> +#define NPCM7XX_CLK_SDHC\t18\n> +#define NPCM7XX_CLK_ADC\t\t19\n> +#define NPCM7XX_CLK_GFX_MEM\t20\n> +#define NPCM7XX_CLK_USB_BRIDGE\t21\n> +#define NPCM7XX_CLK_AXI\t\t22\n> +#define NPCM7XX_CLK_AHB\t\t23\n> +#define NPCM7XX_CLK_EMC\t\t24\n> +#define NPCM7XX_CLK_GMAC\t25\n> +\n> +#endif\n> -- \n> 2.14.1.581.gf28d330327-goog\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with 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","Cc":"mark.rutland@arm.com, linux@armlinux.org.uk,\n\tavifishman70@gmail.com, tmaimon77@gmail.com, raltherr@google.com,\n\tf.fainelli@gmail.com, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\topenbmc@lists.ozlabs.org","Subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","Message-ID":"<20170918194625.xz5y7tkemjnbwunh@rob-hp-laptop>","References":"<20170909015308.30001-1-brendanhiggins@google.com>\n\t<20170909015308.30001-3-brendanhiggins@google.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170909015308.30001-3-brendanhiggins@google.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770475,"web_url":"http://patchwork.ozlabs.org/comment/1770475/","msgid":"","list_archive_url":null,"date":"2017-09-18T20:37:33","subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Sep 18, 2017 at 2:46 PM, Rob Herring wrote:\n> On Fri, Sep 08, 2017 at 06:53:07PM -0700, Brendan Higgins wrote:\n>> Add a common device tree for all Nuvoton NPCM750 BMCs and a board\n>> specific device tree for the NPCM750 (Poleg) evaluation board.\n\n[...]\n\n>> +/ {\n>> + model = \"Nuvoton npcm750 Development Board (Device Tree)\";\n>> + compatible = \"nuvoton,npcm750\";\n>> +\n>> + chosen {\n>> + stdout-path = &serial3;\n>\n> stdout-path is a path string, not a phandle.\n\nSorry, it's Monday and my brain is not working. This is fine.\n\nRob\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwyW92x5Rz9s78\n\tfor ;\n\tTue, 19 Sep 2017 06:37:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750868AbdIRUhz (ORCPT\n\t);\n\tMon, 18 Sep 2017 16:37:55 -0400","from mail.kernel.org ([198.145.29.99]:47108 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750791AbdIRUhz (ORCPT );\n\tMon, 18 Sep 2017 16:37:55 -0400","from mail-qt0-f176.google.com (mail-qt0-f176.google.com\n\t[209.85.216.176])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id A2D2221E91;\n\tMon, 18 Sep 2017 20:37:54 +0000 (UTC)","by mail-qt0-f176.google.com with SMTP id f15so1849122qtf.7;\n\tMon, 18 Sep 2017 13:37:54 -0700 (PDT)","by 10.12.209.75 with HTTP; Mon, 18 Sep 2017 13:37:33 -0700 (PDT)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org A2D2221E91","X-Gm-Message-State":"AHPjjUiE+sXS05mAd+Yba6pMNtT0iUQCcLkfoApAlYUXAkrQuiK6CWA4\n\tKJaQVP2hklnbyE8BqLfcfAh6pYZOkVGW6lIUIA==","X-Google-Smtp-Source":"AOwi7QDJPO6ZbaCgRwaC6gdp3fim+cOWKrpIgc1YLGne9cuZpoR1STBqX0F6DsUUJSXJWSx5JQfCFgG431qVxoRzsjU=","X-Received":"by 10.200.26.211 with SMTP id h19mr52648003qtk.341.1505767073832;\n\tMon, 18 Sep 2017 13:37:53 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170918194625.xz5y7tkemjnbwunh@rob-hp-laptop>","References":"<20170909015308.30001-1-brendanhiggins@google.com>\n\t<20170909015308.30001-3-brendanhiggins@google.com>\n\t<20170918194625.xz5y7tkemjnbwunh@rob-hp-laptop>","From":"Rob Herring ","Date":"Mon, 18 Sep 2017 15:37:33 -0500","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v5 2/3] arm: dts: add Nuvoton NPCM750 device tree","To":"Brendan Higgins ","Cc":"Mark Rutland ,\n\tRussell King , avifishman70@gmail.com,\n\ttmaimon77@gmail.com, Rick Altherr ,\n\tFlorian Fainelli ,\n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t, openbmc@lists.ozlabs.org","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]