[{"id":1789126,"web_url":"http://patchwork.ozlabs.org/comment/1789126/","msgid":"<20171018154831.50b2abcb@firefly.ozlabs.ibm.com>","date":"2017-10-18T04:48:31","subject":"Re: [PATCH 17/25] powerpc: helper to validate key-access\n\tpermissions of a pte","submitter":{"id":9347,"url":"http://patchwork.ozlabs.org/api/people/9347/","name":"Balbir Singh","email":"bsingharora@gmail.com"},"content":"On Fri, 8 Sep 2017 15:45:05 -0700\nRam Pai wrote:\n\n> helper function that checks if the read/write/execute is allowed\n> on the pte.\n> \n> Signed-off-by: Ram Pai \n> ---\n> arch/powerpc/include/asm/book3s/64/pgtable.h | 4 +++\n> arch/powerpc/include/asm/pkeys.h | 12 +++++++++++\n> arch/powerpc/mm/pkeys.c | 28 ++++++++++++++++++++++++++\n> 3 files changed, 44 insertions(+), 0 deletions(-)\n> \n> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> index 5935d4e..bd244b3 100644\n> --- a/arch/powerpc/include/asm/book3s/64/pgtable.h\n> +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> @@ -492,6 +492,10 @@ static inline void write_uamor(u64 value)\n> \tmtspr(SPRN_UAMOR, value);\n> }\n> \n> +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS\n> +extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);\n> +#endif /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n> +\n> #define __HAVE_ARCH_PTEP_GET_AND_CLEAR\n> static inline pte_t ptep_get_and_clear(struct mm_struct *mm,\n> \t\t\t\t unsigned long addr, pte_t *ptep)\n> diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h\n> index cd3924c..50522a0 100644\n> --- a/arch/powerpc/include/asm/pkeys.h\n> +++ b/arch/powerpc/include/asm/pkeys.h\n> @@ -80,6 +80,18 @@ static inline u64 pte_to_hpte_pkey_bits(u64 pteflags)\n> \t\t((pteflags & H_PAGE_PKEY_BIT4) ? HPTE_R_KEY_BIT4 : 0x0UL));\n> }\n> \n> +static inline u16 pte_to_pkey_bits(u64 pteflags)\n> +{\n> +\tif (!pkey_inited)\n> +\t\treturn 0x0UL;\n> +\n> +\treturn (((pteflags & H_PAGE_PKEY_BIT0) ? 0x10 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT1) ? 0x8 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT2) ? 0x4 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT3) ? 0x2 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT4) ? 0x1 : 0x0UL));\n> +}\n> +\n> #define ARCH_VM_PKEY_FLAGS (VM_PKEY_BIT0 | VM_PKEY_BIT1 | VM_PKEY_BIT2 | \\\n> \t\t\t\tVM_PKEY_BIT3 | VM_PKEY_BIT4)\n> #define AMR_BITS_PER_PKEY 2\n> diff --git a/arch/powerpc/mm/pkeys.c b/arch/powerpc/mm/pkeys.c\n> index fb1a76a..24589d9 100644\n> --- a/arch/powerpc/mm/pkeys.c\n> +++ b/arch/powerpc/mm/pkeys.c\n> @@ -292,3 +292,31 @@ int __arch_override_mprotect_pkey(struct vm_area_struct *vma, int prot,\n> \t */\n> \treturn vma_pkey(vma);\n> }\n> +\n> +static bool pkey_access_permitted(int pkey, bool write, bool execute)\n> +{\n> +\tint pkey_shift;\n> +\tu64 amr;\n> +\n> +\tif (!pkey)\n> +\t\treturn true;\n\nWhy would we have pkey set to 0, it's reserved. Why do we return true?\n\n> +\n> +\tpkey_shift = pkeyshift(pkey);\n> +\tif (!(read_uamor() & (0x3UL << pkey_shift)))\n> +\t\treturn true;\n> +\n> +\tif (execute && !(read_iamr() & (IAMR_EX_BIT << pkey_shift)))\n> +\t\treturn true;\n> +\n> +\tamr = read_amr(); /* delay reading amr uptil absolutely needed*/\n> +\treturn ((!write && !(amr & (AMR_RD_BIT << pkey_shift))) ||\n> +\t\t(write && !(amr & (AMR_WR_BIT << pkey_shift))));\n> +}\n> +\n> +bool arch_pte_access_permitted(u64 pte, bool write, bool execute)\n> +{\n> +\tif (!pkey_inited)\n> +\t\treturn true;\n\nAgain, don't like the pkey_inited bits :)\n\n> +\treturn pkey_access_permitted(pte_to_pkey_bits(pte),\n> +\t\t\twrite, execute);\n> +}\n\nBalbir Singh","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yH03j2y0Fz9t2d\n\tfor ;\n\tWed, 18 Oct 2017 15:50:09 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yH03j1VnMzDrJj\n\tfor ;\n\tWed, 18 Oct 2017 15:50:09 +1100 (AEDT)","from mail-pf0-x244.google.com (mail-pf0-x244.google.com\n\t[IPv6:2607:f8b0:400e:c00::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yH0243LXVzDrD6\n\tfor ;\n\tWed, 18 Oct 2017 15:48:43 +1100 (AEDT)","by mail-pf0-x244.google.com with SMTP id b85so3020942pfj.13\n\tfor ;\n\tTue, 17 Oct 2017 21:48:43 -0700 (PDT)","from firefly.ozlabs.ibm.com ([122.99.82.10])\n\tby smtp.gmail.com with ESMTPSA id\n\th22sm4699526pfi.64.2017.10.17.21.48.37\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 17 Oct 2017 21:48:41 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BftpA+n5\"; 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x86_64-redhat-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"ebiederm@xmission.com, mhocko@kernel.org, paulus@samba.org,\n\taneesh.kumar@linux.vnet.ibm.com, bauerman@linux.vnet.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, khandual@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1789977,"web_url":"http://patchwork.ozlabs.org/comment/1789977/","msgid":"<20171018211917.GK5617@ram.oc3035372033.ibm.com>","date":"2017-10-18T21:19:17","subject":"Re: [PATCH 17/25] powerpc: helper to validate key-access permissions\n\tof a pte","submitter":{"id":2667,"url":"http://patchwork.ozlabs.org/api/people/2667/","name":"Ram Pai","email":"linuxram@us.ibm.com"},"content":"On Wed, Oct 18, 2017 at 03:48:31PM +1100, Balbir Singh wrote:\n> On Fri, 8 Sep 2017 15:45:05 -0700\n> Ram Pai wrote:\n> \n> > helper function that checks if the read/write/execute is allowed\n> > on the pte.\n> > \n> > Signed-off-by: Ram Pai \n> > ---\n> > arch/powerpc/include/asm/book3s/64/pgtable.h | 4 +++\n> > arch/powerpc/include/asm/pkeys.h | 12 +++++++++++\n> > arch/powerpc/mm/pkeys.c | 28 ++++++++++++++++++++++++++\n> > 3 files changed, 44 insertions(+), 0 deletions(-)\n> > \n> > diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> > index 5935d4e..bd244b3 100644\n> > --- a/arch/powerpc/include/asm/book3s/64/pgtable.h\n> > +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> > @@ -492,6 +492,10 @@ static inline void write_uamor(u64 value)\n> > \tmtspr(SPRN_UAMOR, value);\n> > }\n> > \n> > +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS\n> > +extern bool arch_pte_access_permitted(u64 pte, bool write, bool execute);\n> > +#endif /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n> > +\n> > #define __HAVE_ARCH_PTEP_GET_AND_CLEAR\n> > static inline pte_t ptep_get_and_clear(struct mm_struct *mm,\n> > \t\t\t\t unsigned long addr, pte_t *ptep)\n> > diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h\n> > index cd3924c..50522a0 100644\n> > --- a/arch/powerpc/include/asm/pkeys.h\n> > +++ b/arch/powerpc/include/asm/pkeys.h\n> > @@ -80,6 +80,18 @@ static inline u64 pte_to_hpte_pkey_bits(u64 pteflags)\n> > \t\t((pteflags & H_PAGE_PKEY_BIT4) ? HPTE_R_KEY_BIT4 : 0x0UL));\n> > }\n> > \n> > +static inline u16 pte_to_pkey_bits(u64 pteflags)\n> > +{\n> > +\tif (!pkey_inited)\n> > +\t\treturn 0x0UL;\n> > +\n> > +\treturn (((pteflags & H_PAGE_PKEY_BIT0) ? 0x10 : 0x0UL) |\n> > +\t\t((pteflags & H_PAGE_PKEY_BIT1) ? 0x8 : 0x0UL) |\n> > +\t\t((pteflags & H_PAGE_PKEY_BIT2) ? 0x4 : 0x0UL) |\n> > +\t\t((pteflags & H_PAGE_PKEY_BIT3) ? 0x2 : 0x0UL) |\n> > +\t\t((pteflags & H_PAGE_PKEY_BIT4) ? 0x1 : 0x0UL));\n> > +}\n> > +\n> > #define ARCH_VM_PKEY_FLAGS (VM_PKEY_BIT0 | VM_PKEY_BIT1 | VM_PKEY_BIT2 | \\\n> > \t\t\t\tVM_PKEY_BIT3 | VM_PKEY_BIT4)\n> > #define AMR_BITS_PER_PKEY 2\n> > diff --git a/arch/powerpc/mm/pkeys.c b/arch/powerpc/mm/pkeys.c\n> > index fb1a76a..24589d9 100644\n> > --- a/arch/powerpc/mm/pkeys.c\n> > +++ b/arch/powerpc/mm/pkeys.c\n> > @@ -292,3 +292,31 @@ int __arch_override_mprotect_pkey(struct vm_area_struct *vma, int prot,\n> > \t */\n> > \treturn vma_pkey(vma);\n> > }\n> > +\n> > +static bool pkey_access_permitted(int pkey, bool write, bool execute)\n> > +{\n> > +\tint pkey_shift;\n> > +\tu64 amr;\n> > +\n> > +\tif (!pkey)\n> > +\t\treturn true;\n> \n> Why would we have pkey set to 0, it's reserved. Why do we return true?\n\npkey 0 is reserved in some weird sense. it is the default key which is\nomnipresent, which cannot be allocated or freed, but can be used any time and\nallows read/write/execute at all times.\n\n> \n> > +\n> > +\tpkey_shift = pkeyshift(pkey);\n> > +\tif (!(read_uamor() & (0x3UL << pkey_shift)))\n> > +\t\treturn true;\n> > +\n> > +\tif (execute && !(read_iamr() & (IAMR_EX_BIT << pkey_shift)))\n> > +\t\treturn true;\n> > +\n> > +\tamr = read_amr(); /* delay reading amr uptil absolutely needed*/\n> > +\treturn ((!write && !(amr & (AMR_RD_BIT << pkey_shift))) ||\n> > +\t\t(write && !(amr & (AMR_WR_BIT << pkey_shift))));\n> > +}\n> > +\n> > +bool arch_pte_access_permitted(u64 pte, bool write, bool execute)\n> > +{\n> > +\tif (!pkey_inited)\n> > +\t\treturn true;\n> \n> Again, don't like the pkey_inited bits :)\n\nsuggest something. :) running out of ideas ;)\n\n> \n> > +\treturn pkey_access_permitted(pte_to_pkey_bits(pte),\n> > +\t\t\twrite, execute);\n> > +}\n> \n> Balbir Singh","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yHQ2b1pvcz9t7D\n\tfor ;\n\tThu, 19 Oct 2017 08:20:39 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yHQ2Z2qSRzDqmQ\n\tfor ;\n\tThu, 19 Oct 2017 08:20:38 +1100 (AEDT)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yHQ1D6Sl4zDqJ7\n\tfor ;\n\tThu, 19 Oct 2017 08:19:28 +1100 (AEDT)","from pps.filterd (m0098409.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv9ILIuB8004873\n\tfor ; Wed, 18 Oct 2017 17:19:26 -0400","from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2dp9p5150k-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 18 Oct 2017 17:19:26 -0400","from localhost\n\tby e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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