[{"id":1789124,"web_url":"http://patchwork.ozlabs.org/comment/1789124/","msgid":"<20171018154327.2cafadf2@firefly.ozlabs.ibm.com>","date":"2017-10-18T04:43:27","subject":"Re: [PATCH 16/25] powerpc: Program HPTE key protection bits","submitter":{"id":9347,"url":"http://patchwork.ozlabs.org/api/people/9347/","name":"Balbir Singh","email":"bsingharora@gmail.com"},"content":"On Fri, 8 Sep 2017 15:45:04 -0700\nRam Pai wrote:\n\n> Map the PTE protection key bits to the HPTE key protection bits,\n> while creating HPTE entries.\n> \n> Signed-off-by: Ram Pai \n> ---\n> arch/powerpc/include/asm/book3s/64/mmu-hash.h | 5 +++++\n> arch/powerpc/include/asm/mmu_context.h | 6 ++++++\n> arch/powerpc/include/asm/pkeys.h | 13 +++++++++++++\n> arch/powerpc/mm/hash_utils_64.c | 1 +\n> 4 files changed, 25 insertions(+), 0 deletions(-)\n> \n> diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n> index 508275b..2e22357 100644\n> --- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n> +++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h\n> @@ -90,6 +90,8 @@\n> #define HPTE_R_PP0\t\tASM_CONST(0x8000000000000000)\n> #define HPTE_R_TS\t\tASM_CONST(0x4000000000000000)\n> #define HPTE_R_KEY_HI\t\tASM_CONST(0x3000000000000000)\n> +#define HPTE_R_KEY_BIT0\t\tASM_CONST(0x2000000000000000)\n> +#define HPTE_R_KEY_BIT1\t\tASM_CONST(0x1000000000000000)\n> #define HPTE_R_RPN_SHIFT\t12\n> #define HPTE_R_RPN\t\tASM_CONST(0x0ffffffffffff000)\n> #define HPTE_R_RPN_3_0\t\tASM_CONST(0x01fffffffffff000)\n> @@ -104,6 +106,9 @@\n> #define HPTE_R_C\t\tASM_CONST(0x0000000000000080)\n> #define HPTE_R_R\t\tASM_CONST(0x0000000000000100)\n> #define HPTE_R_KEY_LO\t\tASM_CONST(0x0000000000000e00)\n> +#define HPTE_R_KEY_BIT2\t\tASM_CONST(0x0000000000000800)\n> +#define HPTE_R_KEY_BIT3\t\tASM_CONST(0x0000000000000400)\n> +#define HPTE_R_KEY_BIT4\t\tASM_CONST(0x0000000000000200)\n> #define HPTE_R_KEY\t\t(HPTE_R_KEY_LO | HPTE_R_KEY_HI)\n> \n> #define HPTE_V_1TB_SEG\t\tASM_CONST(0x4000000000000000)\n> diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h\n> index 8e5a87e..04e9221 100644\n> --- a/arch/powerpc/include/asm/mmu_context.h\n> +++ b/arch/powerpc/include/asm/mmu_context.h\n> @@ -150,6 +150,12 @@ static inline int vma_pkey(struct vm_area_struct *vma)\n> {\n> \treturn 0;\n> }\n> +\n> +static inline u64 pte_to_hpte_pkey_bits(u64 pteflags)\n> +{\n> +\treturn 0x0UL;\n> +}\n> +\n> #endif /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n> \n> #endif /* __KERNEL__ */\n> diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h\n> index 0d2488a..cd3924c 100644\n> --- a/arch/powerpc/include/asm/pkeys.h\n> +++ b/arch/powerpc/include/asm/pkeys.h\n> @@ -67,6 +67,19 @@ static inline int vma_pkey(struct vm_area_struct *vma)\n> #define AMR_RD_BIT 0x1UL\n> #define AMR_WR_BIT 0x2UL\n> #define IAMR_EX_BIT 0x1UL\n> +\n> +static inline u64 pte_to_hpte_pkey_bits(u64 pteflags)\n> +{\n> +\tif (!pkey_inited)\n> +\t\treturn 0x0UL;\n> +\n> +\treturn (((pteflags & H_PAGE_PKEY_BIT0) ? HPTE_R_KEY_BIT0 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT1) ? HPTE_R_KEY_BIT1 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT2) ? HPTE_R_KEY_BIT2 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT3) ? HPTE_R_KEY_BIT3 : 0x0UL) |\n> +\t\t((pteflags & H_PAGE_PKEY_BIT4) ? HPTE_R_KEY_BIT4 : 0x0UL));\n> +}\n> +\n> #define ARCH_VM_PKEY_FLAGS (VM_PKEY_BIT0 | VM_PKEY_BIT1 | VM_PKEY_BIT2 | \\\n> \t\t\t\tVM_PKEY_BIT3 | VM_PKEY_BIT4)\n> #define AMR_BITS_PER_PKEY 2\n> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\n> index 67f62b5..a739a2d 100644\n> --- a/arch/powerpc/mm/hash_utils_64.c\n> +++ b/arch/powerpc/mm/hash_utils_64.c\n> @@ -232,6 +232,7 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags)\n> \t\t */\n> \t\trflags |= HPTE_R_M;\n> \n> +\trflags |= pte_to_hpte_pkey_bits(pteflags);\n> \treturn rflags;\n> }\n> \n\n\nLooks good!\n\nAcked-by: Balbir Singh ","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yGzxm6PM4z9t3Z\n\tfor ;\n\tWed, 18 Oct 2017 15:45:00 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yGzxm56jwzDrLC\n\tfor ;\n\tWed, 18 Oct 2017 15:45:00 +1100 (AEDT)","from mail-pg0-x241.google.com (mail-pg0-x241.google.com\n\t[IPv6:2607:f8b0:400e:c05::241])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yGzwB64cqzDrD6\n\tfor ;\n\tWed, 18 Oct 2017 15:43:38 +1100 (AEDT)","by mail-pg0-x241.google.com with SMTP id l24so3249486pgu.11\n\tfor ;\n\tTue, 17 Oct 2017 21:43:38 -0700 (PDT)","from firefly.ozlabs.ibm.com ([122.99.82.10])\n\tby smtp.gmail.com with ESMTPSA id\n\tg11sm22229645pfe.41.2017.10.17.21.43.32\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 17 Oct 2017 21:43:36 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"RZtXm3x0\"; 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