[{"id":1789122,"web_url":"http://patchwork.ozlabs.org/comment/1789122/","msgid":"<20171018153911.3079f0cf@firefly.ozlabs.ibm.com>","date":"2017-10-18T04:39:11","subject":"Re: [PATCH 14/25] powerpc: map vma key-protection bits to pte key\n\tbits.","submitter":{"id":9347,"url":"http://patchwork.ozlabs.org/api/people/9347/","name":"Balbir Singh","email":"bsingharora@gmail.com"},"content":"On Fri, 8 Sep 2017 15:45:02 -0700\nRam Pai wrote:\n\n> map the key protection bits of the vma to the pkey bits in\n> the PTE.\n> \n> The Pte bits used for pkey are 3,4,5,6 and 57. The first\n> four bits are the same four bits that were freed up initially\n> in this patch series. remember? :-) Without those four bits\n> this patch would'nt be possible.\n> \n> BUT, On 4k kernel, bit 3, and 4 could not be freed up. remember?\n> Hence we have to be satisfied with 5,6 and 7.\n> \n> Signed-off-by: Ram Pai \n> ---\n> arch/powerpc/include/asm/book3s/64/pgtable.h | 25 ++++++++++++++++++++++++-\n> arch/powerpc/include/asm/mman.h | 8 ++++++++\n> arch/powerpc/include/asm/pkeys.h | 12 ++++++++++++\n> 3 files changed, 44 insertions(+), 1 deletions(-)\n> \n> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> index 73ed52c..5935d4e 100644\n> --- a/arch/powerpc/include/asm/book3s/64/pgtable.h\n> +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> @@ -38,6 +38,7 @@\n> #define _RPAGE_RSV2\t\t0x0800000000000000UL\n> #define _RPAGE_RSV3\t\t0x0400000000000000UL\n> #define _RPAGE_RSV4\t\t0x0200000000000000UL\n> +#define _RPAGE_RSV5\t\t0x00040UL\n> \n> #define _PAGE_PTE\t\t0x4000000000000000UL\t/* distinguishes PTEs from pointers */\n> #define _PAGE_PRESENT\t\t0x8000000000000000UL\t/* pte contains a translation */\n> @@ -57,6 +58,25 @@\n> /* Max physical address bit as per radix table */\n> #define _RPAGE_PA_MAX\t\t57\n> \n> +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS\n> +#ifdef CONFIG_PPC_64K_PAGES\n> +#define H_PAGE_PKEY_BIT0\t_RPAGE_RSV1\n> +#define H_PAGE_PKEY_BIT1\t_RPAGE_RSV2\n> +#else /* CONFIG_PPC_64K_PAGES */\n> +#define H_PAGE_PKEY_BIT0\t0 /* _RPAGE_RSV1 is not available */\n> +#define H_PAGE_PKEY_BIT1\t0 /* _RPAGE_RSV2 is not available */\n> +#endif /* CONFIG_PPC_64K_PAGES */\n> +#define H_PAGE_PKEY_BIT2\t_RPAGE_RSV3\n> +#define H_PAGE_PKEY_BIT3\t_RPAGE_RSV4\n> +#define H_PAGE_PKEY_BIT4\t_RPAGE_RSV5\n> +#else /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n> +#define H_PAGE_PKEY_BIT0\t0\n> +#define H_PAGE_PKEY_BIT1\t0\n> +#define H_PAGE_PKEY_BIT2\t0\n> +#define H_PAGE_PKEY_BIT3\t0\n> +#define H_PAGE_PKEY_BIT4\t0\n> +#endif /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n\nH_PTE_PKEY_BITX?\n\n> +\n> /*\n> * Max physical address bit we will use for now.\n> *\n> @@ -120,13 +140,16 @@\n> #define _PAGE_CHG_MASK\t(PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \\\n> \t\t\t _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE |\t\\\n> \t\t\t _PAGE_SOFT_DIRTY)\n> +\n> +#define H_PAGE_PKEY (H_PAGE_PKEY_BIT0 | H_PAGE_PKEY_BIT1 | H_PAGE_PKEY_BIT2 | \\\n> +\t\t\tH_PAGE_PKEY_BIT3 | H_PAGE_PKEY_BIT4)\n> /*\n> * Mask of bits returned by pte_pgprot()\n> */\n> #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \\\n> \t\t\t H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \\\n> \t\t\t _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \\\n> -\t\t\t _PAGE_SOFT_DIRTY)\n> +\t\t\t _PAGE_SOFT_DIRTY | H_PAGE_PKEY)\n> /*\n> * We define 2 sets of base prot bits, one for basic pages (ie,\n> * cacheable kernel and user pages) and one for non cacheable\n> diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h\n> index 067eec2..3f7220f 100644\n> --- a/arch/powerpc/include/asm/mman.h\n> +++ b/arch/powerpc/include/asm/mman.h\n> @@ -32,12 +32,20 @@ static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot,\n> }\n> #define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey)\n> \n> +\n> static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)\n> {\n> +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS\n> +\treturn (vm_flags & VM_SAO) ?\n> +\t\t__pgprot(_PAGE_SAO | vmflag_to_page_pkey_bits(vm_flags)) :\n> +\t\t__pgprot(0 | vmflag_to_page_pkey_bits(vm_flags));\n> +#else\n> \treturn (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : __pgprot(0);\n> +#endif\n> }\n> #define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)\n> \n> +\n> static inline bool arch_validate_prot(unsigned long prot)\n> {\n> \tif (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))\n> diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h\n> index d2fffef..0d2488a 100644\n> --- a/arch/powerpc/include/asm/pkeys.h\n> +++ b/arch/powerpc/include/asm/pkeys.h\n> @@ -41,6 +41,18 @@ static inline u64 pkey_to_vmflag_bits(u16 pkey)\n> \t\t((pkey & 0x10UL) ? VM_PKEY_BIT4 : 0x0UL));\n> }\n> \n> +static inline u64 vmflag_to_page_pkey_bits(u64 vm_flags)\n\nvmflag_to_pte_pkey_bits?\n\n> +{\n> +\tif (!pkey_inited)\n> +\t\treturn 0x0UL;\n> +\n> +\treturn (((vm_flags & VM_PKEY_BIT0) ? H_PAGE_PKEY_BIT4 : 0x0UL) |\n> +\t\t((vm_flags & VM_PKEY_BIT1) ? H_PAGE_PKEY_BIT3 : 0x0UL) |\n> +\t\t((vm_flags & VM_PKEY_BIT2) ? H_PAGE_PKEY_BIT2 : 0x0UL) |\n> +\t\t((vm_flags & VM_PKEY_BIT3) ? H_PAGE_PKEY_BIT1 : 0x0UL) |\n> +\t\t((vm_flags & VM_PKEY_BIT4) ? H_PAGE_PKEY_BIT0 : 0x0UL));\n> +}\n> +\n> #define ARCH_VM_PKEY_FLAGS (VM_PKEY_BIT0 | VM_PKEY_BIT1 | VM_PKEY_BIT2 | \\\n> \t\t\t\tVM_PKEY_BIT3 | VM_PKEY_BIT4)\n> \n\nBalbir Singh.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yGzrv6rTjz9s7F\n\tfor ;\n\tWed, 18 Oct 2017 15:40:47 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yGzrv5bX2zDrLB\n\tfor ;\n\tWed, 18 Oct 2017 15:40:47 +1100 (AEDT)","from mail-pg0-x244.google.com (mail-pg0-x244.google.com\n\t[IPv6:2607:f8b0:400e:c05::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yGzqG51zszDrD6\n\tfor ;\n\tWed, 18 Oct 2017 15:39:22 +1100 (AEDT)","by mail-pg0-x244.google.com with SMTP id s75so3251222pgs.0\n\tfor ;\n\tTue, 17 Oct 2017 21:39:22 -0700 (PDT)","from firefly.ozlabs.ibm.com ([122.99.82.10])\n\tby smtp.gmail.com with ESMTPSA id\n\to128sm20980999pfg.118.2017.10.17.21.39.16\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 17 Oct 2017 21:39:20 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"YVu8ERZH\"; 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x86_64-redhat-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"ebiederm@xmission.com, mhocko@kernel.org, paulus@samba.org,\n\taneesh.kumar@linux.vnet.ibm.com, bauerman@linux.vnet.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, khandual@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1789974,"web_url":"http://patchwork.ozlabs.org/comment/1789974/","msgid":"<20171018211433.GJ5617@ram.oc3035372033.ibm.com>","date":"2017-10-18T21:14:33","subject":"Re: [PATCH 14/25] powerpc: map vma key-protection bits to pte key\n\tbits.","submitter":{"id":2667,"url":"http://patchwork.ozlabs.org/api/people/2667/","name":"Ram Pai","email":"linuxram@us.ibm.com"},"content":"On Wed, Oct 18, 2017 at 03:39:11PM +1100, Balbir Singh wrote:\n> On Fri, 8 Sep 2017 15:45:02 -0700\n> Ram Pai wrote:\n> \n> > map the key protection bits of the vma to the pkey bits in\n> > the PTE.\n> > \n> > The Pte bits used for pkey are 3,4,5,6 and 57. The first\n> > four bits are the same four bits that were freed up initially\n> > in this patch series. remember? :-) Without those four bits\n> > this patch would'nt be possible.\n> > \n> > BUT, On 4k kernel, bit 3, and 4 could not be freed up. remember?\n> > Hence we have to be satisfied with 5,6 and 7.\n> > \n> > Signed-off-by: Ram Pai \n> > ---\n> > arch/powerpc/include/asm/book3s/64/pgtable.h | 25 ++++++++++++++++++++++++-\n> > arch/powerpc/include/asm/mman.h | 8 ++++++++\n> > arch/powerpc/include/asm/pkeys.h | 12 ++++++++++++\n> > 3 files changed, 44 insertions(+), 1 deletions(-)\n> > \n> > diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> > index 73ed52c..5935d4e 100644\n> > --- a/arch/powerpc/include/asm/book3s/64/pgtable.h\n> > +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h\n> > @@ -38,6 +38,7 @@\n> > #define _RPAGE_RSV2\t\t0x0800000000000000UL\n> > #define _RPAGE_RSV3\t\t0x0400000000000000UL\n> > #define _RPAGE_RSV4\t\t0x0200000000000000UL\n> > +#define _RPAGE_RSV5\t\t0x00040UL\n> > \n> > #define _PAGE_PTE\t\t0x4000000000000000UL\t/* distinguishes PTEs from pointers */\n> > #define _PAGE_PRESENT\t\t0x8000000000000000UL\t/* pte contains a translation */\n> > @@ -57,6 +58,25 @@\n> > /* Max physical address bit as per radix table */\n> > #define _RPAGE_PA_MAX\t\t57\n> > \n> > +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS\n> > +#ifdef CONFIG_PPC_64K_PAGES\n> > +#define H_PAGE_PKEY_BIT0\t_RPAGE_RSV1\n> > +#define H_PAGE_PKEY_BIT1\t_RPAGE_RSV2\n> > +#else /* CONFIG_PPC_64K_PAGES */\n> > +#define H_PAGE_PKEY_BIT0\t0 /* _RPAGE_RSV1 is not available */\n> > +#define H_PAGE_PKEY_BIT1\t0 /* _RPAGE_RSV2 is not available */\n> > +#endif /* CONFIG_PPC_64K_PAGES */\n> > +#define H_PAGE_PKEY_BIT2\t_RPAGE_RSV3\n> > +#define H_PAGE_PKEY_BIT3\t_RPAGE_RSV4\n> > +#define H_PAGE_PKEY_BIT4\t_RPAGE_RSV5\n> > +#else /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n> > +#define H_PAGE_PKEY_BIT0\t0\n> > +#define H_PAGE_PKEY_BIT1\t0\n> > +#define H_PAGE_PKEY_BIT2\t0\n> > +#define H_PAGE_PKEY_BIT3\t0\n> > +#define H_PAGE_PKEY_BIT4\t0\n> > +#endif /* CONFIG_PPC64_MEMORY_PROTECTION_KEYS */\n> \n> H_PTE_PKEY_BITX?\n\nok. makes sense. will do.\n\n> \n> > +\n> > /*\n> > * Max physical address bit we will use for now.\n> > *\n> > @@ -120,13 +140,16 @@\n> > #define _PAGE_CHG_MASK\t(PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \\\n> > \t\t\t _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE |\t\\\n> > \t\t\t _PAGE_SOFT_DIRTY)\n> > +\n> > +#define H_PAGE_PKEY (H_PAGE_PKEY_BIT0 | H_PAGE_PKEY_BIT1 | H_PAGE_PKEY_BIT2 | \\\n> > +\t\t\tH_PAGE_PKEY_BIT3 | H_PAGE_PKEY_BIT4)\n> > /*\n> > * Mask of bits returned by pte_pgprot()\n> > */\n> > #define PAGE_PROT_BITS (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \\\n> > \t\t\t H_PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \\\n> > \t\t\t _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_EXEC | \\\n> > -\t\t\t _PAGE_SOFT_DIRTY)\n> > +\t\t\t _PAGE_SOFT_DIRTY | H_PAGE_PKEY)\n> > /*\n> > * We define 2 sets of base prot bits, one for basic pages (ie,\n> > * cacheable kernel and user pages) and one for non cacheable\n> > diff --git a/arch/powerpc/include/asm/mman.h b/arch/powerpc/include/asm/mman.h\n> > index 067eec2..3f7220f 100644\n> > --- a/arch/powerpc/include/asm/mman.h\n> > +++ b/arch/powerpc/include/asm/mman.h\n> > @@ -32,12 +32,20 @@ static inline unsigned long arch_calc_vm_prot_bits(unsigned long prot,\n> > }\n> > #define arch_calc_vm_prot_bits(prot, pkey) arch_calc_vm_prot_bits(prot, pkey)\n> > \n> > +\n> > static inline pgprot_t arch_vm_get_page_prot(unsigned long vm_flags)\n> > {\n> > +#ifdef CONFIG_PPC64_MEMORY_PROTECTION_KEYS\n> > +\treturn (vm_flags & VM_SAO) ?\n> > +\t\t__pgprot(_PAGE_SAO | vmflag_to_page_pkey_bits(vm_flags)) :\n> > +\t\t__pgprot(0 | vmflag_to_page_pkey_bits(vm_flags));\n> > +#else\n> > \treturn (vm_flags & VM_SAO) ? __pgprot(_PAGE_SAO) : __pgprot(0);\n> > +#endif\n> > }\n> > #define arch_vm_get_page_prot(vm_flags) arch_vm_get_page_prot(vm_flags)\n> > \n> > +\n> > static inline bool arch_validate_prot(unsigned long prot)\n> > {\n> > \tif (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM | PROT_SAO))\n> > diff --git a/arch/powerpc/include/asm/pkeys.h b/arch/powerpc/include/asm/pkeys.h\n> > index d2fffef..0d2488a 100644\n> > --- a/arch/powerpc/include/asm/pkeys.h\n> > +++ b/arch/powerpc/include/asm/pkeys.h\n> > @@ -41,6 +41,18 @@ static inline u64 pkey_to_vmflag_bits(u16 pkey)\n> > \t\t((pkey & 0x10UL) ? VM_PKEY_BIT4 : 0x0UL));\n> > }\n> > \n> > +static inline u64 vmflag_to_page_pkey_bits(u64 vm_flags)\n> \n> vmflag_to_pte_pkey_bits?\n\nok. if you insist :). will do.\n\n> \n> > +{\n> > +\tif (!pkey_inited)\n> > +\t\treturn 0x0UL;\n> > +\n> > +\treturn (((vm_flags & VM_PKEY_BIT0) ? H_PAGE_PKEY_BIT4 : 0x0UL) |\n> > +\t\t((vm_flags & VM_PKEY_BIT1) ? H_PAGE_PKEY_BIT3 : 0x0UL) |\n> > +\t\t((vm_flags & VM_PKEY_BIT2) ? H_PAGE_PKEY_BIT2 : 0x0UL) |\n> > +\t\t((vm_flags & VM_PKEY_BIT3) ? H_PAGE_PKEY_BIT1 : 0x0UL) |\n> > +\t\t((vm_flags & VM_PKEY_BIT4) ? H_PAGE_PKEY_BIT0 : 0x0UL));\n> > +}\n> > +\n> > #define ARCH_VM_PKEY_FLAGS (VM_PKEY_BIT0 | VM_PKEY_BIT1 | VM_PKEY_BIT2 | \\\n> > \t\t\t\tVM_PKEY_BIT3 | VM_PKEY_BIT4)\n> > \n> \n> Balbir Singh.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yHPxG0ySNz9sBd\n\tfor ;\n\tThu, 19 Oct 2017 08:16:02 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yHPxF6yK0zDqgw\n\tfor ;\n\tThu, 19 Oct 2017 08:16:01 +1100 (AEDT)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yHPvm73mqzDqBr\n\tfor ;\n\tThu, 19 Oct 2017 08:14:44 +1100 (AEDT)","from pps.filterd (m0098399.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv9ILEIWg034353\n\tfor ; Wed, 18 Oct 2017 17:14:43 -0400","from e31.co.us.ibm.com (e31.co.us.ibm.com [32.97.110.149])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2dpax6cprt-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 18 Oct 2017 17:14:42 -0400","from localhost\n\tby e31.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tWed, 18 Oct 2017 15:14:38 -0600","from b03ledav001.gho.boulder.ibm.com\n\t(b03ledav001.gho.boulder.ibm.com [9.17.130.232])\n\tby b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v9ILEcUi31916234; Wed, 18 Oct 2017 14:14:38 -0700","from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id E67AB6E03A;\n\tWed, 18 Oct 2017 15:14:37 -0600 (MDT)","from ram.oc3035372033.ibm.com (unknown [9.85.176.245])\n\tby b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTPS id\n\tC0AB96E03D; Wed, 18 Oct 2017 15:14:35 -0600 (MDT)"],"Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=us.ibm.com\n\t(client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com;\n\tenvelope-from=linuxram@us.ibm.com; receiver=)","Date":"Wed, 18 Oct 2017 14:14:33 -0700","From":"Ram Pai ","To":"Balbir Singh ","Subject":"Re: [PATCH 14/25] powerpc: map vma key-protection bits to pte key\n\tbits.","References":"<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>\n\t<1504910713-7094-23-git-send-email-linuxram@us.ibm.com>\n\t<20171018153911.3079f0cf@firefly.ozlabs.ibm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20171018153911.3079f0cf@firefly.ozlabs.ibm.com>","User-Agent":"Mutt/1.5.20 (2009-12-10)","X-TM-AS-GCONF":"00","x-cbid":"17101821-8235-0000-0000-00000C6E5763","X-IBM-SpamModules-Scores":"","X-IBM-SpamModules-Versions":"BY=3.00007916; HX=3.00000241; KW=3.00000007;\n\tPH=3.00000004; SC=3.00000237; SDB=6.00933067; UDB=6.00469936;\n\tIPR=6.00713357; \n\tBA=6.00005648; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009;\n\tZB=6.00000000; \n\tZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017597;\n\tXFM=3.00000015; UTC=2017-10-18 21:14:40","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17101821-8236-0000-0000-00003E1807B4","Message-Id":"<20171018211433.GJ5617@ram.oc3035372033.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-10-18_08:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1710180295","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Reply-To":"Ram Pai ","Cc":"ebiederm@xmission.com, mhocko@kernel.org, paulus@samba.org,\n\taneesh.kumar@linux.vnet.ibm.com, bauerman@linux.vnet.ibm.com,\n\tlinuxppc-dev@lists.ozlabs.org, khandual@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]