[{"id":1767716,"web_url":"http://patchwork.ozlabs.org/comment/1767716/","msgid":"<CAKTCnz=SYo5NbVWuXWE8+fapW_v65rrEJDWShwofDR6x-X8Wyw@mail.gmail.com>","date":"2017-09-13T09:32:57","subject":"Re: [PATCH 2/7] powerpc: introduce pte_get_hash_gslot() helper","submitter":{"id":9347,"url":"http://patchwork.ozlabs.org/api/people/9347/","name":"Balbir Singh","email":"bsingharora@gmail.com"},"content":"On Sat, Sep 9, 2017 at 8:44 AM, Ram Pai <linuxram@us.ibm.com> wrote:\n> Introduce pte_get_hash_gslot()() which returns the slot number of the\n> HPTE in the global hash table.\n>\n> This function will come in handy as we work towards re-arranging the\n> PTE bits in the later patches.\n>\n> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\n> Signed-off-by: Ram Pai <linuxram@us.ibm.com>\n> ---\n>  arch/powerpc/include/asm/book3s/64/hash.h |    3 +++\n>  arch/powerpc/mm/hash_utils_64.c           |   18 ++++++++++++++++++\n>  2 files changed, 21 insertions(+), 0 deletions(-)\n>\n> diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h\n> index f884520..060c059 100644\n> --- a/arch/powerpc/include/asm/book3s/64/hash.h\n> +++ b/arch/powerpc/include/asm/book3s/64/hash.h\n> @@ -166,6 +166,9 @@ static inline int hash__pte_none(pte_t pte)\n>         return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0;\n>  }\n>\n> +unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,\n> +               int ssize, real_pte_t rpte, unsigned int subpg_index);\n> +\n>  /* This low level function performs the actual PTE insertion\n>   * Setting the PTE depends on the MMU type and other factors. It's\n>   * an horrible mess that I'm not going to try to clean up now but\n> diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\n> index 67ec2e9..e68f053 100644\n> --- a/arch/powerpc/mm/hash_utils_64.c\n> +++ b/arch/powerpc/mm/hash_utils_64.c\n> @@ -1591,6 +1591,24 @@ static inline void tm_flush_hash_page(int local)\n>  }\n>  #endif\n>\n> +/*\n> + * return the global hash slot, corresponding to the given\n> + * pte, which contains the hpte.\n\nDoes this work with native/guest page tables? I guess both.\nThe comment sounds trivial, could you please elaborate more.\nLooking at the code, it seems like given a real pte, we use\nthe hash value and hidx to figure out the slot value in the global\nslot information. This uses information in the software page\ntables. Is that correct? Do we have to consider validity and\npresent state here or is that guaranteed?\n\n> + */\n> +unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,\n> +               int ssize, real_pte_t rpte, unsigned int subpg_index)\n> +{\n> +       unsigned long hash, slot, hidx;\n> +\n> +       hash = hpt_hash(vpn, shift, ssize);\n> +       hidx = __rpte_to_hidx(rpte, subpg_index);\n> +       if (hidx & _PTEIDX_SECONDARY)\n> +               hash = ~hash;\n> +       slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n> +       slot += hidx & _PTEIDX_GROUP_IX;\n> +       return slot;\n> +}\n> +\n>  /* WARNING: This is called from hash_low_64.S, if you change this prototype,\n>   *          do not forget to update the assembly call site !\n>   */\n\nBalbir Singh.","headers":{"Return-Path":"<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsc2T2k6vz9sMN\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 13 Sep 2017 19:34:57 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xsc2T1N7DzDrJq\n\tfor <patchwork-incoming@ozlabs.org>;\n\tWed, 13 Sep 2017 19:34:57 +1000 (AEST)","from mail-vk0-x244.google.com (mail-vk0-x244.google.com\n\t[IPv6:2607:f8b0:400c:c05::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xsc0D6gcPzDqlw\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 13 Sep 2017 19:33:00 +1000 (AEST)","by mail-vk0-x244.google.com with SMTP id t10so3338442vke.2\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tWed, 13 Sep 2017 02:33:00 -0700 (PDT)","by 10.176.75.25 with HTTP; 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charset=\"UTF-8\"","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>","List-Unsubscribe":"<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>","List-Archive":"<http://lists.ozlabs.org/pipermail/linuxppc-dev/>","List-Post":"<mailto:linuxppc-dev@lists.ozlabs.org>","List-Help":"<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>","List-Subscribe":"<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>","Cc":"\"Eric W. Biederman\" <ebiederm@xmission.com>,\n\tMichal Hocko <mhocko@kernel.org>, Paul Mackerras <paulus@samba.org>, \n\tAneesh Kumar KV <aneesh.kumar@linux.vnet.ibm.com>,\n\tThiago Jung Bauermann <bauerman@linux.vnet.ibm.com>,\n\t\"open list:LINUX FOR POWERPC \\(32-BIT AND 64-BIT\\)\"\n\t<linuxppc-dev@lists.ozlabs.org>,\n\tAnshuman Khandual <khandual@linux.vnet.ibm.com>","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>"}},{"id":1768120,"web_url":"http://patchwork.ozlabs.org/comment/1768120/","msgid":"<20170913201006.GA5698@ram.oc3035372033.ibm.com>","date":"2017-09-13T20:10:06","subject":"Re: [PATCH 2/7] powerpc: introduce pte_get_hash_gslot() helper","submitter":{"id":2667,"url":"http://patchwork.ozlabs.org/api/people/2667/","name":"Ram Pai","email":"linuxram@us.ibm.com"},"content":"On Wed, Sep 13, 2017 at 07:32:57PM +1000, Balbir Singh wrote:\n> On Sat, Sep 9, 2017 at 8:44 AM, Ram Pai <linuxram@us.ibm.com> wrote:\n> > Introduce pte_get_hash_gslot()() which returns the slot number of the\n> > HPTE in the global hash table.\n> >\n> > This function will come in handy as we work towards re-arranging the\n> > PTE bits in the later patches.\n> >\n> > Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\n> > Signed-off-by: Ram Pai <linuxram@us.ibm.com>\n> > ---\n> >  arch/powerpc/include/asm/book3s/64/hash.h |    3 +++\n> >  arch/powerpc/mm/hash_utils_64.c           |   18 ++++++++++++++++++\n> >  2 files changed, 21 insertions(+), 0 deletions(-)\n> >\n> > diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h\n> > index f884520..060c059 100644\n> > --- a/arch/powerpc/include/asm/book3s/64/hash.h\n> > +++ b/arch/powerpc/include/asm/book3s/64/hash.h\n> > @@ -166,6 +166,9 @@ static inline int hash__pte_none(pte_t pte)\n> >         return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0;\n> >  }\n> >\n> > +unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,\n> > +               int ssize, real_pte_t rpte, unsigned int subpg_index);\n> > +\n> >  /* This low level function performs the actual PTE insertion\n> >   * Setting the PTE depends on the MMU type and other factors. It's\n> >   * an horrible mess that I'm not going to try to clean up now but\n> > diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c\n> > index 67ec2e9..e68f053 100644\n> > --- a/arch/powerpc/mm/hash_utils_64.c\n> > +++ b/arch/powerpc/mm/hash_utils_64.c\n> > @@ -1591,6 +1591,24 @@ static inline void tm_flush_hash_page(int local)\n> >  }\n> >  #endif\n> >\n> > +/*\n> > + * return the global hash slot, corresponding to the given\n> > + * pte, which contains the hpte.\n> \n> Does this work with native/guest page tables? I guess both.\n\nYes. it is supposed to work with native as well as guest page tables.\nThe code has been this way for ages. This patch encapsulate\nthe logic in a standalone function.\n\n> The comment sounds trivial, could you please elaborate more.\n> Looking at the code, it seems like given a real pte, we use\n> the hash value and hidx to figure out the slot value in the global\n> slot information. This uses information in the software page\n> tables. Is that correct?\n\nYes. This uses information passed to it by the caller, the information\nis expected to be derived from linux page table.\n\n> Do we have to consider validity and\n> present state here or is that guaranteed?\n\nThis function's job is to do the math and return the global slot based\non the input. It will return the calculated value regardless of the validity of\nits inputs.\n\nIts the the callers' job to validate the pte and ensure that it is hashed,\nbefore meaningfully using the return value of the this function.\n\n> \n> > + */\n> > +unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,\n> > +               int ssize, real_pte_t rpte, unsigned int subpg_index)\n> > +{\n> > +       unsigned long hash, slot, hidx;\n> > +\n> > +       hash = hpt_hash(vpn, shift, ssize);\n> > +       hidx = __rpte_to_hidx(rpte, subpg_index);\n> > +       if (hidx & _PTEIDX_SECONDARY)\n> > +               hash = ~hash;\n> > +       slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;\n> > +       slot += hidx & _PTEIDX_GROUP_IX;\n> > +       return slot;\n> > +}\n> > +\n> >  /* WARNING: This is called from hash_low_64.S, if you change this prototype,\n> >   *          do not forget to update the assembly call site !\n> >   */\n> \n> Balbir Singh.","headers":{"Return-Path":"<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xst9K3mtTz9rxj\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 14 Sep 2017 06:11:49 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xst9K2vXWzDrVq\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 14 Sep 2017 06:11:49 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xst7Y4HrJzDqNh\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 14 Sep 2017 06:10:17 +1000 (AEST)","from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8DKA05w038821\n\tfor <linuxppc-dev@lists.ozlabs.org>; Wed, 13 Sep 2017 16:10:14 -0400","from e11.ny.us.ibm.com (e11.ny.us.ibm.com [129.33.205.201])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cy5y4be7c-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Wed, 13 Sep 2017 16:10:14 -0400","from localhost\n\tby e11.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Biederman\" <ebiederm@xmission.com>,\n\tMichal Hocko <mhocko@kernel.org>, Paul Mackerras <paulus@samba.org>, \n\tAneesh Kumar KV <aneesh.kumar@linux.vnet.ibm.com>,\n\tThiago Jung Bauermann <bauerman@linux.vnet.ibm.com>,\n\t\"open list:LINUX FOR POWERPC \\(32-BIT AND 64-BIT\\)\"\n\t<linuxppc-dev@lists.ozlabs.org>,\n\tAnshuman Khandual <khandual@linux.vnet.ibm.com>","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>"}}]