[{"id":1766103,"web_url":"http://patchwork.ozlabs.org/comment/1766103/","msgid":"<4ca41a0a-5298-c1e2-8324-3792981cfe34@ncentric.com>","list_archive_url":null,"date":"2017-09-11T07:41:43","subject":"Re: [LEDE-DEV] [PATCH] cns3xxx: fix GPIO controller interrupt enable","submitter":{"id":69184,"url":"http://patchwork.ozlabs.org/api/people/69184/","name":"Koen Vandeputte","email":"koen.vandeputte@ncentric.com"},"content":"On 2017-09-08 20:56, Tim Harvey wrote:\n> The cns3xxx interrupt controller uses a single register and as such\n> the 'mask' reg/functions must be used as opposed to the 'enable'/'disable'\n> reg/functions.\n>\n> This fixes an issue that occurs if more than one GPIO on a specific controller\n> (there is GPIOA and GPIOB each having 32 GPIO's) uses interrupts. When one\n> would get enabled all others would be disabled prior to this patch.\n>\n> Signed-off-by: Tim Harvey \n> ---\n> target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c | 6 +++---\n> 1 file changed, 3 insertions(+), 3 deletions(-)\n>\n> diff --git a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c\n> index 19de24c..bdf930a 100644\n> --- a/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c\n> +++ b/target/linux/cns3xxx/files/arch/arm/mach-cns3xxx/gpio.c\n> @@ -273,10 +273,10 @@ void __init cns3xxx_gpio_init(int gpio_base, int ngpio,\n> \tct = gc->chip_types;\n> \tct->type = IRQ_TYPE_EDGE_FALLING;\n> \tct->regs.ack = GPIO_INTERRUPT_CLEAR;\n> -\tct->regs.enable = GPIO_INTERRUPT_ENABLE;\n> \tct->chip.irq_ack = irq_gc_ack_set_bit;\n> -\tct->chip.irq_enable = irq_gc_unmask_enable_reg;\n> -\tct->chip.irq_disable = irq_gc_mask_disable_reg;\n> +\tct->regs.mask = GPIO_INTERRUPT_ENABLE;\n> +\tct->chip.irq_enable = irq_gc_mask_set_bit;\n> +\tct->chip.irq_disable = irq_gc_mask_clr_bit;\n> \tct->chip.irq_set_type = cns3xxx_gpio_irq_set_type;\n> \tct->handler = handle_edge_irq;\n> \n\n\nAcked-by: Koen Vandeputte ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; spf=none (mailfrom)\n\tsmtp.mailfrom=lists.infradead.org (client-ip=65.50.211.133;\n\thelo=bombadil.infradead.org;\n\tenvelope-from=lede-dev-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"IjqR5amv\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=infradead.org header.i=@infradead.org\n\theader.b=\"WQKtROFY\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ncentric.com header.i=@ncentric.com\n\theader.b=\"MC1pB1WK\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrKg00DxJz9s7F\n\tfor ;\n\tMon, 11 Sep 2017 17:43:40 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1drJNI-0005ik-32; Mon, 11 Sep 2017 07:43:20 +0000","from merlin.infradead.org ([2001:8b0:10b:1231::1])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1drJNE-0005hj-VV\n\tfor lede-dev@bombadil.infradead.org; Mon, 11 Sep 2017 07:43:17 +0000","from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e])\n\tby merlin.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1drJNB-0000OU-Uk\n\tfor lede-dev@lists.infradead.org; Mon, 11 Sep 2017 07:43:14 +0000","by mail-wm0-x22e.google.com with SMTP id i189so32628271wmf.1\n\tfor ;\n\tMon, 11 Sep 2017 00:42:47 -0700 (PDT)","from [192.168.3.153] (d515300d8.static.telenet.be. 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